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GET /api/patches/118496/?format=api
{ "id": 118496, "url": "https://patches.dpdk.org/api/patches/118496/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221018194131.23006-30-andrew.boyer@amd.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221018194131.23006-30-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221018194131.23006-30-andrew.boyer@amd.com", "date": "2022-10-18T19:41:24", "name": "[v2,29/36] net/ionic: add Q-in-CMB option controlled by devarg", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "e4479503df80c3d977ac7a369c7a792ef618a5ac", "submitter": { "id": 2861, "url": "https://patches.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221018194131.23006-30-andrew.boyer@amd.com/mbox/", "series": [ { "id": 25088, "url": "https://patches.dpdk.org/api/series/25088/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25088", "date": "2022-10-11T00:49:57", "name": "net/ionic: updates for 22.11 release", "version": 1, "mbox": "https://patches.dpdk.org/series/25088/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/118496/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/118496/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EA771A0560;\n\tTue, 18 Oct 2022 21:47:19 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CA1874282F;\n\tTue, 18 Oct 2022 21:47:15 +0200 (CEST)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2059.outbound.protection.outlook.com [40.107.93.59])\n by mails.dpdk.org (Postfix) with ESMTP id 1C01A42B72\n for <dev@dpdk.org>; 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helo=SATLEXMB04.amd.com; pr=C", "From": "Andrew Boyer <andrew.boyer@amd.com>", "To": "<dev@dpdk.org>", "CC": "Andrew Boyer <andrew.boyer@amd.com>, Neel Patel <neel.patel@amd.com>", "Subject": "[PATCH v2 29/36] net/ionic: add Q-in-CMB option controlled by devarg", "Date": "Tue, 18 Oct 2022 12:41:24 -0700", "Message-ID": "<20221018194131.23006-30-andrew.boyer@amd.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20221011005032.47584-1-andrew.boyer@amd.com>", "References": "<20221011005032.47584-1-andrew.boyer@amd.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT025:EE_|SJ0PR12MB6808:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a2c46525-a7ea-49de-f91b-08dab1418c5a", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n OjMpg106b9ebFrC7XdDqyJ2aqJL/x3c5Ufc15B8vpfADaF3iQ9PwyCUfx0TIjLqMRcCi0mQbmkKG+rsFx1AKWvAKkik7CQGycURgU1ATjN9MOzMNjD493A3b0h3ZFIZtmgJnuk/BSREcAFAbbvY8FVKazYqpjKg1bTD/HirL7PkDICoPyTR9Ab6+5a9miyqKGGo8Ieqg29C0IwfkIGmFVGVR9tGvML/fprzWzo6kX8KiVKJIcQqbQTIz5fnIA3eGpO6i9XSIThOdYpNYGH2QI8gOWZ1GZN9pK+wn+YFFvp+SIKg/tmMOuaq3ta3wNZe6YSHYLoBlqYzuGiW8teUR2XHeL4B3wZTBT9GNuwm6HuRx5VVCydcib6lRWJLE6TYOlPAw/U28jG+VWxqm1/aSqGvbqVDF/8LYUPCkmrvxRRK7Np3TwRZ6G3Djm+uMR9tbiF9/oeNfd9h38Fx8zt7WsSQVnEtciYXS4cPWBtH+EFoGwHxQETD2c5TZhcoTBuxL7AQWneVTTTGeeDZV0VhFjXgROtH9JQmNd/EX9W3tIj+1EOevgQAdmFEbpgsxZrHftMiGlB0X20F03/ZZ4I+/0SgT1F7o5KbW1BTFCcg+c2POSUfp1FvqZ/XeWD58UObv0YHhom4emlEeqXTfQMYQf1tOcATWNs8ertxG1IJrqNnsU4r2eXLQBN4h8kzLIvh+gsYHRYcOUTFcMnW6EhLRBgMgNpECNbcSKfCAWMSV2jbH9z2Dyb0vbD2ofM8VmKK99PTZeAfOiRpnp/hKhETgQM+gJtFv/5Nm3tZ9ddkVvXfup0L+WVaaJL2QNA4B1sVF", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230022)(4636009)(396003)(346002)(376002)(39860400002)(136003)(451199015)(46966006)(36840700001)(40470700004)(83380400001)(40480700001)(356005)(81166007)(86362001)(336012)(426003)(47076005)(82310400005)(36756003)(82740400003)(36860700001)(316002)(54906003)(6916009)(6666004)(40460700003)(478600001)(2616005)(8936002)(5660300002)(26005)(2906002)(44832011)(16526019)(30864003)(70206006)(70586007)(41300700001)(8676002)(1076003)(186003)(4326008)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Oct 2022 19:47:11.1171 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a2c46525-a7ea-49de-f91b-08dab1418c5a", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT025.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ0PR12MB6808", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "When 'ionic_cmb' is set to '1', queue memory will be allocated from\nthe device's onboard memory (Controller Memory Buffer). In some\nconfigurations, this will dramatically reduce packet latency and\nincrease PPS.\n\nAdd the WC_ACTIVATE flag to the PCI driver flags.\nWrite combining must be enabled to achieve the maximum PPS.\n\nWhen the queue is in the CMB, descriptors cannot be prefetched.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\nSigned-off-by: Neel Patel <neel.patel@amd.com>\n---\n doc/guides/nics/ionic.rst | 12 ++++++\n doc/guides/rel_notes/release_22_11.rst | 1 +\n drivers/net/ionic/ionic.h | 5 +++\n drivers/net/ionic/ionic_dev.h | 3 ++\n drivers/net/ionic/ionic_dev_pci.c | 60 +++++++++++++++++++++++++-\n drivers/net/ionic/ionic_ethdev.c | 9 ++++\n drivers/net/ionic/ionic_lif.c | 38 ++++++++++++++++\n drivers/net/ionic/ionic_lif.h | 2 +\n drivers/net/ionic/ionic_rxtx.c | 9 ++--\n 9 files changed, 135 insertions(+), 4 deletions(-)", "diff": "diff --git a/doc/guides/nics/ionic.rst b/doc/guides/nics/ionic.rst\nindex 216f820736..e0eb1b5c9a 100644\n--- a/doc/guides/nics/ionic.rst\n+++ b/doc/guides/nics/ionic.rst\n@@ -32,6 +32,18 @@ The ionic PMD requires firmware which supports 16 segment transmit SGLs.\n This support was added prior to version 1.0. For help upgrading older versions,\n please contact AMD Pensando support.\n \n+Runtime Configuration\n+---------------------\n+\n+- ``Queue in CMB support`` (default ``0``)\n+\n+ Queue memory can be allocated from the Controller Memory Buffer (CMB) using\n+ the ``ionic_cmb`` ``devargs`` parameter.\n+\n+ For example::\n+\n+ -a 0000:b5:00.0,ionic_cmb=1\n+\n Building DPDK\n -------------\n \ndiff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst\nindex fcbb3228a4..c98c64d24d 100644\n--- a/doc/guides/rel_notes/release_22_11.rst\n+++ b/doc/guides/rel_notes/release_22_11.rst\n@@ -149,6 +149,7 @@ New Features\n * Added support for mbuf fast free.\n * Added support for advertising packet types.\n * Added support for descriptor status functions.\n+ * Added Q-in-CMB feature controlled by devarg ionic_cmb.\n \n * **Updated Intel iavf driver.**\n \ndiff --git a/drivers/net/ionic/ionic.h b/drivers/net/ionic/ionic.h\nindex 8b0e85ea26..c479eaba74 100644\n--- a/drivers/net/ionic/ionic.h\n+++ b/drivers/net/ionic/ionic.h\n@@ -24,6 +24,9 @@\n #define IONIC_DEV_ID_ETH_VF\t\t0x1003\n #define IONIC_DEV_ID_ETH_MGMT\t\t0x1004\n \n+/* Devargs */\n+#define PMD_IONIC_CMB_KVARG\t\t\"ionic_cmb\"\n+\n enum ionic_mac_type {\n \tIONIC_MAC_UNKNOWN = 0,\n \tIONIC_MAC_CAPRI,\n@@ -62,9 +65,11 @@ struct ionic_adapter {\n \tuint32_t link_speed;\n \tuint32_t nintrs;\n \tbool intrs[IONIC_INTR_CTRL_REGS_MAX];\n+\tbool q_in_cmb;\n \tbool link_up;\n \tchar fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];\n \tvoid *bus_dev;\n+\tuint64_t cmb_offset;\n };\n \n /** ionic_admin_ctx - Admin command context.\ndiff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h\nindex 312f195e58..7ac86396be 100644\n--- a/drivers/net/ionic/ionic_dev.h\n+++ b/drivers/net/ionic/ionic_dev.h\n@@ -176,9 +176,12 @@ struct ionic_adapter;\n struct ionic_qcq;\n struct rte_mempool;\n struct rte_eth_dev;\n+struct rte_devargs;\n \n struct ionic_dev_intf {\n \tint (*setup)(struct ionic_adapter *adapter);\n+\tint (*devargs)(struct ionic_adapter *adapter,\n+\t\t\tstruct rte_devargs *devargs);\n \tvoid (*copy_bus_info)(struct ionic_adapter *adapter,\n \t\t\tstruct rte_eth_dev *eth_dev);\n \tint (*configure_intr)(struct ionic_adapter *adapter);\ndiff --git a/drivers/net/ionic/ionic_dev_pci.c b/drivers/net/ionic/ionic_dev_pci.c\nindex 5366cee56a..5e74a6da71 100644\n--- a/drivers/net/ionic/ionic_dev_pci.c\n+++ b/drivers/net/ionic/ionic_dev_pci.c\n@@ -15,6 +15,7 @@\n #include <rte_eal.h>\n #include <ethdev_pci.h>\n #include <rte_dev.h>\n+#include <rte_kvargs.h>\n \n #include \"ionic.h\"\n #include \"ionic_if.h\"\n@@ -92,6 +93,58 @@ ionic_pci_setup(struct ionic_adapter *adapter)\n \treturn 0;\n }\n \n+const char *ionic_pci_devargs_arr[] = {\n+\tPMD_IONIC_CMB_KVARG,\n+\tNULL,\n+};\n+\n+static int\n+ionic_pci_devarg_cmb(const char *key __rte_unused, const char *val, void *arg)\n+{\n+\tstruct ionic_adapter *adapter = arg;\n+\n+\tif (!strcmp(val, \"1\")) {\n+\t\tIONIC_PRINT(NOTICE, \"%s enabled\", PMD_IONIC_CMB_KVARG);\n+\t\tadapter->q_in_cmb = true;\n+\t} else if (!strcmp(val, \"0\")) {\n+\t\tIONIC_PRINT(DEBUG, \"%s disabled (default)\",\n+\t\t\tPMD_IONIC_CMB_KVARG);\n+\t} else {\n+\t\tIONIC_PRINT(ERR, \"%s=%s invalid, use 1 or 0\",\n+\t\t\tPMD_IONIC_CMB_KVARG, val);\n+\t\treturn -ERANGE;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+ionic_pci_devargs(struct ionic_adapter *adapter, struct rte_devargs *devargs)\n+{\n+\tstruct rte_kvargs *kvlist;\n+\tint err = 0;\n+\n+\tif (!devargs)\n+\t\treturn 0;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, ionic_pci_devargs_arr);\n+\tif (!kvlist) {\n+\t\tIONIC_PRINT(ERR, \"Couldn't parse args '%s'\", devargs->args);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rte_kvargs_count(kvlist, PMD_IONIC_CMB_KVARG) == 1) {\n+\t\terr = rte_kvargs_process(kvlist, PMD_IONIC_CMB_KVARG,\n+\t\t\t\tionic_pci_devarg_cmb, adapter);\n+\t\tif (err < 0)\n+\t\t\tgoto free_kvlist;\n+\t}\n+\n+free_kvlist:\n+\trte_kvargs_free(kvlist);\n+\treturn err;\n+}\n+\n static void\n ionic_pci_copy_bus_info(struct ionic_adapter *adapter,\n \tstruct rte_eth_dev *eth_dev)\n@@ -160,6 +213,7 @@ ionic_pci_unconfigure_intr(struct ionic_adapter *adapter)\n \n static const struct ionic_dev_intf ionic_pci_intf = {\n \t.setup = ionic_pci_setup,\n+\t.devargs = ionic_pci_devargs,\n \t.copy_bus_info = ionic_pci_copy_bus_info,\n \t.configure_intr = ionic_pci_configure_intr,\n \t.unconfigure_intr = ionic_pci_unconfigure_intr,\n@@ -206,7 +260,8 @@ eth_ionic_pci_remove(struct rte_pci_device *pci_dev)\n \n static struct rte_pci_driver rte_pci_ionic_pmd = {\n \t.id_table = pci_id_ionic_map,\n-\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |\n+\t\t\tRTE_PCI_DRV_WC_ACTIVATE,\n \t.probe = eth_ionic_pci_probe,\n \t.remove = eth_ionic_pci_remove,\n };\n@@ -214,3 +269,6 @@ static struct rte_pci_driver rte_pci_ionic_pmd = {\n RTE_PMD_REGISTER_PCI(net_ionic_pci, rte_pci_ionic_pmd);\n RTE_PMD_REGISTER_PCI_TABLE(net_ionic_pci, pci_id_ionic_map);\n RTE_PMD_REGISTER_KMOD_DEP(net_ionic_pci, \"* igb_uio | uio_pci_generic | vfio-pci\");\n+RTE_PMD_REGISTER_PARAM_STRING(net_ionic_pci,\n+\tPMD_IONIC_CMB_KVARG \"=<0|1>\"\n+);\ndiff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c\nindex 393d36d946..0184ffb02e 100644\n--- a/drivers/net/ionic/ionic_ethdev.c\n+++ b/drivers/net/ionic/ionic_ethdev.c\n@@ -1118,6 +1118,15 @@ eth_ionic_dev_probe(void *bus_dev, struct rte_device *rte_dev,\n \n \tadapter->intf = intf;\n \n+\t/* Parse device arguments */\n+\tif (adapter->intf->devargs) {\n+\t\terr = (*adapter->intf->devargs)(adapter, rte_dev->devargs);\n+\t\tif (err) {\n+\t\t\tIONIC_PRINT(ERR, \"Cannot parse device arguments\");\n+\t\t\tgoto err_free_adapter;\n+\t\t}\n+\t}\n+\n \t/* Discover ionic dev resources */\n \terr = ionic_setup(adapter);\n \tif (err) {\ndiff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c\nindex 4305587fe0..db0893acb8 100644\n--- a/drivers/net/ionic/ionic_lif.c\n+++ b/drivers/net/ionic/ionic_lif.c\n@@ -660,6 +660,21 @@ ionic_qcq_alloc(struct ionic_lif *lif,\n \t\tionic_q_sg_map(&new->q, sg_base, sg_base_pa);\n \t}\n \n+\tif (flags & IONIC_QCQ_F_CMB) {\n+\t\t/* alloc descriptor ring from nic memory */\n+\t\tif (lif->adapter->cmb_offset + q_size >\n+\t\t\t\tlif->adapter->bars.bar[2].len) {\n+\t\t\tIONIC_PRINT(ERR, \"Cannot reserve queue from NIC mem\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\tq_base = (void *)\n+\t\t\t((uintptr_t)lif->adapter->bars.bar[2].vaddr +\n+\t\t\t (uintptr_t)lif->adapter->cmb_offset);\n+\t\t/* CMB PA is a relative address */\n+\t\tq_base_pa = lif->adapter->cmb_offset;\n+\t\tlif->adapter->cmb_offset += q_size;\n+\t}\n+\n \tIONIC_PRINT(DEBUG, \"Q-Base-PA = %#jx CQ-Base-PA = %#jx \"\n \t\t\"SG-base-PA = %#jx\",\n \t\tq_base_pa, cq_base_pa, sg_base_pa);\n@@ -744,6 +759,8 @@ ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index,\n \tint err;\n \n \tflags = IONIC_QCQ_F_SG;\n+\tif (lif->state & IONIC_LIF_F_Q_IN_CMB)\n+\t\tflags |= IONIC_QCQ_F_CMB;\n \n \tseg_size = rte_pktmbuf_data_room_size(mb_pool);\n \n@@ -806,6 +823,8 @@ ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index,\n \tint err;\n \n \tflags = IONIC_QCQ_F_SG;\n+\tif (lif->state & IONIC_LIF_F_Q_IN_CMB)\n+\t\tflags |= IONIC_QCQ_F_CMB;\n \n \tnum_segs_fw = IONIC_TX_MAX_SG_ELEMS_V1 + 1;\n \n@@ -994,6 +1013,19 @@ ionic_lif_alloc(struct ionic_lif *lif)\n \t\treturn -ENXIO;\n \t}\n \n+\tif (adapter->q_in_cmb) {\n+\t\tif (adapter->bars.num_bars >= 3 &&\n+\t\t lif->qtype_info[IONIC_QTYPE_RXQ].version >= 2 &&\n+\t\t lif->qtype_info[IONIC_QTYPE_TXQ].version >= 3) {\n+\t\t\tIONIC_PRINT(INFO, \"%s enabled on %s\",\n+\t\t\t\tPMD_IONIC_CMB_KVARG, lif->name);\n+\t\t\tlif->state |= IONIC_LIF_F_Q_IN_CMB;\n+\t\t} else {\n+\t\t\tIONIC_PRINT(ERR, \"%s not supported on %s, disabled\",\n+\t\t\t\tPMD_IONIC_CMB_KVARG, lif->name);\n+\t\t}\n+\t}\n+\n \tIONIC_PRINT(DEBUG, \"Allocating Lif Info\");\n \n \trte_spinlock_init(&lif->adminq_lock);\n@@ -1537,6 +1569,9 @@ ionic_lif_txq_init(struct ionic_tx_qcq *txq)\n \t};\n \tint err;\n \n+\tif (txq->flags & IONIC_QCQ_F_CMB)\n+\t\tctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_CMB);\n+\n \tIONIC_PRINT(DEBUG, \"txq_init.index %d\", q->index);\n \tIONIC_PRINT(DEBUG, \"txq_init.ring_base 0x%\" PRIx64 \"\", q->base_pa);\n \tIONIC_PRINT(DEBUG, \"txq_init.ring_size %d\",\n@@ -1588,6 +1623,9 @@ ionic_lif_rxq_init(struct ionic_rx_qcq *rxq)\n \t};\n \tint err;\n \n+\tif (rxq->flags & IONIC_QCQ_F_CMB)\n+\t\tctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_CMB);\n+\n \tIONIC_PRINT(DEBUG, \"rxq_init.index %d\", q->index);\n \tIONIC_PRINT(DEBUG, \"rxq_init.ring_base 0x%\" PRIx64 \"\", q->base_pa);\n \tIONIC_PRINT(DEBUG, \"rxq_init.ring_size %d\",\ndiff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h\nindex f1cc0f60fc..b9d2e879fb 100644\n--- a/drivers/net/ionic/ionic_lif.h\n+++ b/drivers/net/ionic/ionic_lif.h\n@@ -49,6 +49,7 @@ struct ionic_rx_stats {\n #define IONIC_QCQ_F_INITED\tBIT(0)\n #define IONIC_QCQ_F_SG\t\tBIT(1)\n #define IONIC_QCQ_F_DEFERRED\tBIT(4)\n+#define IONIC_QCQ_F_CMB\t\tBIT(5)\n #define IONIC_QCQ_F_CSUM_L3\tBIT(7)\n #define IONIC_QCQ_F_CSUM_UDP\tBIT(8)\n #define IONIC_QCQ_F_CSUM_TCP\tBIT(9)\n@@ -126,6 +127,7 @@ struct ionic_qtype_info {\n #define IONIC_LIF_F_LINK_CHECK_NEEDED\tBIT(1)\n #define IONIC_LIF_F_UP\t\t\tBIT(2)\n #define IONIC_LIF_F_FW_RESET\t\tBIT(3)\n+#define IONIC_LIF_F_Q_IN_CMB\t\tBIT(4)\n \n #define IONIC_LIF_NAME_MAX_SZ\t\t(32)\n \ndiff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c\nindex 24f498d910..1885c5961e 100644\n--- a/drivers/net/ionic/ionic_rxtx.c\n+++ b/drivers/net/ionic/ionic_rxtx.c\n@@ -600,7 +600,8 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tint err;\n \n \tstruct ionic_txq_desc *desc_base = q->base;\n-\trte_prefetch0(&desc_base[q->head_idx]);\n+\tif (!(txq->flags & IONIC_QCQ_F_CMB))\n+\t\trte_prefetch0(&desc_base[q->head_idx]);\n \trte_prefetch0(IONIC_INFO_PTR(q, q->head_idx));\n \n \tif (tx_pkts) {\n@@ -619,7 +620,8 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \n \twhile (nb_tx < nb_pkts) {\n \t\tuint16_t next_idx = Q_NEXT_TO_POST(q, 1);\n-\t\trte_prefetch0(&desc_base[next_idx]);\n+\t\tif (!(txq->flags & IONIC_QCQ_F_CMB))\n+\t\t\trte_prefetch0(&desc_base[next_idx]);\n \t\trte_prefetch0(IONIC_INFO_PTR(q, next_idx));\n \n \t\tif (nb_tx + 1 < nb_pkts) {\n@@ -1172,7 +1174,8 @@ ionic_rxq_service(struct ionic_rx_qcq *rxq, uint32_t work_to_do,\n \t\t/* Prefetch 4 x 16B comp */\n \t\trte_prefetch0(&cq_desc_base[Q_NEXT_TO_SRVC(cq, 4)]);\n \t\t/* Prefetch 4 x 16B descriptors */\n-\t\trte_prefetch0(&q_desc_base[Q_NEXT_TO_POST(q, 4)]);\n+\t\tif (!(rxq->flags & IONIC_QCQ_F_CMB))\n+\t\t\trte_prefetch0(&q_desc_base[Q_NEXT_TO_POST(q, 4)]);\n \n \t\tionic_rx_clean_one(rxq, cq_desc, rx_svc);\n \n", "prefixes": [ "v2", "29/36" ] }