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{
    "id": 118488,
    "url": "https://patches.dpdk.org/api/patches/118488/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221018194131.23006-22-andrew.boyer@amd.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
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        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
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    "msgid": "<20221018194131.23006-22-andrew.boyer@amd.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20221018194131.23006-22-andrew.boyer@amd.com",
    "date": "2022-10-18T19:41:16",
    "name": "[v2,21/36] net/ionic: overhaul transmit side for performance",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "fb7b17ebe9ce371a6ae763dec560277b2abc61cd",
    "submitter": {
        "id": 2861,
        "url": "https://patches.dpdk.org/api/people/2861/?format=api",
        "name": "Andrew Boyer",
        "email": "Andrew.Boyer@amd.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221018194131.23006-22-andrew.boyer@amd.com/mbox/",
    "series": [
        {
            "id": 25088,
            "url": "https://patches.dpdk.org/api/series/25088/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25088",
            "date": "2022-10-11T00:49:57",
            "name": "net/ionic: updates for 22.11 release",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/25088/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/118488/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/118488/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Andrew Boyer <andrew.boyer@amd.com>",
        "To": "<dev@dpdk.org>",
        "CC": "Andrew Boyer <andrew.boyer@amd.com>",
        "Subject": "[PATCH v2 21/36] net/ionic: overhaul transmit side for performance",
        "Date": "Tue, 18 Oct 2022 12:41:16 -0700",
        "Message-ID": "<20221018194131.23006-22-andrew.boyer@amd.com>",
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    },
    "content": "Linearize Tx mbuf chains in the info array.\nThis avoids walking the mbuf chain during flush.\nMove a few branches out of the hot path.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\n---\n drivers/net/ionic/ionic_lif.c  |   2 +-\n drivers/net/ionic/ionic_rxtx.c | 143 ++++++++++++++++++++-------------\n 2 files changed, 87 insertions(+), 58 deletions(-)",
    "diff": "diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c\nindex ede368d8ca..4305587fe0 100644\n--- a/drivers/net/ionic/ionic_lif.c\n+++ b/drivers/net/ionic/ionic_lif.c\n@@ -817,7 +817,7 @@ ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index,\n \t\t\"tx\",\n \t\tflags,\n \t\tntxq_descs,\n-\t\t1,\n+\t\tnum_segs_fw,\n \t\tsizeof(struct ionic_txq_desc),\n \t\tsizeof(struct ionic_txq_comp),\n \t\tsizeof(struct ionic_txq_sg_desc_v1),\ndiff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c\nindex a4082e9ba4..56701e90d4 100644\n--- a/drivers/net/ionic/ionic_rxtx.c\n+++ b/drivers/net/ionic/ionic_rxtx.c\n@@ -64,7 +64,7 @@ ionic_tx_empty(struct ionic_tx_qcq *txq)\n {\n \tstruct ionic_queue *q = &txq->qcq.q;\n \n-\tionic_empty_array(q->info, q->num_descs, 0);\n+\tionic_empty_array(q->info, q->num_descs * q->num_segs, 0);\n }\n \n static void __rte_cold\n@@ -102,50 +102,49 @@ ionic_tx_flush(struct ionic_tx_qcq *txq)\n {\n \tstruct ionic_cq *cq = &txq->qcq.cq;\n \tstruct ionic_queue *q = &txq->qcq.q;\n-\tstruct rte_mbuf *txm, *next;\n-\tstruct ionic_txq_comp *cq_desc_base = cq->base;\n-\tstruct ionic_txq_comp *cq_desc;\n+\tstruct rte_mbuf *txm;\n+\tstruct ionic_txq_comp *cq_desc, *cq_desc_base = cq->base;\n \tvoid **info;\n-\tu_int32_t comp_index = (u_int32_t)-1;\n+\tuint32_t i;\n \n \tcq_desc = &cq_desc_base[cq->tail_idx];\n+\n \twhile (color_match(cq_desc->color, cq->done_color)) {\n \t\tcq->tail_idx = Q_NEXT_TO_SRVC(cq, 1);\n-\n-\t\t/* Prefetch the next 4 descriptors (not really useful here) */\n-\t\tif ((cq->tail_idx & 0x3) == 0)\n-\t\t\trte_prefetch0(&cq_desc_base[cq->tail_idx]);\n-\n \t\tif (cq->tail_idx == 0)\n \t\t\tcq->done_color = !cq->done_color;\n \n-\t\tcomp_index = cq_desc->comp_index;\n+\t\t/* Prefetch 4 x 16B comp at cq->tail_idx + 4 */\n+\t\tif ((cq->tail_idx & 0x3) == 0)\n+\t\t\trte_prefetch0(&cq_desc_base[Q_NEXT_TO_SRVC(cq, 4)]);\n \n-\t\tcq_desc = &cq_desc_base[cq->tail_idx];\n-\t}\n+\t\twhile (q->tail_idx != rte_le_to_cpu_16(cq_desc->comp_index)) {\n+\t\t\t/* Prefetch 8 mbuf ptrs at q->tail_idx + 2 */\n+\t\t\trte_prefetch0(IONIC_INFO_PTR(q, Q_NEXT_TO_SRVC(q, 2)));\n \n-\tif (comp_index != (u_int32_t)-1) {\n-\t\twhile (q->tail_idx != comp_index) {\n-\t\t\tinfo = IONIC_INFO_PTR(q, q->tail_idx);\n+\t\t\t/* Prefetch next mbuf */\n+\t\t\tvoid **next_info =\n+\t\t\t\tIONIC_INFO_PTR(q, Q_NEXT_TO_SRVC(q, 1));\n+\t\t\tif (next_info[0])\n+\t\t\t\trte_mbuf_prefetch_part2(next_info[0]);\n+\t\t\tif (next_info[1])\n+\t\t\t\trte_mbuf_prefetch_part2(next_info[1]);\n \n-\t\t\tq->tail_idx = Q_NEXT_TO_SRVC(q, 1);\n+\t\t\tinfo = IONIC_INFO_PTR(q, q->tail_idx);\n+\t\t\tfor (i = 0; i < q->num_segs; i++) {\n+\t\t\t\ttxm = info[i];\n+\t\t\t\tif (!txm)\n+\t\t\t\t\tbreak;\n \n-\t\t\t/* Prefetch the next 4 descriptors */\n-\t\t\tif ((q->tail_idx & 0x3) == 0)\n-\t\t\t\t/* q desc info */\n-\t\t\t\trte_prefetch0(&q->info[q->tail_idx]);\n-\n-\t\t\t/*\n-\t\t\t * Note: you can just use rte_pktmbuf_free,\n-\t\t\t * but this loop is faster\n-\t\t\t */\n-\t\t\ttxm = info[0];\n-\t\t\twhile (txm != NULL) {\n-\t\t\t\tnext = txm->next;\n \t\t\t\trte_pktmbuf_free_seg(txm);\n-\t\t\t\ttxm = next;\n+\n+\t\t\t\tinfo[i] = NULL;\n \t\t\t}\n+\n+\t\t\tq->tail_idx = Q_NEXT_TO_SRVC(q, 1);\n \t\t}\n+\n+\t\tcq_desc = &cq_desc_base[cq->tail_idx];\n \t}\n }\n \n@@ -327,9 +326,12 @@ ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc,\n \t\tuint16_t vlan_tci, bool has_vlan,\n \t\tbool start, bool done)\n {\n+\tstruct rte_mbuf *txm_seg;\n \tvoid **info;\n \tuint64_t cmd;\n \tuint8_t flags = 0;\n+\tint i;\n+\n \tflags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;\n \tflags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;\n \tflags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0;\n@@ -345,7 +347,13 @@ ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc,\n \n \tif (done) {\n \t\tinfo = IONIC_INFO_PTR(q, q->head_idx);\n-\t\tinfo[0] = txm;\n+\n+\t\t/* Walk the mbuf chain to stash pointers in the array */\n+\t\ttxm_seg = txm;\n+\t\tfor (i = 0; i < txm->nb_segs; i++) {\n+\t\t\tinfo[i] = txm_seg;\n+\t\t\ttxm_seg = txm_seg->next;\n+\t\t}\n \t}\n \n \tq->head_idx = Q_NEXT_TO_POST(q, 1);\n@@ -497,8 +505,7 @@ ionic_tx(struct ionic_tx_qcq *txq, struct rte_mbuf *txm)\n \tstruct ionic_tx_stats *stats = &txq->stats;\n \tstruct rte_mbuf *txm_seg;\n \tvoid **info;\n-\tbool encap;\n-\tbool has_vlan;\n+\trte_iova_t data_iova;\n \tuint64_t ol_flags = txm->ol_flags;\n \tuint64_t addr, cmd;\n \tuint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE;\n@@ -524,32 +531,44 @@ ionic_tx(struct ionic_tx_qcq *txq, struct rte_mbuf *txm)\n \tif (opcode == IONIC_TXQ_DESC_OPCODE_CSUM_NONE)\n \t\tstats->no_csum++;\n \n-\thas_vlan = (ol_flags & RTE_MBUF_F_TX_VLAN);\n-\tencap = ((ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM) ||\n-\t\t\t(ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM)) &&\n-\t\t\t((ol_flags & RTE_MBUF_F_TX_OUTER_IPV4) ||\n-\t\t\t (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6));\n+\tif (((ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM) ||\n+\t     (ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM)) &&\n+\t    ((ol_flags & RTE_MBUF_F_TX_OUTER_IPV4) ||\n+\t     (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6))) {\n+\t\tflags |= IONIC_TXQ_DESC_FLAG_ENCAP;\n+\t}\n \n-\tflags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;\n-\tflags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;\n+\tif (ol_flags & RTE_MBUF_F_TX_VLAN) {\n+\t\tflags |= IONIC_TXQ_DESC_FLAG_VLAN;\n+\t\tdesc->vlan_tci = rte_cpu_to_le_16(txm->vlan_tci);\n+\t}\n \n \taddr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm));\n \n \tcmd = encode_txq_desc_cmd(opcode, flags, txm->nb_segs - 1, addr);\n \tdesc->cmd = rte_cpu_to_le_64(cmd);\n \tdesc->len = rte_cpu_to_le_16(txm->data_len);\n-\tdesc->vlan_tci = rte_cpu_to_le_16(txm->vlan_tci);\n \n \tinfo[0] = txm;\n \n-\telem = sg_desc_base[q->head_idx].elems;\n+\tif (txm->nb_segs > 1) {\n+\t\ttxm_seg = txm->next;\n \n-\ttxm_seg = txm->next;\n-\twhile (txm_seg != NULL) {\n-\t\telem->len = rte_cpu_to_le_16(txm_seg->data_len);\n-\t\telem->addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm_seg));\n-\t\telem++;\n-\t\ttxm_seg = txm_seg->next;\n+\t\telem = sg_desc_base[q->head_idx].elems;\n+\n+\t\twhile (txm_seg != NULL) {\n+\t\t\t/* Stash the mbuf ptr in the array */\n+\t\t\tinfo++;\n+\t\t\t*info = txm_seg;\n+\n+\t\t\t/* Configure the SGE */\n+\t\t\tdata_iova = rte_mbuf_data_iova(txm_seg);\n+\t\t\telem->len = rte_cpu_to_le_16(txm_seg->data_len);\n+\t\t\telem->addr = rte_cpu_to_le_64(data_iova);\n+\t\t\telem++;\n+\n+\t\t\ttxm_seg = txm_seg->next;\n+\t\t}\n \t}\n \n \tq->head_idx = Q_NEXT_TO_POST(q, 1);\n@@ -565,11 +584,19 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tstruct ionic_queue *q = &txq->qcq.q;\n \tstruct ionic_tx_stats *stats = &txq->stats;\n \tstruct rte_mbuf *mbuf;\n-\tuint32_t next_q_head_idx;\n \tuint32_t bytes_tx = 0;\n \tuint16_t nb_avail, nb_tx = 0;\n \tint err;\n \n+\tstruct ionic_txq_desc *desc_base = q->base;\n+\trte_prefetch0(&desc_base[q->head_idx]);\n+\trte_prefetch0(IONIC_INFO_PTR(q, q->head_idx));\n+\n+\tif (tx_pkts) {\n+\t\trte_mbuf_prefetch_part1(tx_pkts[0]);\n+\t\trte_mbuf_prefetch_part2(tx_pkts[0]);\n+\t}\n+\n \t/* Cleaning old buffers */\n \tionic_tx_flush(txq);\n \n@@ -580,11 +607,13 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t}\n \n \twhile (nb_tx < nb_pkts) {\n-\t\tnext_q_head_idx = Q_NEXT_TO_POST(q, 1);\n-\t\tif ((next_q_head_idx & 0x3) == 0) {\n-\t\t\tstruct ionic_txq_desc *desc_base = q->base;\n-\t\t\trte_prefetch0(&desc_base[next_q_head_idx]);\n-\t\t\trte_prefetch0(&q->info[next_q_head_idx]);\n+\t\tuint16_t next_idx = Q_NEXT_TO_POST(q, 1);\n+\t\trte_prefetch0(&desc_base[next_idx]);\n+\t\trte_prefetch0(IONIC_INFO_PTR(q, next_idx));\n+\n+\t\tif (nb_tx + 1 < nb_pkts) {\n+\t\t\trte_mbuf_prefetch_part1(tx_pkts[nb_tx + 1]);\n+\t\t\trte_mbuf_prefetch_part2(tx_pkts[nb_tx + 1]);\n \t\t}\n \n \t\tmbuf = tx_pkts[nb_tx];\n@@ -605,10 +634,10 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tif (nb_tx > 0) {\n \t\trte_wmb();\n \t\tionic_q_flush(q);\n-\t}\n \n-\tstats->packets += nb_tx;\n-\tstats->bytes += bytes_tx;\n+\t\tstats->packets += nb_tx;\n+\t\tstats->bytes += bytes_tx;\n+\t}\n \n \treturn nb_tx;\n }\n",
    "prefixes": [
        "v2",
        "21/36"
    ]
}