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GET /api/patches/118483/?format=api
{ "id": 118483, "url": "https://patches.dpdk.org/api/patches/118483/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221018194131.23006-18-andrew.boyer@amd.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221018194131.23006-18-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221018194131.23006-18-andrew.boyer@amd.com", "date": "2022-10-18T19:41:12", "name": "[v2,17/36] net/ionic: precalculate segment lengths on receive side", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "51641f3c41ca13a165fc2342900555914ed9ebb3", "submitter": { "id": 2861, "url": "https://patches.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221018194131.23006-18-andrew.boyer@amd.com/mbox/", "series": [ { "id": 25088, "url": "https://patches.dpdk.org/api/series/25088/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25088", "date": "2022-10-11T00:49:57", "name": "net/ionic: updates for 22.11 release", "version": 1, "mbox": "https://patches.dpdk.org/series/25088/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/118483/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/118483/checks/", "tags": {}, "related": [], "headers": { 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SFS:(13230022)(4636009)(39860400002)(136003)(396003)(346002)(376002)(451199015)(46966006)(36840700001)(40470700004)(82310400005)(44832011)(356005)(81166007)(83380400001)(47076005)(316002)(70586007)(40480700001)(70206006)(426003)(2616005)(26005)(478600001)(5660300002)(8936002)(36756003)(82740400003)(16526019)(86362001)(1076003)(36860700001)(6916009)(4326008)(8676002)(41300700001)(186003)(2906002)(336012)(40460700003)(6666004)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Oct 2022 19:45:31.0258 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 99528f1c-3ee9-41fd-175a-08dab14150ab", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT016.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB5104", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The first (header) segment includes the standard headroom.\nSubsequent segments do not.\n\nStore the fragment counts in the queue structure.\n\nPrecalculating improves performance by reducing\nhow much work must be done in the hot path.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\n---\n drivers/net/ionic/ionic_dev.h | 1 +\n drivers/net/ionic/ionic_lif.c | 36 ++++++++++++++++++++++++--\n drivers/net/ionic/ionic_lif.h | 4 ++-\n drivers/net/ionic/ionic_rxtx.c | 46 ++++++++++++++--------------------\n 4 files changed, 57 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h\nindex b77de30de1..aff49ae34d 100644\n--- a/drivers/net/ionic/ionic_dev.h\n+++ b/drivers/net/ionic/ionic_dev.h\n@@ -137,6 +137,7 @@ struct ionic_dev {\n \n struct ionic_queue {\n \tuint16_t num_descs;\n+\tuint16_t num_segs;\n \tuint16_t head_idx;\n \tuint16_t tail_idx;\n \tuint16_t size_mask;\ndiff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c\nindex e7cb9e2ea3..2bc2362453 100644\n--- a/drivers/net/ionic/ionic_lif.c\n+++ b/drivers/net/ionic/ionic_lif.c\n@@ -566,6 +566,7 @@ ionic_qcq_alloc(struct ionic_lif *lif,\n \t\tconst char *type_name,\n \t\tuint16_t flags,\n \t\tuint16_t num_descs,\n+\t\tuint16_t num_segs,\n \t\tuint16_t desc_size,\n \t\tuint16_t cq_desc_size,\n \t\tuint16_t sg_desc_size,\n@@ -616,6 +617,7 @@ ionic_qcq_alloc(struct ionic_lif *lif,\n \t\tgoto err_out_free_qcq;\n \t}\n \n+\tnew->q.num_segs = num_segs;\n \tnew->q.type = type;\n \n \terr = ionic_q_init(&new->q, index, num_descs);\n@@ -698,14 +700,38 @@ ionic_qcq_free(struct ionic_qcq *qcq)\n \n int\n ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index,\n-\t\tuint16_t nrxq_descs, struct ionic_rx_qcq **rxq_out)\n+\t\tuint16_t nrxq_descs, struct rte_mempool *mb_pool,\n+\t\tstruct ionic_rx_qcq **rxq_out)\n {\n \tstruct ionic_rx_qcq *rxq;\n-\tuint16_t flags;\n+\tuint16_t flags, seg_size, hdr_seg_size, max_segs, max_segs_fw;\n+\tuint32_t max_mtu;\n \tint err;\n \n \tflags = IONIC_QCQ_F_SG;\n \n+\tseg_size = rte_pktmbuf_data_room_size(mb_pool);\n+\n+\t/* The first mbuf needs to leave headroom */\n+\thdr_seg_size = seg_size - RTE_PKTMBUF_HEADROOM;\n+\n+\tmax_mtu = rte_le_to_cpu_32(lif->adapter->ident.lif.eth.max_mtu);\n+\n+\tmax_segs_fw = IONIC_RX_MAX_SG_ELEMS + 1;\n+\n+\t/*\n+\t * Calculate how many fragment pointers might be stored in queue.\n+\t */\n+\tmax_segs = 1 + (max_mtu + RTE_PKTMBUF_HEADROOM - 1) / seg_size;\n+\n+\tIONIC_PRINT(DEBUG, \"rxq %u frame_size %u seg_size %u max_segs %u\",\n+\t\tindex, lif->frame_size, seg_size, max_segs);\n+\tif (max_segs > max_segs_fw) {\n+\t\tIONIC_PRINT(ERR, \"Rx mbuf size insufficient (%d > %d avail)\",\n+\t\t\tmax_segs, max_segs_fw);\n+\t\treturn -EINVAL;\n+\t}\n+\n \terr = ionic_qcq_alloc(lif,\n \t\tIONIC_QTYPE_RXQ,\n \t\tsizeof(struct ionic_rx_qcq),\n@@ -714,6 +740,7 @@ ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index,\n \t\t\"rx\",\n \t\tflags,\n \t\tnrxq_descs,\n+\t\tmax_segs,\n \t\tsizeof(struct ionic_rxq_desc),\n \t\tsizeof(struct ionic_rxq_comp),\n \t\tsizeof(struct ionic_rxq_sg_desc),\n@@ -722,6 +749,8 @@ ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index,\n \t\treturn err;\n \n \trxq->flags = flags;\n+\trxq->seg_size = seg_size;\n+\trxq->hdr_seg_size = hdr_seg_size;\n \n \tlif->rxqcqs[index] = rxq;\n \t*rxq_out = rxq;\n@@ -749,6 +778,7 @@ ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index,\n \t\t\"tx\",\n \t\tflags,\n \t\tntxq_descs,\n+\t\t1,\n \t\tsizeof(struct ionic_txq_desc),\n \t\tsizeof(struct ionic_txq_comp),\n \t\tsizeof(struct ionic_txq_sg_desc_v1),\n@@ -779,6 +809,7 @@ ionic_admin_qcq_alloc(struct ionic_lif *lif)\n \t\t\"admin\",\n \t\tflags,\n \t\tIONIC_ADMINQ_LENGTH,\n+\t\t1,\n \t\tsizeof(struct ionic_admin_cmd),\n \t\tsizeof(struct ionic_admin_comp),\n \t\t0,\n@@ -805,6 +836,7 @@ ionic_notify_qcq_alloc(struct ionic_lif *lif)\n \t\t\"notify\",\n \t\tflags,\n \t\tIONIC_NOTIFYQ_LENGTH,\n+\t\t1,\n \t\tsizeof(struct ionic_notifyq_cmd),\n \t\tsizeof(union ionic_notifyq_comp),\n \t\t0,\ndiff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h\nindex a8f7458327..8650200ec7 100644\n--- a/drivers/net/ionic/ionic_lif.h\n+++ b/drivers/net/ionic/ionic_lif.h\n@@ -81,6 +81,8 @@ struct ionic_rx_qcq {\n \t/* cacheline2 */\n \tstruct rte_mempool *mb_pool;\n \tuint16_t frame_size;\t/* Based on configured MTU */\n+\tuint16_t hdr_seg_size;\t/* Length of first segment of RX chain */\n+\tuint16_t seg_size;\t/* Length of all subsequent segments */\n \tuint16_t flags;\n \n \t/* cacheline3 (inside stats) */\n@@ -199,7 +201,7 @@ int ionic_dev_allmulticast_enable(struct rte_eth_dev *dev);\n int ionic_dev_allmulticast_disable(struct rte_eth_dev *dev);\n \n int ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id,\n-\tuint32_t index, uint16_t nrxq_descs,\n+\tuint32_t index, uint16_t nrxq_descs, struct rte_mempool *mp,\n \tstruct ionic_rx_qcq **qcq_out);\n int ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id,\n \tuint32_t index, uint16_t ntxq_descs,\ndiff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c\nindex b2c3639e51..27678ccb6e 100644\n--- a/drivers/net/ionic/ionic_rxtx.c\n+++ b/drivers/net/ionic/ionic_rxtx.c\n@@ -732,7 +732,7 @@ ionic_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,\n \teth_dev->data->rx_queue_state[rx_queue_id] =\n \t\tRTE_ETH_QUEUE_STATE_STOPPED;\n \n-\terr = ionic_rx_qcq_alloc(lif, socket_id, rx_queue_id, nb_desc,\n+\terr = ionic_rx_qcq_alloc(lif, socket_id, rx_queue_id, nb_desc, mp,\n \t\t\t&rxq);\n \tif (err) {\n \t\tIONIC_PRINT(ERR, \"Queue %d allocation failure\", rx_queue_id);\n@@ -773,9 +773,6 @@ ionic_rx_clean(struct ionic_rx_qcq *rxq,\n \tuint64_t pkt_flags = 0;\n \tuint32_t pkt_type;\n \tstruct ionic_rx_stats *stats = &rxq->stats;\n-\tuint32_t buf_size = (uint16_t)\n-\t\t(rte_pktmbuf_data_room_size(rxq->mb_pool) -\n-\t\tRTE_PKTMBUF_HEADROOM);\n \tuint32_t left;\n \tvoid **info;\n \n@@ -809,14 +806,12 @@ ionic_rx_clean(struct ionic_rx_qcq *rxq,\n \trxm->pkt_len = cq_desc->len;\n \trxm->port = rxq->qcq.lif->port_id;\n \n-\tleft = cq_desc->len;\n-\n-\trxm->data_len = RTE_MIN(buf_size, left);\n-\tleft -= rxm->data_len;\n+\trxm->data_len = RTE_MIN(rxq->hdr_seg_size, cq_desc->len);\n+\tleft = cq_desc->len - rxm->data_len;\n \n \trxm_seg = rxm->next;\n \twhile (rxm_seg && left) {\n-\t\trxm_seg->data_len = RTE_MIN(buf_size, left);\n+\t\trxm_seg->data_len = RTE_MIN(rxq->seg_size, left);\n \t\tleft -= rxm_seg->data_len;\n \n \t\trxm_seg = rxm_seg->next;\n@@ -926,10 +921,7 @@ ionic_rx_fill(struct ionic_rx_qcq *rxq)\n \tstruct ionic_rxq_sg_elem *elem;\n \tvoid **info;\n \trte_iova_t dma_addr;\n-\tuint32_t i, j, nsegs, buf_size, size;\n-\n-\tbuf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -\n-\t\tRTE_PKTMBUF_HEADROOM);\n+\tuint32_t i, j;\n \n \t/* Initialize software ring entries */\n \tfor (i = ionic_q_space_avail(q); i; i--) {\n@@ -943,21 +935,18 @@ ionic_rx_fill(struct ionic_rx_qcq *rxq)\n \n \t\tinfo = IONIC_INFO_PTR(q, q->head_idx);\n \n-\t\tnsegs = (rxq->frame_size + buf_size - 1) / buf_size;\n-\n \t\tdesc = &desc_base[q->head_idx];\n \t\tdma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(rxm));\n \t\tdesc->addr = dma_addr;\n-\t\tdesc->len = buf_size;\n-\t\tsize = buf_size;\n-\t\tdesc->opcode = (nsegs > 1) ? IONIC_RXQ_DESC_OPCODE_SG :\n+\t\tdesc->len = rxq->hdr_seg_size;\n+\t\tdesc->opcode = (q->num_segs > 1) ? IONIC_RXQ_DESC_OPCODE_SG :\n \t\t\tIONIC_RXQ_DESC_OPCODE_SIMPLE;\n \t\trxm->next = NULL;\n \n \t\tprev_rxm_seg = rxm;\n \t\tsg_desc = &sg_desc_base[q->head_idx];\n \t\telem = sg_desc->elems;\n-\t\tfor (j = 0; j < nsegs - 1 && j < IONIC_RX_MAX_SG_ELEMS; j++) {\n+\t\tfor (j = 0; j < q->num_segs - 1u; j++) {\n \t\t\tstruct rte_mbuf *rxm_seg;\n \t\t\trte_iova_t data_iova;\n \n@@ -967,21 +956,18 @@ ionic_rx_fill(struct ionic_rx_qcq *rxq)\n \t\t\t\treturn -ENOMEM;\n \t\t\t}\n \n+\t\t\trxm_seg->data_off = 0;\n \t\t\tdata_iova = rte_mbuf_data_iova(rxm_seg);\n \t\t\tdma_addr = rte_cpu_to_le_64(data_iova);\n \t\t\telem->addr = dma_addr;\n-\t\t\telem->len = buf_size;\n-\t\t\tsize += buf_size;\n+\t\t\telem->len = rxq->seg_size;\n \t\t\telem++;\n+\n \t\t\trxm_seg->next = NULL;\n \t\t\tprev_rxm_seg->next = rxm_seg;\n \t\t\tprev_rxm_seg = rxm_seg;\n \t\t}\n \n-\t\tif (size < rxq->frame_size)\n-\t\t\tIONIC_PRINT(ERR, \"Rx SG size is not sufficient (%d < %d)\",\n-\t\t\t\tsize, rxq->frame_size);\n-\n \t\tinfo[0] = rxm;\n \n \t\tq->head_idx = Q_NEXT_TO_POST(q, 1);\n@@ -1000,6 +986,7 @@ ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)\n {\n \tuint8_t *rx_queue_state = eth_dev->data->rx_queue_state;\n \tstruct ionic_rx_qcq *rxq;\n+\tstruct ionic_queue *q;\n \tint err;\n \n \tif (rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED) {\n@@ -1009,11 +996,16 @@ ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)\n \t}\n \n \trxq = eth_dev->data->rx_queues[rx_queue_id];\n+\tq = &rxq->qcq.q;\n \n \trxq->frame_size = rxq->qcq.lif->frame_size - RTE_ETHER_CRC_LEN;\n \n-\tIONIC_PRINT(DEBUG, \"Starting RX queue %u, %u descs, size %u\",\n-\t\trx_queue_id, rxq->qcq.q.num_descs, rxq->frame_size);\n+\t/* Recalculate segment count based on MTU */\n+\tq->num_segs = 1 +\n+\t\t(rxq->frame_size + RTE_PKTMBUF_HEADROOM - 1) / rxq->seg_size;\n+\n+\tIONIC_PRINT(DEBUG, \"Starting RX queue %u, %u descs, size %u segs %u\",\n+\t\trx_queue_id, q->num_descs, rxq->frame_size, q->num_segs);\n \n \terr = ionic_lif_rxq_init(rxq);\n \tif (err)\n", "prefixes": [ "v2", "17/36" ] }