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{
    "id": 118460,
    "url": "https://patches.dpdk.org/api/patches/118460/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221019003918.257506-26-hernan.vargas@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
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        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20221019003918.257506-26-hernan.vargas@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20221019003918.257506-26-hernan.vargas@intel.com",
    "date": "2022-10-19T00:39:13",
    "name": "[v4,25/30] baseband/acc100: store FCW from first CB descriptor",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "0fb36fe3b2ab7e01f7c3e81e2eae8518ee03a952",
    "submitter": {
        "id": 2659,
        "url": "https://patches.dpdk.org/api/people/2659/?format=api",
        "name": "Hernan Vargas",
        "email": "hernan.vargas@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "https://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221019003918.257506-26-hernan.vargas@intel.com/mbox/",
    "series": [
        {
            "id": 25287,
            "url": "https://patches.dpdk.org/api/series/25287/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25287",
            "date": "2022-10-19T00:38:48",
            "name": "baseband/acc100: changes for 22.11",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/25287/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/118460/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/118460/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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            "E=McAfee;i=\"6500,9779,10504\"; a=\"368192134\"",
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            "E=McAfee;i=\"6500,9779,10504\"; a=\"803836147\"",
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        "X-ExtLoop1": "1",
        "From": "Hernan Vargas <hernan.vargas@intel.com>",
        "To": "dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,\n maxime.coquelin@redhat.com",
        "Cc": "nicolas.chautru@intel.com, qi.z.zhang@intel.com,\n Hernan Vargas <hernan.vargas@intel.com>",
        "Subject": "[PATCH v4 25/30] baseband/acc100: store FCW from first CB descriptor",
        "Date": "Tue, 18 Oct 2022 17:39:13 -0700",
        "Message-Id": "<20221019003918.257506-26-hernan.vargas@intel.com>",
        "X-Mailer": "git-send-email 2.37.1",
        "In-Reply-To": "<20221019003918.257506-1-hernan.vargas@intel.com>",
        "References": "<20221019003918.257506-1-hernan.vargas@intel.com>",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Store the descriptor from the first code block from a transport block.\nCopy the LDPC FCW from the first descriptor into the rest of the CBs in\nthat TB.\n\nSigned-off-by: Hernan Vargas <hernan.vargas@intel.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n drivers/baseband/acc/rte_acc100_pmd.c | 3 +++\n 1 file changed, 3 insertions(+)",
    "diff": "diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c\nindex e00a636d9f..ed5ee63950 100644\n--- a/drivers/baseband/acc/rte_acc100_pmd.c\n+++ b/drivers/baseband/acc/rte_acc100_pmd.c\n@@ -3188,6 +3188,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n \t\tuint16_t total_enqueued_cbs, uint8_t cbs_in_tb)\n {\n \tunion acc_dma_desc *desc = NULL;\n+\tunion acc_dma_desc *desc_first = NULL;\n \tint ret;\n \tuint8_t r, c;\n \tuint32_t in_offset, h_out_offset,\n@@ -3207,6 +3208,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n \n \tdesc_idx = acc_desc_idx(q, total_enqueued_cbs);\n \tdesc = q->ring_addr + desc_idx;\n+\tdesc_first = desc;\n \tfcw_offset = (desc_idx << 8) + ACC_DESC_FCW_OFFSET;\n \tharq_layout = q->d->harq_layout;\n \tq->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);\n@@ -3229,6 +3231,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n \t\tdesc = acc_desc(q, total_enqueued_cbs);\n \t\tdesc->req.data_ptrs[0].address = q->ring_addr_iova + fcw_offset;\n \t\tdesc->req.data_ptrs[0].blen = ACC_FCW_LD_BLEN;\n+\t\trte_memcpy(&desc->req.fcw_ld, &desc_first->req.fcw_ld, ACC_FCW_LD_BLEN);\n \t\tret = acc100_dma_desc_ld_fill(op, &desc->req, &input,\n \t\t\t\th_output, &in_offset, &h_out_offset,\n \t\t\t\t&h_out_length,\n",
    "prefixes": [
        "v4",
        "25/30"
    ]
}