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GET /api/patches/118452/?format=api
https://patches.dpdk.org/api/patches/118452/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221019003918.257506-18-hernan.vargas@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221019003918.257506-18-hernan.vargas@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221019003918.257506-18-hernan.vargas@intel.com", "date": "2022-10-19T00:39:05", "name": "[v4,17/30] baseband/acc100: add HARQ index helper function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a977db2f5859fa968aef46b6f18e2baa32ef5022", "submitter": { "id": 2659, "url": "https://patches.dpdk.org/api/people/2659/?format=api", "name": "Hernan Vargas", "email": "hernan.vargas@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221019003918.257506-18-hernan.vargas@intel.com/mbox/", "series": [ { "id": 25287, "url": "https://patches.dpdk.org/api/series/25287/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25287", "date": "2022-10-19T00:38:48", "name": "baseband/acc100: changes for 22.11", "version": 4, "mbox": "https://patches.dpdk.org/series/25287/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/118452/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/118452/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 11DC2A0560;\n\tTue, 18 Oct 2022 18:44:37 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D8EB742B90;\n\tTue, 18 Oct 2022 18:43:07 +0200 (CEST)", "from mga06.intel.com (mga06b.intel.com [134.134.136.31])\n by mails.dpdk.org (Postfix) with ESMTP id 17844427F9\n for <dev@dpdk.org>; Tue, 18 Oct 2022 18:42:56 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Oct 2022 09:42:56 -0700", "from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103])\n by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:55 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1666111377; x=1697647377;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=4Gza2lgLVnc+AKnEvMYkxN5QsSl4HGtPC4UGcnVbpwA=;\n b=CD0gKSWM/oaqDAXW/sF2ZeLwQiGqrFQTjSoYBpFqLXBRgzKtu2QdzUKA\n vjnslVZwdihGS7x9CBuSj3hIcgbTgIcFG/AGtu/zEj84EhI/ojpGJCoC8\n rrgqY2VVZpbCfvxsruIAGumk+UoRPILh76V3k/Wa5ZvP3rBts8N5snbio\n WpDVtjbQgbDdJ39X7TKzlDuJrnDghJlnQiSmj0rVon3S+ND1WI/CVOKAU\n Rm0/qtP2BMXRr1p57Vcc70u9OMneLfuDOAZzjGJLZjkHlPTxqP9G1Z8CF\n S5gpqlc2SqgATAPjki3sCpzE+OSBtipw8pL9xufKrRciuzHBJdYnmnvR4 A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10504\"; a=\"368192094\"", "E=Sophos;i=\"5.95,193,1661842800\"; d=\"scan'208\";a=\"368192094\"", "E=McAfee;i=\"6500,9779,10504\"; a=\"803836093\"", "E=Sophos;i=\"5.95,193,1661842800\"; d=\"scan'208\";a=\"803836093\"" ], "X-ExtLoop1": "1", "From": "Hernan Vargas <hernan.vargas@intel.com>", "To": "dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,\n maxime.coquelin@redhat.com", "Cc": "nicolas.chautru@intel.com, qi.z.zhang@intel.com,\n Hernan Vargas <hernan.vargas@intel.com>", "Subject": "[PATCH v4 17/30] baseband/acc100: add HARQ index helper function", "Date": "Tue, 18 Oct 2022 17:39:05 -0700", "Message-Id": "<20221019003918.257506-18-hernan.vargas@intel.com>", "X-Mailer": "git-send-email 2.37.1", "In-Reply-To": "<20221019003918.257506-1-hernan.vargas@intel.com>", "References": "<20221019003918.257506-1-hernan.vargas@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Refactor code to use the HARQ index helper function and make harq_idx\nuint32.\n\nSigned-off-by: Hernan Vargas <hernan.vargas@intel.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n drivers/baseband/acc/rte_acc100_pmd.c | 36 +++++++++++++--------------\n 1 file changed, 17 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c\nindex 0921e9a44d..d0c98ced32 100644\n--- a/drivers/baseband/acc/rte_acc100_pmd.c\n+++ b/drivers/baseband/acc/rte_acc100_pmd.c\n@@ -1050,7 +1050,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,\n \t\tunion acc_harq_layout_data *harq_layout)\n {\n \tuint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;\n-\tuint16_t harq_index;\n+\tuint32_t harq_index;\n \tuint32_t l;\n \tbool harq_prun = false;\n \tuint32_t max_hc_in;\n@@ -1098,8 +1098,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,\n \t\t\tRTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);\n \tfcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,\n \t\t\tRTE_BBDEV_LDPC_LLR_COMPRESSION);\n-\tharq_index = op->ldpc_dec.harq_combined_output.offset /\n-\t\t\tACC_HARQ_OFFSET;\n+\tharq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);\n #ifdef ACC100_EXT_MEM\n \t/* Limit cases when HARQ pruning is valid */\n \tharq_prun = ((op->ldpc_dec.harq_combined_output.offset %\n@@ -1777,20 +1776,17 @@ acc100_dma_desc_ld_update(struct rte_bbdev_dec_op *op,\n \t*h_out_length = desc->data_ptrs[next_triplet].blen;\n \tnext_triplet++;\n \n-\tif (check_bit(op->ldpc_dec.op_flags,\n-\t\t\t\tRTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) {\n-\t\tdesc->data_ptrs[next_triplet].address =\n-\t\t\t\top->ldpc_dec.harq_combined_output.offset;\n+\tif (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) {\n+\t\tstruct rte_bbdev_dec_op *prev_op;\n+\t\tuint32_t harq_idx, prev_harq_idx;\n+\t\tdesc->data_ptrs[next_triplet].address = op->ldpc_dec.harq_combined_output.offset;\n \t\t/* Adjust based on previous operation */\n-\t\tstruct rte_bbdev_dec_op *prev_op = desc->op_addr;\n+\t\tprev_op = desc->op_addr;\n \t\top->ldpc_dec.harq_combined_output.length =\n \t\t\t\tprev_op->ldpc_dec.harq_combined_output.length;\n-\t\tint16_t hq_idx = op->ldpc_dec.harq_combined_output.offset /\n-\t\t\t\tACC_HARQ_OFFSET;\n-\t\tint16_t prev_hq_idx =\n-\t\t\t\tprev_op->ldpc_dec.harq_combined_output.offset\n-\t\t\t\t/ ACC_HARQ_OFFSET;\n-\t\tharq_layout[hq_idx].val = harq_layout[prev_hq_idx].val;\n+\t\tharq_idx = hq_index(op->ldpc_dec.harq_combined_output.offset);\n+\t\tprev_harq_idx = hq_index(prev_op->ldpc_dec.harq_combined_output.offset);\n+\t\tharq_layout[harq_idx].val = harq_layout[prev_harq_idx].val;\n #ifndef ACC100_EXT_MEM\n \t\tstruct rte_bbdev_op_data ho =\n \t\t\t\top->ldpc_dec.harq_combined_output;\n@@ -2534,6 +2530,9 @@ harq_loopback(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n \tstruct rte_mbuf *hq_output_head, *hq_output;\n \tuint16_t harq_dma_length_in, harq_dma_length_out;\n \tuint16_t harq_in_length = op->ldpc_dec.harq_combined_input.length;\n+\tbool ddr_mem_in;\n+\tunion acc_harq_layout_data *harq_layout;\n+\tuint32_t harq_index;\n \n \tif (harq_in_length == 0) {\n \t\trte_bbdev_log(ERR, \"Loopback of invalid null size\\n\");\n@@ -2553,13 +2552,12 @@ harq_loopback(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n \t}\n \tharq_dma_length_out = harq_dma_length_in;\n \n-\tbool ddr_mem_in = check_bit(op->ldpc_dec.op_flags,\n+\tddr_mem_in = check_bit(op->ldpc_dec.op_flags,\n \t\t\tRTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE);\n-\tunion acc_harq_layout_data *harq_layout = q->d->harq_layout;\n-\tuint16_t harq_index = (ddr_mem_in ?\n+\tharq_layout = q->d->harq_layout;\n+\tharq_index = hq_index(ddr_mem_in ?\n \t\t\top->ldpc_dec.harq_combined_input.offset :\n-\t\t\top->ldpc_dec.harq_combined_output.offset)\n-\t\t\t/ ACC_HARQ_OFFSET;\n+\t\t\top->ldpc_dec.harq_combined_output.offset);\n \n \tdesc = acc_desc(q, total_enqueued_cbs);\n \tfcw = &desc->req.fcw_ld;\n", "prefixes": [ "v4", "17/30" ] }{ "id": 118452, "url": "