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GET /api/patches/118436/?format=api
{ "id": 118436, "url": "https://patches.dpdk.org/api/patches/118436/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221019003918.257506-2-hernan.vargas@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221019003918.257506-2-hernan.vargas@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221019003918.257506-2-hernan.vargas@intel.com", "date": "2022-10-19T00:38:49", "name": "[v4,01/30] baseband/acc100: fix ring availability calculation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "862a324a70c117b296354637aab4a8630b8dddc1", "submitter": { "id": 2659, "url": "https://patches.dpdk.org/api/people/2659/?format=api", "name": "Hernan Vargas", "email": "hernan.vargas@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221019003918.257506-2-hernan.vargas@intel.com/mbox/", "series": [ { "id": 25287, "url": "https://patches.dpdk.org/api/series/25287/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25287", "date": "2022-10-19T00:38:48", "name": "baseband/acc100: changes for 22.11", "version": 4, "mbox": "https://patches.dpdk.org/series/25287/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/118436/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/118436/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E5882A0560;\n\tTue, 18 Oct 2022 18:42:53 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DA6E741144;\n\tTue, 18 Oct 2022 18:42:50 +0200 (CEST)", "from mga06.intel.com (mga06b.intel.com [134.134.136.31])\n by mails.dpdk.org (Postfix) with ESMTP id E339B40395;\n Tue, 18 Oct 2022 18:42:47 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Oct 2022 09:42:47 -0700", "from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103])\n by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:46 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1666111368; x=1697647368;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=Gwyd+01g6kF0VZMaCZCULw9hNkTDvbEptlyUbPOUevo=;\n b=iRxBGWhGhhRH4KuVAKNf05RW4ILUvI20wuvAeDMbXlBsI1lYAoTNqTSk\n L2LvmXyJxb3F7kZO+cikryIYnbpXf02CZHkxvCY9A7TEPy6GBxlZ7SGgB\n Vauiby+X4UhA5yMINy620KVr6Hwe6PsYv1D7YyG8IauPCcxc1XkEj2LtK\n zervFL7Bzve3U0gihFFSyBM9l9Fwiv3ll/Z/OAd3/1L7wEoBJRidYzB5W\n JInFxykxnUbGf7qFK+LTPEYL8iepVIKhbNMy1EuKH3eyWIb0WvjdGFRPu\n rRUptOXDvV1APD+R+FHDsjpNP5gsNtX3y6fOef2aMPreGLtN3NpSY7gk6 w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10504\"; a=\"368192021\"", "E=Sophos;i=\"5.95,193,1661842800\"; d=\"scan'208\";a=\"368192021\"", "E=McAfee;i=\"6500,9779,10504\"; a=\"803835980\"", "E=Sophos;i=\"5.95,193,1661842800\"; d=\"scan'208\";a=\"803835980\"" ], "X-ExtLoop1": "1", "From": "Hernan Vargas <hernan.vargas@intel.com>", "To": "dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,\n maxime.coquelin@redhat.com", "Cc": "nicolas.chautru@intel.com, qi.z.zhang@intel.com,\n Hernan Vargas <hernan.vargas@intel.com>, stable@dpdk.org", "Subject": "[PATCH v4 01/30] baseband/acc100: fix ring availability calculation", "Date": "Tue, 18 Oct 2022 17:38:49 -0700", "Message-Id": "<20221019003918.257506-2-hernan.vargas@intel.com>", "X-Mailer": "git-send-email 2.37.1", "In-Reply-To": "<20221019003918.257506-1-hernan.vargas@intel.com>", "References": "<20221019003918.257506-1-hernan.vargas@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Refactor of the queue availability computation to prevent the\napplication to dequeue more than what may have been enqueued.\n\nFixes: 5ad5060f8f7 (\"baseband/acc100: add LDPC processing functions\")\nCc: stable@dpdk.org\n\nSigned-off-by: Hernan Vargas <hernan.vargas@intel.com>\n---\n drivers/baseband/acc/rte_acc100_pmd.c | 25 +++++++++++++------------\n 1 file changed, 13 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c\nindex e5384223d1..3b0c8e41dc 100644\n--- a/drivers/baseband/acc/rte_acc100_pmd.c\n+++ b/drivers/baseband/acc/rte_acc100_pmd.c\n@@ -2861,7 +2861,7 @@ acc100_enqueue_enc_cb(struct rte_bbdev_queue_data *q_data,\n \t\tstruct rte_bbdev_enc_op **ops, uint16_t num)\n {\n \tstruct acc_queue *q = q_data->queue_private;\n-\tint32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head;\n+\tint32_t avail = acc_ring_avail_enq(q);\n \tuint16_t i;\n \tunion acc_dma_desc *desc;\n \tint ret;\n@@ -2899,7 +2899,7 @@ acc100_enqueue_ldpc_enc_cb(struct rte_bbdev_queue_data *q_data,\n \t\tstruct rte_bbdev_enc_op **ops, uint16_t num)\n {\n \tstruct acc_queue *q = q_data->queue_private;\n-\tint32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head;\n+\tint32_t avail = acc_ring_avail_enq(q);\n \tuint16_t i = 0;\n \tunion acc_dma_desc *desc;\n \tint ret, desc_idx = 0;\n@@ -2949,7 +2949,7 @@ acc100_enqueue_enc_tb(struct rte_bbdev_queue_data *q_data,\n \t\tstruct rte_bbdev_enc_op **ops, uint16_t num)\n {\n \tstruct acc_queue *q = q_data->queue_private;\n-\tint32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head;\n+\tint32_t avail = acc_ring_avail_enq(q);\n \tuint16_t i, enqueued_cbs = 0;\n \tuint8_t cbs_in_tb;\n \tint ret;\n@@ -3011,7 +3011,7 @@ acc100_enqueue_dec_cb(struct rte_bbdev_queue_data *q_data,\n \t\tstruct rte_bbdev_dec_op **ops, uint16_t num)\n {\n \tstruct acc_queue *q = q_data->queue_private;\n-\tint32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head;\n+\tint32_t avail = acc_ring_avail_enq(q);\n \tuint16_t i;\n \tunion acc_dma_desc *desc;\n \tint ret;\n@@ -3050,7 +3050,7 @@ acc100_enqueue_ldpc_dec_tb(struct rte_bbdev_queue_data *q_data,\n \t\tstruct rte_bbdev_dec_op **ops, uint16_t num)\n {\n \tstruct acc_queue *q = q_data->queue_private;\n-\tint32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head;\n+\tint32_t avail = acc_ring_avail_enq(q);\n \tuint16_t i, enqueued_cbs = 0;\n \tuint8_t cbs_in_tb;\n \tint ret;\n@@ -3083,7 +3083,7 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data,\n \t\tstruct rte_bbdev_dec_op **ops, uint16_t num)\n {\n \tstruct acc_queue *q = q_data->queue_private;\n-\tint32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head;\n+\tint32_t avail = acc_ring_avail_enq(q);\n \tuint16_t i;\n \tunion acc_dma_desc *desc;\n \tint ret;\n@@ -3132,7 +3132,7 @@ acc100_enqueue_dec_tb(struct rte_bbdev_queue_data *q_data,\n \t\tstruct rte_bbdev_dec_op **ops, uint16_t num)\n {\n \tstruct acc_queue *q = q_data->queue_private;\n-\tint32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head;\n+\tint32_t avail = acc_ring_avail_enq(q);\n \tuint16_t i, enqueued_cbs = 0;\n \tuint8_t cbs_in_tb;\n \tint ret;\n@@ -3495,12 +3495,13 @@ acc100_dequeue_enc(struct rte_bbdev_queue_data *q_data,\n {\n \tstruct acc_queue *q = q_data->queue_private;\n \tuint16_t dequeue_num;\n-\tuint32_t avail = q->sw_ring_head - q->sw_ring_tail;\n+\tuint32_t avail = acc_ring_avail_deq(q);\n \tuint32_t aq_dequeued = 0;\n \tuint16_t i, dequeued_cbs = 0;\n \tstruct rte_bbdev_enc_op *op;\n \tint ret;\n-\n+\tif (avail == 0)\n+\t\treturn 0;\n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n \tif (unlikely(ops == NULL || q == NULL)) {\n \t\trte_bbdev_log_debug(\"Unexpected undefined pointer\");\n@@ -3539,7 +3540,7 @@ acc100_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,\n \t\tstruct rte_bbdev_enc_op **ops, uint16_t num)\n {\n \tstruct acc_queue *q = q_data->queue_private;\n-\tuint32_t avail = q->sw_ring_head - q->sw_ring_tail;\n+\tuint32_t avail = acc_ring_avail_deq(q);\n \tuint32_t aq_dequeued = 0;\n \tuint16_t dequeue_num, i, dequeued_cbs = 0, dequeued_descs = 0;\n \tint ret;\n@@ -3579,7 +3580,7 @@ acc100_dequeue_dec(struct rte_bbdev_queue_data *q_data,\n {\n \tstruct acc_queue *q = q_data->queue_private;\n \tuint16_t dequeue_num;\n-\tuint32_t avail = q->sw_ring_head - q->sw_ring_tail;\n+\tuint32_t avail = acc_ring_avail_deq(q);\n \tuint32_t aq_dequeued = 0;\n \tuint16_t i;\n \tuint16_t dequeued_cbs = 0;\n@@ -3623,7 +3624,7 @@ acc100_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n {\n \tstruct acc_queue *q = q_data->queue_private;\n \tuint16_t dequeue_num;\n-\tuint32_t avail = q->sw_ring_head - q->sw_ring_tail;\n+\tuint32_t avail = acc_ring_avail_deq(q);\n \tuint32_t aq_dequeued = 0;\n \tuint16_t i;\n \tuint16_t dequeued_cbs = 0;\n", "prefixes": [ "v4", "01/30" ] }