Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/118139/?format=api
{ "id": 118139, "url": "https://patches.dpdk.org/api/patches/118139/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221013114156.996517-1-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221013114156.996517-1-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221013114156.996517-1-ndabilpuram@marvell.com", "date": "2022-10-13T11:41:44", "name": "[v2,01/13] common/cnxk: set MTU size on SDP based on SoC type", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6e23493949ab680a1cdc1474e26562fd91f61cfe", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221013114156.996517-1-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 25210, "url": "https://patches.dpdk.org/api/series/25210/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25210", "date": "2022-10-13T11:41:44", "name": "[v2,01/13] common/cnxk: set MTU size on SDP based on SoC type", "version": 2, "mbox": "https://patches.dpdk.org/series/25210/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/118139/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/118139/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9EF82A00C2;\n\tThu, 13 Oct 2022 13:42:08 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 898D742EAF;\n\tThu, 13 Oct 2022 13:42:08 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 23DA842C95\n for <dev@dpdk.org>; Thu, 13 Oct 2022 13:42:06 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 29DAGjst027230\n for <dev@dpdk.org>; Thu, 13 Oct 2022 04:42:06 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3k67nqacd0-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 13 Oct 2022 04:42:06 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 13 Oct 2022 04:42:04 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 13 Oct 2022 04:42:04 -0700", "from localhost.localdomain (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 118633F7058;\n Thu, 13 Oct 2022 04:42:01 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=oVewmLuVIu6sAASjZ8s3eVskBcTlzciqDqmoCfLnTJs=;\n b=f29OOMxqw58a/WBylYAb5MkfQ8HCMpSS6MHfI/b0TjYTARmY1c0rgGEhpP476ZS6vGvj\n 2eYLogEjFHSWJ0t5NL/MiPe5qw5X9JIrausXI94kelbkTn6I6fAvMaHlVfFB4jZzMkla\n HMSfIXexi/0NXxwBn08pho+HESYz8M20kO6ZYX8ofo/gP4P1sYojrKvCsGNDgX4JRJ53\n bt3VvtpSJ3pc4MFA8qqpOPZovzL6YXvg8Xid3G6k8j21cjeBkRFtn0wTbkcR7Ir+Bdrh\n xyELH84wTCycL88KJCvp/HcuGgdtCBLJNw0xqXndy4PRpJaj91YOzYR28dTsUfHPJT+L Ow==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>, Sathesh Edara <sedara@marvell.com>", "Subject": "[PATCH v2 01/13] common/cnxk: set MTU size on SDP based on SoC type", "Date": "Thu, 13 Oct 2022 17:11:44 +0530", "Message-ID": "<20221013114156.996517-1-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221011120135.45846-1-ndabilpuram@marvell.com>", "References": "<20221011120135.45846-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "oPSN2catvDjUH-yQls7ak5V1iAckE7yM", "X-Proofpoint-ORIG-GUID": "oPSN2catvDjUH-yQls7ak5V1iAckE7yM", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-10-13_07,2022-10-13_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Sathesh Edara <sedara@marvell.com>\n\nSet maximum frame size on SDP NIX side to 16KB for T93 A0-B0,\nF95N A0 and F95O A0 SOC type. Rest of the SoCs SDP NIX to 64KB.\n\nSigned-off-by: Sathesh Edara <sedara@marvell.com>\n---\nv2:\n- Add fixes line in patch 1/13\n- Squash patch 8/13 to 7/13 as 7/13 is the patch that introduced the bug\n- Add another patch to handle HARD SA expiry event for outbound inline.\n\n drivers/common/cnxk/hw/nix.h | 1 +\n drivers/common/cnxk/roc_errata.h | 8 ++++++++\n drivers/common/cnxk/roc_model.h | 12 ++++++++++++\n drivers/common/cnxk/roc_nix.c | 5 ++++-\n 4 files changed, 25 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h\nindex a5352644ca..425c335bf3 100644\n--- a/drivers/common/cnxk/hw/nix.h\n+++ b/drivers/common/cnxk/hw/nix.h\n@@ -2118,6 +2118,7 @@ struct nix_lso_format {\n #define NIX_CN9K_MAX_HW_FRS 9212UL\n #define NIX_LBK_MAX_HW_FRS 65535UL\n #define NIX_SDP_MAX_HW_FRS 65535UL\n+#define NIX_SDP_16K_HW_FRS 16380UL\n #define NIX_RPM_MAX_HW_FRS 16380UL\n #define NIX_MIN_HW_FRS\t 60UL\n \ndiff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h\nindex d3b32f1786..a39796e894 100644\n--- a/drivers/common/cnxk/roc_errata.h\n+++ b/drivers/common/cnxk/roc_errata.h\n@@ -90,4 +90,12 @@ roc_errata_nix_no_meta_aura(void)\n \treturn roc_model_is_cn10ka_a0();\n }\n \n+/* Errata IPBUNIXTX-35039 */\n+static inline bool\n+roc_errata_nix_sdp_send_has_mtu_size_16k(void)\n+{\n+\treturn (roc_model_is_cnf95xxn_a0() || roc_model_is_cnf95xxo_a0() ||\n+\t\troc_model_is_cn96_a0() || roc_model_is_cn96_b0());\n+}\n+\n #endif /* _ROC_ERRATA_H_ */\ndiff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h\nindex 57a8af06fc..1985dd771d 100644\n--- a/drivers/common/cnxk/roc_model.h\n+++ b/drivers/common/cnxk/roc_model.h\n@@ -140,6 +140,12 @@ roc_model_is_cn96_ax(void)\n \treturn (roc_model->flag & ROC_MODEL_CN96xx_Ax);\n }\n \n+static inline uint64_t\n+roc_model_is_cn96_b0(void)\n+{\n+\treturn (roc_model->flag & ROC_MODEL_CN96xx_B0);\n+}\n+\n static inline uint64_t\n roc_model_is_cn96_cx(void)\n {\n@@ -170,6 +176,12 @@ roc_model_is_cnf95xxn_b0(void)\n \treturn roc_model->flag & ROC_MODEL_CNF95xxN_B0;\n }\n \n+static inline uint64_t\n+roc_model_is_cnf95xxo_a0(void)\n+{\n+\treturn roc_model->flag & ROC_MODEL_CNF95xxO_A0;\n+}\n+\n static inline uint16_t\n roc_model_is_cn95xxn_a0(void)\n {\ndiff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c\nindex 4bb306b60e..8fd8ec8461 100644\n--- a/drivers/common/cnxk/roc_nix.c\n+++ b/drivers/common/cnxk/roc_nix.c\n@@ -127,8 +127,11 @@ roc_nix_max_pkt_len(struct roc_nix *roc_nix)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \n-\tif (roc_nix_is_sdp(roc_nix))\n+\tif (roc_nix_is_sdp(roc_nix)) {\n+\t\tif (roc_errata_nix_sdp_send_has_mtu_size_16k())\n+\t\t\treturn NIX_SDP_16K_HW_FRS;\n \t\treturn NIX_SDP_MAX_HW_FRS;\n+\t}\n \n \tif (roc_model_is_cn9k())\n \t\treturn NIX_CN9K_MAX_HW_FRS;\n", "prefixes": [ "v2", "01/13" ] }