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GET /api/patches/117652/?format=api
{ "id": 117652, "url": "https://patches.dpdk.org/api/patches/117652/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221007213851.31524-7-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221007213851.31524-7-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221007213851.31524-7-nicolas.chautru@intel.com", "date": "2022-10-07T21:38:43", "name": "[v9,06/14] baseband/acc: add info get function for ACC200", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b67246ce385df424dda843932ffcf5b9d63a74db", "submitter": { "id": 1314, "url": "https://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221007213851.31524-7-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 25041, "url": "https://patches.dpdk.org/api/series/25041/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25041", "date": "2022-10-07T21:38:37", "name": "bbdev ACC200 PMD", "version": 9, "mbox": "https://patches.dpdk.org/series/25041/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117652/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/117652/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 10FFFA0543;\n\tFri, 7 Oct 2022 23:39:54 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3AEA042B86;\n\tFri, 7 Oct 2022 23:39:16 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 55E3E40042\n for <dev@dpdk.org>; Fri, 7 Oct 2022 23:39:11 +0200 (CEST)", "from orsmga007.jf.intel.com ([10.7.209.58])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 07 Oct 2022 14:39:10 -0700", "from unknown (HELO icx-npg-scs1-cp1.localdomain) ([10.233.180.245])\n by orsmga007.jf.intel.com with ESMTP; 07 Oct 2022 14:39:10 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1665178751; x=1696714751;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=EClIY3rUZ7MrF2hhI39B//yR8IxOZ47FMBq9850mgmM=;\n b=b8fAmkORxml7o3qa77SwYSpYcvOwDhRsizUSE/nehenz4p9Pr7EKmtEq\n GPdPFDk5gBd/yJ9xdIHW7oKEMuSvtn/eTLOkSieRY+cdmUbzpkEU3sSVz\n NX4nddNAk/HZCnQ4tDlxcuekVcYv41BpMFc+6QcMIF7RyOZ6G/Ph/UH37\n 4d0cx9848tAhriCrAfKCvfUEe2lcT9YBTAh0D32pZTXZc1rwbwg6EX91M\n aRprgt2zrdF2ytOrF9j6rKPWLeopgIc5UAqI3LiH1FzEtvXUdSYmU/YIc\n lRLam9CFTjzpf0iCWu0pkHLidTrN0x/zItUeo+ATXYbQLl6wvGT/T/AL/ w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10493\"; a=\"291118502\"", "E=Sophos;i=\"5.95,167,1661842800\"; d=\"scan'208\";a=\"291118502\"", "E=McAfee;i=\"6500,9779,10493\"; a=\"620388451\"", "E=Sophos;i=\"5.95,167,1661842800\"; d=\"scan'208\";a=\"620388451\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tgakhil@marvell.com,\n\tmaxime.coquelin@redhat.com", "Cc": "trix@redhat.com, mdr@ashroe.eu, bruce.richardson@intel.com,\n hemant.agrawal@nxp.com, david.marchand@redhat.com,\n stephen@networkplumber.org, hernan.vargas@intel.com,\n Nic Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v9 06/14] baseband/acc: add info get function for ACC200", "Date": "Fri, 7 Oct 2022 14:38:43 -0700", "Message-Id": "<20221007213851.31524-7-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 2.37.1", "In-Reply-To": "<20221007213851.31524-1-nicolas.chautru@intel.com>", "References": "<20221007213851.31524-1-nicolas.chautru@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Nic Chautru <nicolas.chautru@intel.com>\n\nAdded support for info_get to allow to query the device.\nNull capability exposed.\n\nSigned-off-by: Nic Chautru <nicolas.chautru@intel.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n drivers/baseband/acc/acc200_pmd.h | 1 +\n drivers/baseband/acc/rte_acc200_pmd.c | 231 ++++++++++++++++++++++++++\n 2 files changed, 232 insertions(+)", "diff": "diff --git a/drivers/baseband/acc/acc200_pmd.h b/drivers/baseband/acc/acc200_pmd.h\nindex 9df1f506ad..0a0f6dc4fe 100644\n--- a/drivers/baseband/acc/acc200_pmd.h\n+++ b/drivers/baseband/acc/acc200_pmd.h\n@@ -8,6 +8,7 @@\n #include \"acc_common.h\"\n #include \"acc200_pf_enum.h\"\n #include \"acc200_vf_enum.h\"\n+#include \"rte_acc200_cfg.h\"\n \n /* Helper macro for logging */\n #define rte_bbdev_log(level, fmt, ...) \\\ndiff --git a/drivers/baseband/acc/rte_acc200_pmd.c b/drivers/baseband/acc/rte_acc200_pmd.c\nindex c59cad1d26..09d879fe5f 100644\n--- a/drivers/baseband/acc/rte_acc200_pmd.c\n+++ b/drivers/baseband/acc/rte_acc200_pmd.c\n@@ -29,6 +29,189 @@ RTE_LOG_REGISTER_DEFAULT(acc200_logtype, DEBUG);\n RTE_LOG_REGISTER_DEFAULT(acc200_logtype, NOTICE);\n #endif\n \n+/* Calculate the offset of the enqueue register. */\n+static inline uint32_t\n+queue_offset(bool pf_device, uint8_t vf_id, uint8_t qgrp_id, uint16_t aq_id)\n+{\n+\tif (pf_device)\n+\t\treturn ((vf_id << 12) + (qgrp_id << 7) + (aq_id << 3) +\n+\t\t\t\tHWPfQmgrIngressAq);\n+\telse\n+\t\treturn ((qgrp_id << 7) + (aq_id << 3) +\n+\t\t\t\tHWVfQmgrIngressAq);\n+}\n+\n+enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, FFT, NUM_ACC};\n+\n+/* Return the queue topology for a Queue Group Index. */\n+static inline void\n+qtopFromAcc(struct rte_acc_queue_topology **qtop, int acc_enum, struct rte_acc_conf *acc_conf)\n+{\n+\tstruct rte_acc_queue_topology *p_qtop;\n+\tp_qtop = NULL;\n+\n+\tswitch (acc_enum) {\n+\tcase UL_4G:\n+\t\tp_qtop = &(acc_conf->q_ul_4g);\n+\t\tbreak;\n+\tcase UL_5G:\n+\t\tp_qtop = &(acc_conf->q_ul_5g);\n+\t\tbreak;\n+\tcase DL_4G:\n+\t\tp_qtop = &(acc_conf->q_dl_4g);\n+\t\tbreak;\n+\tcase DL_5G:\n+\t\tp_qtop = &(acc_conf->q_dl_5g);\n+\t\tbreak;\n+\tcase FFT:\n+\t\tp_qtop = &(acc_conf->q_fft);\n+\t\tbreak;\n+\tdefault:\n+\t\t/* NOTREACHED. */\n+\t\trte_bbdev_log(ERR, \"Unexpected error evaluating %s using %d\", __func__, acc_enum);\n+\t\tbreak;\n+\t}\n+\t*qtop = p_qtop;\n+}\n+\n+static void\n+initQTop(struct rte_acc_conf *acc_conf)\n+{\n+\tacc_conf->q_ul_4g.num_aqs_per_groups = 0;\n+\tacc_conf->q_ul_4g.num_qgroups = 0;\n+\tacc_conf->q_ul_4g.first_qgroup_index = -1;\n+\tacc_conf->q_ul_5g.num_aqs_per_groups = 0;\n+\tacc_conf->q_ul_5g.num_qgroups = 0;\n+\tacc_conf->q_ul_5g.first_qgroup_index = -1;\n+\tacc_conf->q_dl_4g.num_aqs_per_groups = 0;\n+\tacc_conf->q_dl_4g.num_qgroups = 0;\n+\tacc_conf->q_dl_4g.first_qgroup_index = -1;\n+\tacc_conf->q_dl_5g.num_aqs_per_groups = 0;\n+\tacc_conf->q_dl_5g.num_qgroups = 0;\n+\tacc_conf->q_dl_5g.first_qgroup_index = -1;\n+\tacc_conf->q_fft.num_aqs_per_groups = 0;\n+\tacc_conf->q_fft.num_qgroups = 0;\n+\tacc_conf->q_fft.first_qgroup_index = -1;\n+}\n+\n+static inline void\n+updateQtop(uint8_t acc, uint8_t qg, struct rte_acc_conf *acc_conf, struct acc_device *d) {\n+\tuint32_t reg;\n+\tstruct rte_acc_queue_topology *q_top = NULL;\n+\tuint16_t aq;\n+\n+\tqtopFromAcc(&q_top, acc, acc_conf);\n+\tif (unlikely(q_top == NULL))\n+\t\treturn;\n+\tq_top->num_qgroups++;\n+\tif (q_top->first_qgroup_index == -1) {\n+\t\tq_top->first_qgroup_index = qg;\n+\t\t/* Can be optimized to assume all are enabled by default. */\n+\t\treg = acc_reg_read(d, queue_offset(d->pf_device, 0, qg, ACC200_NUM_AQS - 1));\n+\t\tif (reg & ACC_QUEUE_ENABLE) {\n+\t\t\tq_top->num_aqs_per_groups = ACC200_NUM_AQS;\n+\t\t\treturn;\n+\t\t}\n+\t\tq_top->num_aqs_per_groups = 0;\n+\t\tfor (aq = 0; aq < ACC200_NUM_AQS; aq++) {\n+\t\t\treg = acc_reg_read(d, queue_offset(d->pf_device, 0, qg, aq));\n+\t\t\tif (reg & ACC_QUEUE_ENABLE)\n+\t\t\t\tq_top->num_aqs_per_groups++;\n+\t\t}\n+\t}\n+}\n+\n+/* Fetch configuration enabled for the PF/VF using MMIO Read (slow). */\n+static inline void\n+fetch_acc200_config(struct rte_bbdev *dev)\n+{\n+\tstruct acc_device *d = dev->data->dev_private;\n+\tstruct rte_acc_conf *acc_conf = &d->acc_conf;\n+\tconst struct acc200_registry_addr *reg_addr;\n+\tuint8_t acc, qg;\n+\tuint32_t reg_aq, reg_len0, reg_len1, reg0, reg1;\n+\tuint32_t reg_mode, idx;\n+\tstruct rte_acc_queue_topology *q_top = NULL;\n+\tint qman_func_id[ACC200_NUM_ACCS] = {ACC_ACCMAP_0, ACC_ACCMAP_1,\n+\t\t\tACC_ACCMAP_2, ACC_ACCMAP_3, ACC_ACCMAP_4};\n+\n+\t/* No need to retrieve the configuration is already done. */\n+\tif (d->configured)\n+\t\treturn;\n+\n+\t/* Choose correct registry addresses for the device type. */\n+\tif (d->pf_device)\n+\t\treg_addr = &pf_reg_addr;\n+\telse\n+\t\treg_addr = &vf_reg_addr;\n+\n+\td->ddr_size = 0;\n+\n+\t/* Single VF Bundle by VF. */\n+\tacc_conf->num_vf_bundles = 1;\n+\tinitQTop(acc_conf);\n+\n+\treg0 = acc_reg_read(d, reg_addr->qman_group_func);\n+\treg1 = acc_reg_read(d, reg_addr->qman_group_func + 4);\n+\tfor (qg = 0; qg < ACC200_NUM_QGRPS; qg++) {\n+\t\treg_aq = acc_reg_read(d, queue_offset(d->pf_device, 0, qg, 0));\n+\t\tif (reg_aq & ACC_QUEUE_ENABLE) {\n+\t\t\tif (qg < ACC_NUM_QGRPS_PER_WORD)\n+\t\t\t\tidx = (reg0 >> (qg * 4)) & 0x7;\n+\t\t\telse\n+\t\t\t\tidx = (reg1 >> ((qg -\n+\t\t\t\t\tACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;\n+\t\t\tif (idx < ACC200_NUM_ACCS) {\n+\t\t\t\tacc = qman_func_id[idx];\n+\t\t\t\tupdateQtop(acc, qg, acc_conf, d);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\t/* Check the depth of the AQs. */\n+\treg_len0 = acc_reg_read(d, reg_addr->depth_log0_offset);\n+\treg_len1 = acc_reg_read(d, reg_addr->depth_log1_offset);\n+\tfor (acc = 0; acc < NUM_ACC; acc++) {\n+\t\tqtopFromAcc(&q_top, acc, acc_conf);\n+\t\tif (q_top->first_qgroup_index < ACC_NUM_QGRPS_PER_WORD)\n+\t\t\tq_top->aq_depth_log2 = (reg_len0 >> (q_top->first_qgroup_index * 4)) & 0xF;\n+\t\telse\n+\t\t\tq_top->aq_depth_log2 = (reg_len1 >> ((q_top->first_qgroup_index -\n+\t\t\t\t\tACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;\n+\t}\n+\n+\t/* Read PF mode. */\n+\tif (d->pf_device) {\n+\t\treg_mode = acc_reg_read(d, HWPfHiPfMode);\n+\t\tacc_conf->pf_mode_en = (reg_mode == ACC_PF_VAL) ? 1 : 0;\n+\t} else {\n+\t\treg_mode = acc_reg_read(d, reg_addr->hi_mode);\n+\t\tacc_conf->pf_mode_en = reg_mode & 1;\n+\t}\n+\n+\trte_bbdev_log_debug(\n+\t\t\t\"%s Config LLR SIGN IN/OUT %s %s QG %u %u %u %u %u AQ %u %u %u %u %u Len %u %u %u %u %u\\n\",\n+\t\t\t(d->pf_device) ? \"PF\" : \"VF\",\n+\t\t\t(acc_conf->input_pos_llr_1_bit) ? \"POS\" : \"NEG\",\n+\t\t\t(acc_conf->output_pos_llr_1_bit) ? \"POS\" : \"NEG\",\n+\t\t\tacc_conf->q_ul_4g.num_qgroups,\n+\t\t\tacc_conf->q_dl_4g.num_qgroups,\n+\t\t\tacc_conf->q_ul_5g.num_qgroups,\n+\t\t\tacc_conf->q_dl_5g.num_qgroups,\n+\t\t\tacc_conf->q_fft.num_qgroups,\n+\t\t\tacc_conf->q_ul_4g.num_aqs_per_groups,\n+\t\t\tacc_conf->q_dl_4g.num_aqs_per_groups,\n+\t\t\tacc_conf->q_ul_5g.num_aqs_per_groups,\n+\t\t\tacc_conf->q_dl_5g.num_aqs_per_groups,\n+\t\t\tacc_conf->q_fft.num_aqs_per_groups,\n+\t\t\tacc_conf->q_ul_4g.aq_depth_log2,\n+\t\t\tacc_conf->q_dl_4g.aq_depth_log2,\n+\t\t\tacc_conf->q_ul_5g.aq_depth_log2,\n+\t\t\tacc_conf->q_dl_5g.aq_depth_log2,\n+\t\t\tacc_conf->q_fft.aq_depth_log2);\n+}\n+\n+/* Free memory used for software rings. */\n static int\n acc200_dev_close(struct rte_bbdev *dev)\n {\n@@ -38,9 +221,57 @@ acc200_dev_close(struct rte_bbdev *dev)\n \treturn 0;\n }\n \n+/* Get ACC200 device info. */\n+static void\n+acc200_dev_info_get(struct rte_bbdev *dev,\n+\t\tstruct rte_bbdev_driver_info *dev_info)\n+{\n+\tstruct acc_device *d = dev->data->dev_private;\n+\tint i;\n+\tstatic const struct rte_bbdev_op_cap bbdev_capabilities[] = {\n+\t\tRTE_BBDEV_END_OF_CAPABILITIES_LIST()\n+\t};\n+\n+\tstatic struct rte_bbdev_queue_conf default_queue_conf;\n+\tdefault_queue_conf.socket = dev->data->socket_id;\n+\tdefault_queue_conf.queue_size = ACC_MAX_QUEUE_DEPTH;\n+\n+\tdev_info->driver_name = dev->device->driver->name;\n+\n+\t/* Read and save the populated config from ACC200 registers. */\n+\tfetch_acc200_config(dev);\n+\n+\t/* Exposed number of queues. */\n+\tdev_info->num_queues[RTE_BBDEV_OP_NONE] = 0;\n+\tdev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] = 0;\n+\tdev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] = 0;\n+\tdev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC] = 0;\n+\tdev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] = 0;\n+\tdev_info->num_queues[RTE_BBDEV_OP_FFT] = 0;\n+\tdev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC] = 0;\n+\tdev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC] = 0;\n+\tdev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] = 0;\n+\tdev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] = 0;\n+\tdev_info->queue_priority[RTE_BBDEV_OP_FFT] = 0;\n+\tdev_info->max_num_queues = 0;\n+\tfor (i = RTE_BBDEV_OP_NONE; i <= RTE_BBDEV_OP_FFT; i++)\n+\t\tdev_info->max_num_queues += dev_info->num_queues[i];\n+\tdev_info->queue_size_lim = ACC_MAX_QUEUE_DEPTH;\n+\tdev_info->hardware_accelerated = true;\n+\tdev_info->max_dl_queue_priority =\n+\t\t\td->acc_conf.q_dl_4g.num_qgroups - 1;\n+\tdev_info->max_ul_queue_priority =\n+\t\t\td->acc_conf.q_ul_4g.num_qgroups - 1;\n+\tdev_info->default_queue_conf = default_queue_conf;\n+\tdev_info->cpu_flag_reqs = NULL;\n+\tdev_info->min_alignment = 1;\n+\tdev_info->capabilities = bbdev_capabilities;\n+\tdev_info->harq_buffer_size = 0;\n+}\n \n static const struct rte_bbdev_ops acc200_bbdev_ops = {\n \t.close = acc200_dev_close,\n+\t.info_get = acc200_dev_info_get,\n };\n \n /* ACC200 PCI PF address map. */\n", "prefixes": [ "v9", "06/14" ] }