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GET /api/patches/117651/?format=api
{ "id": 117651, "url": "https://patches.dpdk.org/api/patches/117651/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221007213851.31524-6-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221007213851.31524-6-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221007213851.31524-6-nicolas.chautru@intel.com", "date": "2022-10-07T21:38:42", "name": "[v9,05/14] baseband/acc: add HW register definitions for ACC200", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8060339c91ebdaa78be9aecc5b4b3201c215e421", "submitter": { "id": 1314, "url": "https://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221007213851.31524-6-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 25041, "url": "https://patches.dpdk.org/api/series/25041/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25041", "date": "2022-10-07T21:38:37", "name": "bbdev ACC200 PMD", "version": 9, "mbox": "https://patches.dpdk.org/series/25041/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117651/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/117651/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 97782A0543;\n\tFri, 7 Oct 2022 23:39:47 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 40C8842B80;\n\tFri, 7 Oct 2022 23:39:15 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 8F51B427EE\n for <dev@dpdk.org>; Fri, 7 Oct 2022 23:39:10 +0200 (CEST)", "from orsmga007.jf.intel.com ([10.7.209.58])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 07 Oct 2022 14:39:10 -0700", "from unknown (HELO icx-npg-scs1-cp1.localdomain) ([10.233.180.245])\n by orsmga007.jf.intel.com with ESMTP; 07 Oct 2022 14:39:09 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1665178750; x=1696714750;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=DFs5rbeyND8WANr4kaP3ERJ7LeQFTkX6TQQQVCXkYow=;\n b=jvB9AKiXm78hNn/Yf3cptCKFD12YKgECaIpXyNg+TB9ASZSC14rUBRZN\n MPZ6UL4DB8eVO+B90aevL02RBaKyVyRE6sSTMYLfdwptH+kzPHe9Po/FH\n 3QJgsnU2wAPoWkYNhfvuJNPPhtf/USHDAtUxRF4Qc1lMIVOZMEmPN+c9r\n 7xn3luEpWQPvZzB4xkxA0UZUa+CbxsfR90Xdp8jddgdpCcgHaZTWC+ood\n ruGk37o0XvfjsKgRq9lGlwE2LuRRQM1W2e3Ppdrax+Gj6WFHxsNN/57Hv\n kUWG2/lSlaQE3hM6Rg6CQ7qoxIsvJ6aUf3VaFe/BJzijezp4ItkcXgRML Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10493\"; a=\"291118501\"", "E=Sophos;i=\"5.95,167,1661842800\"; d=\"scan'208\";a=\"291118501\"", "E=McAfee;i=\"6500,9779,10493\"; a=\"620388448\"", "E=Sophos;i=\"5.95,167,1661842800\"; d=\"scan'208\";a=\"620388448\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tgakhil@marvell.com,\n\tmaxime.coquelin@redhat.com", "Cc": "trix@redhat.com, mdr@ashroe.eu, bruce.richardson@intel.com,\n hemant.agrawal@nxp.com, david.marchand@redhat.com,\n stephen@networkplumber.org, hernan.vargas@intel.com,\n Nic Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v9 05/14] baseband/acc: add HW register definitions for ACC200", "Date": "Fri, 7 Oct 2022 14:38:42 -0700", "Message-Id": "<20221007213851.31524-6-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 2.37.1", "In-Reply-To": "<20221007213851.31524-1-nicolas.chautru@intel.com>", "References": "<20221007213851.31524-1-nicolas.chautru@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Nic Chautru <nicolas.chautru@intel.com>\n\nAdded registers list and structure to access the device.\n\nSigned-off-by: Nic Chautru <nicolas.chautru@intel.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n drivers/baseband/acc/acc200_pf_enum.h | 108 +++++++++++++++++\n drivers/baseband/acc/acc200_pmd.h | 163 ++++++++++++++++++++++++++\n drivers/baseband/acc/acc200_vf_enum.h | 83 +++++++++++++\n 3 files changed, 354 insertions(+)\n create mode 100644 drivers/baseband/acc/acc200_pf_enum.h\n create mode 100644 drivers/baseband/acc/acc200_vf_enum.h", "diff": "diff --git a/drivers/baseband/acc/acc200_pf_enum.h b/drivers/baseband/acc/acc200_pf_enum.h\nnew file mode 100644\nindex 0000000000..e52d8f5b19\n--- /dev/null\n+++ b/drivers/baseband/acc/acc200_pf_enum.h\n@@ -0,0 +1,108 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+#ifndef ACC200_PF_ENUM_H\n+#define ACC200_PF_ENUM_H\n+\n+/*\n+ * ACC200 Register mapping on PF BAR0\n+ * This is automatically generated from RDL, format may change with new RDL\n+ * Release.\n+ * Variable names are as is\n+ */\n+enum {\n+\tHWPfQmgrEgressQueuesTemplate = 0x0007FC00,\n+\tHWPfQmgrIngressAq = 0x00080000,\n+\tHWPfQmgrDepthLog2Grp = 0x00A00200,\n+\tHWPfQmgrTholdGrp = 0x00A00300,\n+\tHWPfQmgrGrpTmplateReg0Indx = 0x00A00600,\n+\tHWPfQmgrGrpTmplateReg1Indx = 0x00A00700,\n+\tHWPfQmgrGrpTmplateReg2indx = 0x00A00800,\n+\tHWPfQmgrGrpTmplateReg3Indx = 0x00A00900,\n+\tHWPfQmgrGrpTmplateReg4Indx = 0x00A00A00,\n+\tHWPfQmgrVfBaseAddr = 0x00A01000,\n+\tHWPfQmgrArbQDepthGrp = 0x00A02F00,\n+\tHWPfQmgrGrpFunction0 = 0x00A02F40,\n+\tHWPfQmgrGrpFunction1 = 0x00A02F44,\n+\tHWPfQmgrGrpPriority = 0x00A02F48,\n+\tHWPfQmgrAqEnableVf = 0x00A10000,\n+\tHWPfQmgrRingSizeVf = 0x00A20004,\n+\tHWPfQmgrGrpDepthLog20Vf = 0x00A20008,\n+\tHWPfQmgrGrpDepthLog21Vf = 0x00A2000C,\n+\tHWPfFabricM2iBufferReg = 0x00B30000,\n+\tHWPfFabricI2Mdma_weight = 0x00B31044,\n+\tHwPfFecUl5gIbDebugReg = 0x00B40200,\n+\tHWPfFftConfig0 = 0x00B58004,\n+\tHWPfFftRamPageAccess = 0x00B5800C,\n+\tHWPfFftRamOff = 0x00B58800,\n+\tHWPfDmaConfig0Reg = 0x00B80000,\n+\tHWPfDmaConfig1Reg = 0x00B80004,\n+\tHWPfDmaQmgrAddrReg = 0x00B80008,\n+\tHWPfDmaAxcacheReg = 0x00B80010,\n+\tHWPfDmaAxiControl = 0x00B8002C,\n+\tHWPfDmaQmanen = 0x00B80040,\n+\tHWPfDma4gdlIbThld = 0x00B800CC,\n+\tHWPfDmaCfgRrespBresp = 0x00B80814,\n+\tHWPfDmaDescriptorSignatuture = 0x00B80868,\n+\tHWPfDmaErrorDetectionEn = 0x00B80870,\n+\tHWPfDmaFec5GulDescBaseLoRegVf = 0x00B88020,\n+\tHWPfDmaFec5GulDescBaseHiRegVf = 0x00B88024,\n+\tHWPfDmaFec5GulRespPtrLoRegVf = 0x00B88028,\n+\tHWPfDmaFec5GulRespPtrHiRegVf = 0x00B8802C,\n+\tHWPfDmaFec5GdlDescBaseLoRegVf = 0x00B88040,\n+\tHWPfDmaFec5GdlDescBaseHiRegVf = 0x00B88044,\n+\tHWPfDmaFec5GdlRespPtrLoRegVf = 0x00B88048,\n+\tHWPfDmaFec5GdlRespPtrHiRegVf = 0x00B8804C,\n+\tHWPfDmaFec4GulDescBaseLoRegVf = 0x00B88060,\n+\tHWPfDmaFec4GulDescBaseHiRegVf = 0x00B88064,\n+\tHWPfDmaFec4GulRespPtrLoRegVf = 0x00B88068,\n+\tHWPfDmaFec4GulRespPtrHiRegVf = 0x00B8806C,\n+\tHWPfDmaFec4GdlDescBaseLoRegVf = 0x00B88080,\n+\tHWPfDmaFec4GdlDescBaseHiRegVf = 0x00B88084,\n+\tHWPfDmaFec4GdlRespPtrLoRegVf = 0x00B88088,\n+\tHWPfDmaFec4GdlRespPtrHiRegVf = 0x00B8808C,\n+\tHWPDmaFftDescBaseLoRegVf = 0x00B880A0,\n+\tHWPDmaFftDescBaseHiRegVf = 0x00B880A4,\n+\tHWPDmaFftRespPtrLoRegVf = 0x00B880A8,\n+\tHWPDmaFftRespPtrHiRegVf = 0x00B880AC,\n+\tHWPfQosmonAEvalOverflow0 = 0x00B90008,\n+\tHWPfPermonACntrlRegVf = 0x00B98000,\n+\tHWPfQosmonBEvalOverflow0 = 0x00BA0008,\n+\tHWPfPermonBCntrlRegVf = 0x00BA8000,\n+\tHWPfPermonCCntrlRegVf = 0x00BB8000,\n+\tHWPfHiInfoRingBaseLoRegPf = 0x00C84014,\n+\tHWPfHiInfoRingBaseHiRegPf = 0x00C84018,\n+\tHWPfHiInfoRingPointerRegPf = 0x00C8401C,\n+\tHWPfHiInfoRingIntWrEnRegPf = 0x00C84020,\n+\tHWPfHiBlockTransmitOnErrorEn = 0x00C84038,\n+\tHWPfHiCfgMsiIntWrEnRegPf = 0x00C84040,\n+\tHWPfHiMsixVectorMapperPf = 0x00C84060,\n+\tHWPfHiPfMode = 0x00C84108,\n+\tHWPfHiClkGateHystReg = 0x00C8410C,\n+\tHWPfHiMsiDropEnableReg = 0x00C84114,\n+\tHWPfHiSectionPowerGatingReq = 0x00C84128,\n+\tHWPfHiSectionPowerGatingAck = 0x00C8412C,\n+};\n+\n+/* TIP PF Interrupt numbers */\n+enum {\n+\tACC200_PF_INT_QMGR_AQ_OVERFLOW = 0,\n+\tACC200_PF_INT_DOORBELL_VF_2_PF = 1,\n+\tACC200_PF_INT_ILLEGAL_FORMAT = 2,\n+\tACC200_PF_INT_QMGR_DISABLED_ACCESS = 3,\n+\tACC200_PF_INT_QMGR_AQ_OVERTHRESHOLD = 4,\n+\tACC200_PF_INT_DMA_DL_DESC_IRQ = 5,\n+\tACC200_PF_INT_DMA_UL_DESC_IRQ = 6,\n+\tACC200_PF_INT_DMA_FFT_DESC_IRQ = 7,\n+\tACC200_PF_INT_DMA_UL5G_DESC_IRQ = 8,\n+\tACC200_PF_INT_DMA_DL5G_DESC_IRQ = 9,\n+\tACC200_PF_INT_DMA_MLD_DESC_IRQ = 10,\n+\tACC200_PF_INT_ARAM_ECC_1BIT_ERR = 11,\n+\tACC200_PF_INT_PARITY_ERR = 12,\n+\tACC200_PF_INT_QMGR_ERR = 13,\n+\tACC200_PF_INT_INT_REQ_OVERFLOW = 14,\n+\tACC200_PF_INT_APB_TIMEOUT = 15,\n+};\n+\n+#endif /* ACC200_PF_ENUM_H */\ndiff --git a/drivers/baseband/acc/acc200_pmd.h b/drivers/baseband/acc/acc200_pmd.h\nindex aaa6b7753c..9df1f506ad 100644\n--- a/drivers/baseband/acc/acc200_pmd.h\n+++ b/drivers/baseband/acc/acc200_pmd.h\n@@ -6,6 +6,8 @@\n #define _RTE_ACC200_PMD_H_\n \n #include \"acc_common.h\"\n+#include \"acc200_pf_enum.h\"\n+#include \"acc200_vf_enum.h\"\n \n /* Helper macro for logging */\n #define rte_bbdev_log(level, fmt, ...) \\\n@@ -29,4 +31,165 @@\n #define RTE_ACC200_PF_DEVICE_ID (0x57C0)\n #define RTE_ACC200_VF_DEVICE_ID (0x57C1)\n \n+#define ACC200_MAX_PF_MSIX (256+32)\n+#define ACC200_MAX_VF_MSIX (256+7)\n+\n+/* Values used in writing to the registers */\n+#define ACC200_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */\n+\n+/* Number of Virtual Functions ACC200 supports */\n+#define ACC200_NUM_VFS 16\n+#define ACC200_NUM_QGRPS 16\n+#define ACC200_NUM_AQS 16\n+\n+#define ACC200_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */\n+#define ACC200_VF_ID_SHIFT 4 /* Queue Index Hierarchy */\n+#define ACC200_WORDS_IN_ARAM_SIZE (256 * 1024 / 4)\n+\n+/* Mapping of signals for the available engines */\n+#define ACC200_SIG_UL_5G 0\n+#define ACC200_SIG_UL_5G_LAST 4\n+#define ACC200_SIG_DL_5G 10\n+#define ACC200_SIG_DL_5G_LAST 11\n+#define ACC200_SIG_UL_4G 12\n+#define ACC200_SIG_UL_4G_LAST 16\n+#define ACC200_SIG_DL_4G 21\n+#define ACC200_SIG_DL_4G_LAST 23\n+#define ACC200_SIG_FFT 24\n+#define ACC200_SIG_FFT_LAST 24\n+\n+#define ACC200_NUM_ACCS 5 /* FIXMEFFT */\n+\n+/* ACC200 Configuration */\n+#define ACC200_FABRIC_MODE 0x8000103\n+#define ACC200_CFG_DMA_ERROR 0x3DF\n+#define ACC200_CFG_AXI_CACHE 0x11\n+#define ACC200_CFG_QMGR_HI_P 0x0F0F\n+#define ACC200_RESET_HARD 0x1FF\n+#define ACC200_ENGINES_MAX 9\n+#define ACC200_GPEX_AXIMAP_NUM 17\n+#define ACC200_CLOCK_GATING_EN 0x30000\n+#define ACC200_FFT_CFG_0 0x2001\n+#define ACC200_FFT_RAM_EN 0x80008000\n+#define ACC200_FFT_RAM_DIS 0x0\n+#define ACC200_FFT_RAM_SIZE 512\n+#define ACC200_CLK_EN 0x00010A01\n+#define ACC200_CLK_DIS 0x01F10A01\n+#define ACC200_PG_MASK_0 0x1F\n+#define ACC200_PG_MASK_1 0xF\n+#define ACC200_PG_MASK_2 0x1\n+#define ACC200_PG_MASK_3 0x0\n+#define ACC200_PG_MASK_FFT 1\n+#define ACC200_PG_MASK_4GUL 4\n+#define ACC200_PG_MASK_5GUL 8\n+#define ACC200_STATUS_WAIT 10\n+#define ACC200_STATUS_TO 100\n+\n+struct acc200_registry_addr {\n+\tunsigned int dma_ring_dl5g_hi;\n+\tunsigned int dma_ring_dl5g_lo;\n+\tunsigned int dma_ring_ul5g_hi;\n+\tunsigned int dma_ring_ul5g_lo;\n+\tunsigned int dma_ring_dl4g_hi;\n+\tunsigned int dma_ring_dl4g_lo;\n+\tunsigned int dma_ring_ul4g_hi;\n+\tunsigned int dma_ring_ul4g_lo;\n+\tunsigned int dma_ring_fft_hi;\n+\tunsigned int dma_ring_fft_lo;\n+\tunsigned int ring_size;\n+\tunsigned int info_ring_hi;\n+\tunsigned int info_ring_lo;\n+\tunsigned int info_ring_en;\n+\tunsigned int info_ring_ptr;\n+\tunsigned int tail_ptrs_dl5g_hi;\n+\tunsigned int tail_ptrs_dl5g_lo;\n+\tunsigned int tail_ptrs_ul5g_hi;\n+\tunsigned int tail_ptrs_ul5g_lo;\n+\tunsigned int tail_ptrs_dl4g_hi;\n+\tunsigned int tail_ptrs_dl4g_lo;\n+\tunsigned int tail_ptrs_ul4g_hi;\n+\tunsigned int tail_ptrs_ul4g_lo;\n+\tunsigned int tail_ptrs_fft_hi;\n+\tunsigned int tail_ptrs_fft_lo;\n+\tunsigned int depth_log0_offset;\n+\tunsigned int depth_log1_offset;\n+\tunsigned int qman_group_func;\n+\tunsigned int hi_mode;\n+\tunsigned int pmon_ctrl_a;\n+\tunsigned int pmon_ctrl_b;\n+\tunsigned int pmon_ctrl_c;\n+};\n+\n+/* Structure holding registry addresses for PF */\n+static const struct acc200_registry_addr pf_reg_addr = {\n+\t.dma_ring_dl5g_hi = HWPfDmaFec5GdlDescBaseHiRegVf,\n+\t.dma_ring_dl5g_lo = HWPfDmaFec5GdlDescBaseLoRegVf,\n+\t.dma_ring_ul5g_hi = HWPfDmaFec5GulDescBaseHiRegVf,\n+\t.dma_ring_ul5g_lo = HWPfDmaFec5GulDescBaseLoRegVf,\n+\t.dma_ring_dl4g_hi = HWPfDmaFec4GdlDescBaseHiRegVf,\n+\t.dma_ring_dl4g_lo = HWPfDmaFec4GdlDescBaseLoRegVf,\n+\t.dma_ring_ul4g_hi = HWPfDmaFec4GulDescBaseHiRegVf,\n+\t.dma_ring_ul4g_lo = HWPfDmaFec4GulDescBaseLoRegVf,\n+\t.dma_ring_fft_hi = HWPDmaFftDescBaseHiRegVf,\n+\t.dma_ring_fft_lo = HWPDmaFftDescBaseLoRegVf,\n+\t.ring_size = HWPfQmgrRingSizeVf,\n+\t.info_ring_hi = HWPfHiInfoRingBaseHiRegPf,\n+\t.info_ring_lo = HWPfHiInfoRingBaseLoRegPf,\n+\t.info_ring_en = HWPfHiInfoRingIntWrEnRegPf,\n+\t.info_ring_ptr = HWPfHiInfoRingPointerRegPf,\n+\t.tail_ptrs_dl5g_hi = HWPfDmaFec5GdlRespPtrHiRegVf,\n+\t.tail_ptrs_dl5g_lo = HWPfDmaFec5GdlRespPtrLoRegVf,\n+\t.tail_ptrs_ul5g_hi = HWPfDmaFec5GulRespPtrHiRegVf,\n+\t.tail_ptrs_ul5g_lo = HWPfDmaFec5GulRespPtrLoRegVf,\n+\t.tail_ptrs_dl4g_hi = HWPfDmaFec4GdlRespPtrHiRegVf,\n+\t.tail_ptrs_dl4g_lo = HWPfDmaFec4GdlRespPtrLoRegVf,\n+\t.tail_ptrs_ul4g_hi = HWPfDmaFec4GulRespPtrHiRegVf,\n+\t.tail_ptrs_ul4g_lo = HWPfDmaFec4GulRespPtrLoRegVf,\n+\t.tail_ptrs_fft_hi = HWPDmaFftRespPtrHiRegVf,\n+\t.tail_ptrs_fft_lo = HWPDmaFftRespPtrLoRegVf,\n+\t.depth_log0_offset = HWPfQmgrGrpDepthLog20Vf,\n+\t.depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,\n+\t.qman_group_func = HWPfQmgrGrpFunction0,\n+\t.hi_mode = HWPfHiMsixVectorMapperPf,\n+\t.pmon_ctrl_a = HWPfPermonACntrlRegVf,\n+\t.pmon_ctrl_b = HWPfPermonBCntrlRegVf,\n+\t.pmon_ctrl_c = HWPfPermonCCntrlRegVf,\n+};\n+\n+/* Structure holding registry addresses for VF */\n+static const struct acc200_registry_addr vf_reg_addr = {\n+\t.dma_ring_dl5g_hi = HWVfDmaFec5GdlDescBaseHiRegVf,\n+\t.dma_ring_dl5g_lo = HWVfDmaFec5GdlDescBaseLoRegVf,\n+\t.dma_ring_ul5g_hi = HWVfDmaFec5GulDescBaseHiRegVf,\n+\t.dma_ring_ul5g_lo = HWVfDmaFec5GulDescBaseLoRegVf,\n+\t.dma_ring_dl4g_hi = HWVfDmaFec4GdlDescBaseHiRegVf,\n+\t.dma_ring_dl4g_lo = HWVfDmaFec4GdlDescBaseLoRegVf,\n+\t.dma_ring_ul4g_hi = HWVfDmaFec4GulDescBaseHiRegVf,\n+\t.dma_ring_ul4g_lo = HWVfDmaFec4GulDescBaseLoRegVf,\n+\t.dma_ring_fft_hi = HWVfDmaFftDescBaseHiRegVf,\n+\t.dma_ring_fft_lo = HWVfDmaFftDescBaseLoRegVf,\n+\t.ring_size = HWVfQmgrRingSizeVf,\n+\t.info_ring_hi = HWVfHiInfoRingBaseHiVf,\n+\t.info_ring_lo = HWVfHiInfoRingBaseLoVf,\n+\t.info_ring_en = HWVfHiInfoRingIntWrEnVf,\n+\t.info_ring_ptr = HWVfHiInfoRingPointerVf,\n+\t.tail_ptrs_dl5g_hi = HWVfDmaFec5GdlRespPtrHiRegVf,\n+\t.tail_ptrs_dl5g_lo = HWVfDmaFec5GdlRespPtrLoRegVf,\n+\t.tail_ptrs_ul5g_hi = HWVfDmaFec5GulRespPtrHiRegVf,\n+\t.tail_ptrs_ul5g_lo = HWVfDmaFec5GulRespPtrLoRegVf,\n+\t.tail_ptrs_dl4g_hi = HWVfDmaFec4GdlRespPtrHiRegVf,\n+\t.tail_ptrs_dl4g_lo = HWVfDmaFec4GdlRespPtrLoRegVf,\n+\t.tail_ptrs_ul4g_hi = HWVfDmaFec4GulRespPtrHiRegVf,\n+\t.tail_ptrs_ul4g_lo = HWVfDmaFec4GulRespPtrLoRegVf,\n+\t.tail_ptrs_fft_hi = HWVfDmaFftRespPtrHiRegVf,\n+\t.tail_ptrs_fft_lo = HWVfDmaFftRespPtrLoRegVf,\n+\t.depth_log0_offset = HWVfQmgrGrpDepthLog20Vf,\n+\t.depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,\n+\t.qman_group_func = HWVfQmgrGrpFunction0Vf,\n+\t.hi_mode = HWVfHiMsixVectorMapperVf,\n+\t.pmon_ctrl_a = HWVfPmACntrlRegVf,\n+\t.pmon_ctrl_b = HWVfPmBCntrlRegVf,\n+\t.pmon_ctrl_c = HWVfPmCCntrlRegVf,\n+};\n+\n #endif /* _RTE_ACC200_PMD_H_ */\ndiff --git a/drivers/baseband/acc/acc200_vf_enum.h b/drivers/baseband/acc/acc200_vf_enum.h\nnew file mode 100644\nindex 0000000000..0d354208ab\n--- /dev/null\n+++ b/drivers/baseband/acc/acc200_vf_enum.h\n@@ -0,0 +1,83 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+#ifndef ACC200_VF_ENUM_H\n+#define ACC200_VF_ENUM_H\n+\n+/*\n+ * ACC200 Register mapping on VF BAR0\n+ * This is automatically generated from RDL, format may change with new RDL\n+ */\n+enum {\n+\tHWVfQmgrIngressAq = 0x00000000,\n+\tHWVfHiVfToPfDbellVf = 0x00000800,\n+\tHWVfHiPfToVfDbellVf = 0x00000808,\n+\tHWVfHiInfoRingBaseLoVf = 0x00000810,\n+\tHWVfHiInfoRingBaseHiVf = 0x00000814,\n+\tHWVfHiInfoRingPointerVf = 0x00000818,\n+\tHWVfHiInfoRingIntWrEnVf = 0x00000820,\n+\tHWVfHiInfoRingPf2VfWrEnVf = 0x00000824,\n+\tHWVfHiMsixVectorMapperVf = 0x00000860,\n+\tHWVfDmaFec5GulDescBaseLoRegVf = 0x00000920,\n+\tHWVfDmaFec5GulDescBaseHiRegVf = 0x00000924,\n+\tHWVfDmaFec5GulRespPtrLoRegVf = 0x00000928,\n+\tHWVfDmaFec5GulRespPtrHiRegVf = 0x0000092C,\n+\tHWVfDmaFec5GdlDescBaseLoRegVf = 0x00000940,\n+\tHWVfDmaFec5GdlDescBaseHiRegVf = 0x00000944,\n+\tHWVfDmaFec5GdlRespPtrLoRegVf = 0x00000948,\n+\tHWVfDmaFec5GdlRespPtrHiRegVf = 0x0000094C,\n+\tHWVfDmaFec4GulDescBaseLoRegVf = 0x00000960,\n+\tHWVfDmaFec4GulDescBaseHiRegVf = 0x00000964,\n+\tHWVfDmaFec4GulRespPtrLoRegVf = 0x00000968,\n+\tHWVfDmaFec4GulRespPtrHiRegVf = 0x0000096C,\n+\tHWVfDmaFec4GdlDescBaseLoRegVf = 0x00000980,\n+\tHWVfDmaFec4GdlDescBaseHiRegVf = 0x00000984,\n+\tHWVfDmaFec4GdlRespPtrLoRegVf = 0x00000988,\n+\tHWVfDmaFec4GdlRespPtrHiRegVf = 0x0000098C,\n+\tHWVfDmaFftDescBaseLoRegVf = 0x000009A0,\n+\tHWVfDmaFftDescBaseHiRegVf = 0x000009A4,\n+\tHWVfDmaFftRespPtrLoRegVf = 0x000009A8,\n+\tHWVfDmaFftRespPtrHiRegVf = 0x000009AC,\n+\tHWVfQmgrAqResetVf = 0x00000E00,\n+\tHWVfQmgrRingSizeVf = 0x00000E04,\n+\tHWVfQmgrGrpDepthLog20Vf = 0x00000E08,\n+\tHWVfQmgrGrpDepthLog21Vf = 0x00000E0C,\n+\tHWVfQmgrGrpFunction0Vf = 0x00000E10,\n+\tHWVfQmgrGrpFunction1Vf = 0x00000E14,\n+\tHWVfPmACntrlRegVf = 0x00000F40,\n+\tHWVfPmACountVf = 0x00000F48,\n+\tHWVfPmAKCntLoVf = 0x00000F50,\n+\tHWVfPmAKCntHiVf = 0x00000F54,\n+\tHWVfPmADeltaCntLoVf = 0x00000F60,\n+\tHWVfPmADeltaCntHiVf = 0x00000F64,\n+\tHWVfPmBCntrlRegVf = 0x00000F80,\n+\tHWVfPmBCountVf = 0x00000F88,\n+\tHWVfPmBKCntLoVf = 0x00000F90,\n+\tHWVfPmBKCntHiVf = 0x00000F94,\n+\tHWVfPmBDeltaCntLoVf = 0x00000FA0,\n+\tHWVfPmBDeltaCntHiVf = 0x00000FA4,\n+\tHWVfPmCCntrlRegVf = 0x00000FC0,\n+\tHWVfPmCCountVf = 0x00000FC8,\n+\tHWVfPmCKCntLoVf = 0x00000FD0,\n+\tHWVfPmCKCntHiVf = 0x00000FD4,\n+\tHWVfPmCDeltaCntLoVf = 0x00000FE0,\n+\tHWVfPmCDeltaCntHiVf = 0x00000FE4\n+};\n+\n+/* TIP VF Interrupt numbers */\n+enum {\n+\tACC200_VF_INT_QMGR_AQ_OVERFLOW = 0,\n+\tACC200_VF_INT_DOORBELL_PF_2_VF = 1,\n+\tACC200_VF_INT_ILLEGAL_FORMAT = 2,\n+\tACC200_VF_INT_QMGR_DISABLED_ACCESS = 3,\n+\tACC200_VF_INT_QMGR_AQ_OVERTHRESHOLD = 4,\n+\tACC200_VF_INT_DMA_DL_DESC_IRQ = 5,\n+\tACC200_VF_INT_DMA_UL_DESC_IRQ = 6,\n+\tACC200_VF_INT_DMA_FFT_DESC_IRQ = 7,\n+\tACC200_VF_INT_DMA_UL5G_DESC_IRQ = 8,\n+\tACC200_VF_INT_DMA_DL5G_DESC_IRQ = 9,\n+\tACC200_VF_INT_DMA_MLD_DESC_IRQ = 10,\n+};\n+\n+#endif /* ACC200_VF_ENUM_H */\n", "prefixes": [ "v9", "05/14" ] }