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GET /api/patches/117599/?format=api
{ "id": 117599, "url": "https://patches.dpdk.org/api/patches/117599/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221007174336.54354-21-andrew.boyer@amd.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221007174336.54354-21-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221007174336.54354-21-andrew.boyer@amd.com", "date": "2022-10-07T17:43:21", "name": "[20/35] net/ionic: overhaul transmit side for performance", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fb7b17ebe9ce371a6ae763dec560277b2abc61cd", "submitter": { "id": 2861, "url": "https://patches.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221007174336.54354-21-andrew.boyer@amd.com/mbox/", "series": [ { "id": 25037, "url": "https://patches.dpdk.org/api/series/25037/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25037", "date": "2022-10-07T17:43:01", "name": "net/ionic: updates for 22.11 release", "version": 1, "mbox": "https://patches.dpdk.org/series/25037/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117599/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/117599/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 11A7CA04FD;\n\tFri, 7 Oct 2022 19:46:32 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 13DA142BCE;\n\tFri, 7 Oct 2022 19:44:54 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40])\n by mails.dpdk.org (Postfix) with ESMTP id 8D23542BBC\n for <dev@dpdk.org>; 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helo=SATLEXMB04.amd.com; pr=C", "From": "Andrew Boyer <andrew.boyer@amd.com>", "To": "<dev@dpdk.org>", "CC": "Andrew Boyer <andrew.boyer@amd.com>", "Subject": "[PATCH 20/35] net/ionic: overhaul transmit side for performance", "Date": "Fri, 7 Oct 2022 10:43:21 -0700", "Message-ID": "<20221007174336.54354-21-andrew.boyer@amd.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20221007174336.54354-1-andrew.boyer@amd.com>", "References": "<20221007174336.54354-1-andrew.boyer@amd.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT003:EE_|SJ0PR12MB6781:EE_", "X-MS-Office365-Filtering-Correlation-Id": "6adca26e-9212-43c9-8656-08daa88ba283", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n ShdaMs+vcZJd0H64coLzlaYciTk6CPwr2U1s/KrSAjoPh0QL5qaoIPCRfupHqo1ArrkU5w/kY7sNI8snGP185KC2+O1ST6rh2Jh9x5c1eClYDDoYJuR/D1ILgaOS3Zr7NeW3Mb+nwfHL1bmjnWhabxmRlE5nxYwsdMOYCF7u3Q6H4KyC1raP2JJdM4qvH0An17RvwB3TnUyHWGKe39bZWHdfb92FfqWJ8UokwwLjCovFrM9eutecDmn/B2634Fu8yrYM7Zi0G6w0KRUo7qj4I5F0q0BQsTfhy6PSYz+YAMk6dLjTXD7t6eN2eP5fCXRGW2/rkBWYHP+2o9Vhik11+Jl0aRZzJrP+d/dlwMua6yYQzfcUyuNwW0hI/i9gcMDfDgbKtjcftM31X6wa5wSptWEtf+X6nh3JrbG3rvWBIU8mMZE8O2fEEtVNTIRCKNhggpZoWNUK1fGL5iS/TEsh08uWVpHA0c8tFpFBTa0z+UzyY59j6e+NwKN7xHIiif26NBelmrMwav+w9DEqUV+IkdEr9tU2dEuM1hiW2/HNBd4w/CAkCcKVpTDyx/B08kTXw4JH7+6/+xg0SBcVBY52iXNSkE1toDAm1swOieC7VKhcSMP3YBj+6sYrsi8t4tJsmLskTjplMekgugEf45gyvIo63fN8A7vYkyDFwKCh0EYS9yWeYbPgRIIuq2KY8Pe3IfCsjN8dnuOOSLQpkI+z65GjLBeaeps1KwWPeGfFELC2z1BiwVSgMCmpvPPrk3T6hxlgg689ykluA2InB8x9ce4iZcFX5qFKmKkYsGD//UIn3WJycegXnPrD3+QKk4uS", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230022)(4636009)(396003)(39860400002)(346002)(376002)(136003)(451199015)(46966006)(36840700001)(40470700004)(8936002)(478600001)(6916009)(316002)(8676002)(70586007)(4326008)(6666004)(70206006)(82310400005)(2906002)(5660300002)(26005)(41300700001)(82740400003)(16526019)(186003)(1076003)(2616005)(336012)(40460700003)(44832011)(36860700001)(426003)(47076005)(36756003)(356005)(86362001)(81166007)(83380400001)(40480700001)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 Oct 2022 17:44:50.5076 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6adca26e-9212-43c9-8656-08daa88ba283", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT003.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ0PR12MB6781", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Linearize Tx mbuf chains in the info array.\nThis avoids walking the mbuf chain during flush.\nMove a few branches out of the hot path.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\n---\n drivers/net/ionic/ionic_lif.c | 2 +-\n drivers/net/ionic/ionic_rxtx.c | 143 ++++++++++++++++++++-------------\n 2 files changed, 87 insertions(+), 58 deletions(-)", "diff": "diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c\nindex db5d42dda6..ac9b69fc70 100644\n--- a/drivers/net/ionic/ionic_lif.c\n+++ b/drivers/net/ionic/ionic_lif.c\n@@ -817,7 +817,7 @@ ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index,\n \t\t\"tx\",\n \t\tflags,\n \t\tntxq_descs,\n-\t\t1,\n+\t\tnum_segs_fw,\n \t\tsizeof(struct ionic_txq_desc),\n \t\tsizeof(struct ionic_txq_comp),\n \t\tsizeof(struct ionic_txq_sg_desc_v1),\ndiff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c\nindex bb6ca019d9..53b0add228 100644\n--- a/drivers/net/ionic/ionic_rxtx.c\n+++ b/drivers/net/ionic/ionic_rxtx.c\n@@ -64,7 +64,7 @@ ionic_tx_empty(struct ionic_tx_qcq *txq)\n {\n \tstruct ionic_queue *q = &txq->qcq.q;\n \n-\tionic_empty_array(q->info, q->num_descs, 0);\n+\tionic_empty_array(q->info, q->num_descs * q->num_segs, 0);\n }\n \n static void __rte_cold\n@@ -102,50 +102,49 @@ ionic_tx_flush(struct ionic_tx_qcq *txq)\n {\n \tstruct ionic_cq *cq = &txq->qcq.cq;\n \tstruct ionic_queue *q = &txq->qcq.q;\n-\tstruct rte_mbuf *txm, *next;\n-\tstruct ionic_txq_comp *cq_desc_base = cq->base;\n-\tstruct ionic_txq_comp *cq_desc;\n+\tstruct rte_mbuf *txm;\n+\tstruct ionic_txq_comp *cq_desc, *cq_desc_base = cq->base;\n \tvoid **info;\n-\tu_int32_t comp_index = (u_int32_t)-1;\n+\tuint32_t i;\n \n \tcq_desc = &cq_desc_base[cq->tail_idx];\n+\n \twhile (color_match(cq_desc->color, cq->done_color)) {\n \t\tcq->tail_idx = Q_NEXT_TO_SRVC(cq, 1);\n-\n-\t\t/* Prefetch the next 4 descriptors (not really useful here) */\n-\t\tif ((cq->tail_idx & 0x3) == 0)\n-\t\t\trte_prefetch0(&cq_desc_base[cq->tail_idx]);\n-\n \t\tif (cq->tail_idx == 0)\n \t\t\tcq->done_color = !cq->done_color;\n \n-\t\tcomp_index = cq_desc->comp_index;\n+\t\t/* Prefetch 4 x 16B comp at cq->tail_idx + 4 */\n+\t\tif ((cq->tail_idx & 0x3) == 0)\n+\t\t\trte_prefetch0(&cq_desc_base[Q_NEXT_TO_SRVC(cq, 4)]);\n \n-\t\tcq_desc = &cq_desc_base[cq->tail_idx];\n-\t}\n+\t\twhile (q->tail_idx != rte_le_to_cpu_16(cq_desc->comp_index)) {\n+\t\t\t/* Prefetch 8 mbuf ptrs at q->tail_idx + 2 */\n+\t\t\trte_prefetch0(IONIC_INFO_PTR(q, Q_NEXT_TO_SRVC(q, 2)));\n \n-\tif (comp_index != (u_int32_t)-1) {\n-\t\twhile (q->tail_idx != comp_index) {\n-\t\t\tinfo = IONIC_INFO_PTR(q, q->tail_idx);\n+\t\t\t/* Prefetch next mbuf */\n+\t\t\tvoid **next_info =\n+\t\t\t\tIONIC_INFO_PTR(q, Q_NEXT_TO_SRVC(q, 1));\n+\t\t\tif (next_info[0])\n+\t\t\t\trte_mbuf_prefetch_part2(next_info[0]);\n+\t\t\tif (next_info[1])\n+\t\t\t\trte_mbuf_prefetch_part2(next_info[1]);\n \n-\t\t\tq->tail_idx = Q_NEXT_TO_SRVC(q, 1);\n+\t\t\tinfo = IONIC_INFO_PTR(q, q->tail_idx);\n+\t\t\tfor (i = 0; i < q->num_segs; i++) {\n+\t\t\t\ttxm = info[i];\n+\t\t\t\tif (!txm)\n+\t\t\t\t\tbreak;\n \n-\t\t\t/* Prefetch the next 4 descriptors */\n-\t\t\tif ((q->tail_idx & 0x3) == 0)\n-\t\t\t\t/* q desc info */\n-\t\t\t\trte_prefetch0(&q->info[q->tail_idx]);\n-\n-\t\t\t/*\n-\t\t\t * Note: you can just use rte_pktmbuf_free,\n-\t\t\t * but this loop is faster\n-\t\t\t */\n-\t\t\ttxm = info[0];\n-\t\t\twhile (txm != NULL) {\n-\t\t\t\tnext = txm->next;\n \t\t\t\trte_pktmbuf_free_seg(txm);\n-\t\t\t\ttxm = next;\n+\n+\t\t\t\tinfo[i] = NULL;\n \t\t\t}\n+\n+\t\t\tq->tail_idx = Q_NEXT_TO_SRVC(q, 1);\n \t\t}\n+\n+\t\tcq_desc = &cq_desc_base[cq->tail_idx];\n \t}\n }\n \n@@ -327,9 +326,12 @@ ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc,\n \t\tuint16_t vlan_tci, bool has_vlan,\n \t\tbool start, bool done)\n {\n+\tstruct rte_mbuf *txm_seg;\n \tvoid **info;\n \tuint64_t cmd;\n \tuint8_t flags = 0;\n+\tint i;\n+\n \tflags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;\n \tflags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;\n \tflags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0;\n@@ -345,7 +347,13 @@ ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc,\n \n \tif (done) {\n \t\tinfo = IONIC_INFO_PTR(q, q->head_idx);\n-\t\tinfo[0] = txm;\n+\n+\t\t/* Walk the mbuf chain to stash pointers in the array */\n+\t\ttxm_seg = txm;\n+\t\tfor (i = 0; i < txm->nb_segs; i++) {\n+\t\t\tinfo[i] = txm_seg;\n+\t\t\ttxm_seg = txm_seg->next;\n+\t\t}\n \t}\n \n \tq->head_idx = Q_NEXT_TO_POST(q, 1);\n@@ -497,8 +505,7 @@ ionic_tx(struct ionic_tx_qcq *txq, struct rte_mbuf *txm)\n \tstruct ionic_tx_stats *stats = &txq->stats;\n \tstruct rte_mbuf *txm_seg;\n \tvoid **info;\n-\tbool encap;\n-\tbool has_vlan;\n+\trte_iova_t data_iova;\n \tuint64_t ol_flags = txm->ol_flags;\n \tuint64_t addr, cmd;\n \tuint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE;\n@@ -524,32 +531,44 @@ ionic_tx(struct ionic_tx_qcq *txq, struct rte_mbuf *txm)\n \tif (opcode == IONIC_TXQ_DESC_OPCODE_CSUM_NONE)\n \t\tstats->no_csum++;\n \n-\thas_vlan = (ol_flags & RTE_MBUF_F_TX_VLAN);\n-\tencap = ((ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM) ||\n-\t\t\t(ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM)) &&\n-\t\t\t((ol_flags & RTE_MBUF_F_TX_OUTER_IPV4) ||\n-\t\t\t (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6));\n+\tif (((ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM) ||\n+\t (ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM)) &&\n+\t ((ol_flags & RTE_MBUF_F_TX_OUTER_IPV4) ||\n+\t (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6))) {\n+\t\tflags |= IONIC_TXQ_DESC_FLAG_ENCAP;\n+\t}\n \n-\tflags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;\n-\tflags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;\n+\tif (ol_flags & RTE_MBUF_F_TX_VLAN) {\n+\t\tflags |= IONIC_TXQ_DESC_FLAG_VLAN;\n+\t\tdesc->vlan_tci = rte_cpu_to_le_16(txm->vlan_tci);\n+\t}\n \n \taddr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm));\n \n \tcmd = encode_txq_desc_cmd(opcode, flags, txm->nb_segs - 1, addr);\n \tdesc->cmd = rte_cpu_to_le_64(cmd);\n \tdesc->len = rte_cpu_to_le_16(txm->data_len);\n-\tdesc->vlan_tci = rte_cpu_to_le_16(txm->vlan_tci);\n \n \tinfo[0] = txm;\n \n-\telem = sg_desc_base[q->head_idx].elems;\n+\tif (txm->nb_segs > 1) {\n+\t\ttxm_seg = txm->next;\n \n-\ttxm_seg = txm->next;\n-\twhile (txm_seg != NULL) {\n-\t\telem->len = rte_cpu_to_le_16(txm_seg->data_len);\n-\t\telem->addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm_seg));\n-\t\telem++;\n-\t\ttxm_seg = txm_seg->next;\n+\t\telem = sg_desc_base[q->head_idx].elems;\n+\n+\t\twhile (txm_seg != NULL) {\n+\t\t\t/* Stash the mbuf ptr in the array */\n+\t\t\tinfo++;\n+\t\t\t*info = txm_seg;\n+\n+\t\t\t/* Configure the SGE */\n+\t\t\tdata_iova = rte_mbuf_data_iova(txm_seg);\n+\t\t\telem->len = rte_cpu_to_le_16(txm_seg->data_len);\n+\t\t\telem->addr = rte_cpu_to_le_64(data_iova);\n+\t\t\telem++;\n+\n+\t\t\ttxm_seg = txm_seg->next;\n+\t\t}\n \t}\n \n \tq->head_idx = Q_NEXT_TO_POST(q, 1);\n@@ -565,11 +584,19 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tstruct ionic_queue *q = &txq->qcq.q;\n \tstruct ionic_tx_stats *stats = &txq->stats;\n \tstruct rte_mbuf *mbuf;\n-\tuint32_t next_q_head_idx;\n \tuint32_t bytes_tx = 0;\n \tuint16_t nb_avail, nb_tx = 0;\n \tint err;\n \n+\tstruct ionic_txq_desc *desc_base = q->base;\n+\trte_prefetch0(&desc_base[q->head_idx]);\n+\trte_prefetch0(IONIC_INFO_PTR(q, q->head_idx));\n+\n+\tif (tx_pkts) {\n+\t\trte_mbuf_prefetch_part1(tx_pkts[0]);\n+\t\trte_mbuf_prefetch_part2(tx_pkts[0]);\n+\t}\n+\n \t/* Cleaning old buffers */\n \tionic_tx_flush(txq);\n \n@@ -580,11 +607,13 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t}\n \n \twhile (nb_tx < nb_pkts) {\n-\t\tnext_q_head_idx = Q_NEXT_TO_POST(q, 1);\n-\t\tif ((next_q_head_idx & 0x3) == 0) {\n-\t\t\tstruct ionic_txq_desc *desc_base = q->base;\n-\t\t\trte_prefetch0(&desc_base[next_q_head_idx]);\n-\t\t\trte_prefetch0(&q->info[next_q_head_idx]);\n+\t\tuint16_t next_idx = Q_NEXT_TO_POST(q, 1);\n+\t\trte_prefetch0(&desc_base[next_idx]);\n+\t\trte_prefetch0(IONIC_INFO_PTR(q, next_idx));\n+\n+\t\tif (nb_tx + 1 < nb_pkts) {\n+\t\t\trte_mbuf_prefetch_part1(tx_pkts[nb_tx + 1]);\n+\t\t\trte_mbuf_prefetch_part2(tx_pkts[nb_tx + 1]);\n \t\t}\n \n \t\tmbuf = tx_pkts[nb_tx];\n@@ -605,10 +634,10 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tif (nb_tx > 0) {\n \t\trte_wmb();\n \t\tionic_q_flush(q);\n-\t}\n \n-\tstats->packets += nb_tx;\n-\tstats->bytes += bytes_tx;\n+\t\tstats->packets += nb_tx;\n+\t\tstats->bytes += bytes_tx;\n+\t}\n \n \treturn nb_tx;\n }\n", "prefixes": [ "20/35" ] }