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GET /api/patches/117588/?format=api
{ "id": 117588, "url": "https://patches.dpdk.org/api/patches/117588/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221007174336.54354-9-andrew.boyer@amd.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221007174336.54354-9-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221007174336.54354-9-andrew.boyer@amd.com", "date": "2022-10-07T17:43:09", "name": "[08/35] net/ionic: update MTU calculations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9bbbfd586794b53128dc20c3f5e83688bcc9d2b6", "submitter": { "id": 2861, "url": "https://patches.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221007174336.54354-9-andrew.boyer@amd.com/mbox/", "series": [ { "id": 25037, "url": "https://patches.dpdk.org/api/series/25037/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25037", "date": "2022-10-07T17:43:01", "name": "net/ionic: updates for 22.11 release", "version": 1, "mbox": "https://patches.dpdk.org/series/25037/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117588/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/117588/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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b=Jbu3i+m2uYvfR6Uo6zsphIFaAQ4evCFaLZn/h5QD4nKJPpOLIF+NYh2D65ZWfpYZNVAbvX5ajwvRCSLusVLOfWg707xUYvdErVTzVTFOPR78mNntB4SAjQ0KNTFHWEuXa9srnN5akYHAmwgfbu6oHFsnXTzyszGm2V/01CFf7/E=", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 165.204.84.17)\n smtp.mailfrom=amd.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=amd.com;", "Received-SPF": "Pass (protection.outlook.com: domain of amd.com designates\n 165.204.84.17 as permitted sender) receiver=protection.outlook.com;\n client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C", "From": "Andrew Boyer <andrew.boyer@amd.com>", "To": "<dev@dpdk.org>", "CC": "Andrew Boyer <andrew.boyer@amd.com>,\n R Mohamed Shah <mohamedshah.r@amd.com>", "Subject": "[PATCH 08/35] net/ionic: update MTU calculations", "Date": "Fri, 7 Oct 2022 10:43:09 -0700", "Message-ID": "<20221007174336.54354-9-andrew.boyer@amd.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": 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SFS:(13230022)(4636009)(136003)(39860400002)(376002)(396003)(346002)(451199015)(46966006)(40470700004)(36840700001)(5660300002)(86362001)(36756003)(41300700001)(15650500001)(44832011)(8936002)(81166007)(4326008)(356005)(40460700003)(2906002)(40480700001)(186003)(70206006)(6666004)(70586007)(478600001)(6916009)(54906003)(36860700001)(8676002)(26005)(47076005)(426003)(82740400003)(16526019)(83380400001)(316002)(1076003)(2616005)(82310400005)(336012)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 Oct 2022 17:44:32.7932 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e35325f7-10a3-4794-20d1-08daa88b97f2", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT055.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR12MB7107", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Test min and max MTU against values read from firmware, for correctness.\nUpdate the firmware field name, for clarity.\nThe device must be stopped before changing MTU, for correctness.\nStore the calculated frame size in the queue, for performance.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\nSigned-off-by: R Mohamed Shah <mohamedshah.r@amd.com>\n---\n drivers/net/ionic/ionic_dev.h | 5 +++-\n drivers/net/ionic/ionic_ethdev.c | 40 +++++++++++++++++++++-----------\n drivers/net/ionic/ionic_if.h | 8 +++----\n drivers/net/ionic/ionic_lif.c | 10 +++-----\n drivers/net/ionic/ionic_lif.h | 4 +++-\n drivers/net/ionic/ionic_rxtx.c | 26 +++++++++------------\n 6 files changed, 51 insertions(+), 42 deletions(-)", "diff": "diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h\nindex 3b902554b8..42ba9ef5aa 100644\n--- a/drivers/net/ionic/ionic_dev.h\n+++ b/drivers/net/ionic/ionic_dev.h\n@@ -11,8 +11,11 @@\n #include \"ionic_if.h\"\n #include \"ionic_regs.h\"\n \n+#define VLAN_TAG_SIZE\t\t\t4\n+\n #define IONIC_MIN_MTU\t\t\tRTE_ETHER_MIN_MTU\n-#define IONIC_MAX_MTU\t\t\t9194\n+#define IONIC_MAX_MTU\t\t\t9378\n+#define IONIC_ETH_OVERHEAD\t\t(RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE)\n \n #define IONIC_MAX_RING_DESC\t\t32768\n #define IONIC_MIN_RING_DESC\t\t16\ndiff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c\nindex 387042c080..815b7e3c9e 100644\n--- a/drivers/net/ionic/ionic_ethdev.c\n+++ b/drivers/net/ionic/ionic_ethdev.c\n@@ -343,18 +343,17 @@ static int\n ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)\n {\n \tstruct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);\n-\tint err;\n \n-\tIONIC_PRINT_CALL();\n+\tif (lif->state & IONIC_LIF_F_UP) {\n+\t\tIONIC_PRINT(ERR, \"Stop %s before setting mtu\", lif->name);\n+\t\treturn -EBUSY;\n+\t}\n \n-\t/*\n-\t * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU\n-\t * is done by the API.\n-\t */\n+\t/* Note: mtu check against min/max is done by the API */\n+\tIONIC_PRINT(INFO, \"Setting mtu %u\", mtu);\n \n-\terr = ionic_lif_change_mtu(lif, mtu);\n-\tif (err)\n-\t\treturn err;\n+\t/* Update the frame size used by the Rx path */\n+\tlif->frame_size = mtu + IONIC_ETH_OVERHEAD;\n \n \treturn 0;\n }\n@@ -376,12 +375,16 @@ ionic_dev_info_get(struct rte_eth_dev *eth_dev,\n \t\trte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]);\n \n \t/* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */\n-\tdev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN;\n-\tdev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN;\n-\tdev_info->max_mac_addrs = adapter->max_mac_addrs;\n-\tdev_info->min_mtu = IONIC_MIN_MTU;\n-\tdev_info->max_mtu = IONIC_MAX_MTU;\n+\tdev_info->min_mtu = RTE_MAX((uint32_t)IONIC_MIN_MTU,\n+\t\t\trte_le_to_cpu_32(ident->lif.eth.min_mtu));\n+\tdev_info->max_mtu = RTE_MIN((uint32_t)IONIC_MAX_MTU,\n+\t\t\trte_le_to_cpu_32(ident->lif.eth.max_mtu));\n+\tdev_info->min_rx_bufsize = dev_info->min_mtu + IONIC_ETH_OVERHEAD;\n+\tdev_info->max_rx_pktlen = dev_info->max_mtu + IONIC_ETH_OVERHEAD;\n+\tdev_info->max_lro_pkt_size =\n+\t\teth_dev->data->dev_conf.rxmode.max_lro_pkt_size;\n \n+\tdev_info->max_mac_addrs = adapter->max_mac_addrs;\n \tdev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE;\n \tdev_info->reta_size = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz);\n \tdev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL;\n@@ -889,6 +892,15 @@ ionic_dev_start(struct rte_eth_dev *eth_dev)\n \tif (dev_conf->lpbk_mode)\n \t\tIONIC_PRINT(WARNING, \"Loopback mode not supported\");\n \n+\tlif->frame_size = eth_dev->data->mtu + IONIC_ETH_OVERHEAD;\n+\n+\terr = ionic_lif_change_mtu(lif, eth_dev->data->mtu);\n+\tif (err) {\n+\t\tIONIC_PRINT(ERR, \"Cannot set LIF frame size %u: %d\",\n+\t\t\tlif->frame_size, err);\n+\t\treturn err;\n+\t}\n+\n \terr = ionic_lif_start(lif);\n \tif (err) {\n \t\tIONIC_PRINT(ERR, \"Cannot start LIF: %d\", err);\ndiff --git a/drivers/net/ionic/ionic_if.h b/drivers/net/ionic/ionic_if.h\nindex 761d366c71..05ab620167 100644\n--- a/drivers/net/ionic/ionic_if.h\n+++ b/drivers/net/ionic/ionic_if.h\n@@ -401,8 +401,8 @@ union ionic_lif_config {\n * @version: Ethernet identify structure version\n * @max_ucast_filters: Number of perfect unicast addresses supported\n * @max_mcast_filters: Number of perfect multicast addresses supported\n- * @min_frame_size: Minimum size of frames to be sent\n- * @max_frame_size: Maximum size of frames to be sent\n+ * @min_mtu: Minimum MTU of frames to be sent\n+ * @max_mtu: Maximum MTU of frames to be sent\n * @config: LIF config struct with features, mtu, mac, q counts\n *\n * @rdma: RDMA identify structure\n@@ -434,8 +434,8 @@ union ionic_lif_identity {\n \t\t\t__le32 max_ucast_filters;\n \t\t\t__le32 max_mcast_filters;\n \t\t\t__le16 rss_ind_tbl_sz;\n-\t\t\t__le32 min_frame_size;\n-\t\t\t__le32 max_frame_size;\n+\t\t\t__le32 min_mtu;\n+\t\t\t__le32 max_mtu;\n \t\t\tu8 rsvd2[106];\n \t\t\tunion ionic_lif_config config;\n \t\t} __rte_packed eth;\ndiff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c\nindex dc21387cd8..2c6f7f7f4e 100644\n--- a/drivers/net/ionic/ionic_lif.c\n+++ b/drivers/net/ionic/ionic_lif.c\n@@ -536,7 +536,7 @@ ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)\n }\n \n int\n-ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)\n+ionic_lif_change_mtu(struct ionic_lif *lif, uint32_t new_mtu)\n {\n \tstruct ionic_admin_ctx ctx = {\n \t\t.pending_work = true,\n@@ -546,13 +546,8 @@ ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)\n \t\t\t.mtu = rte_cpu_to_le_32(new_mtu),\n \t\t},\n \t};\n-\tint err;\n-\n-\terr = ionic_adminq_post_wait(lif, &ctx);\n-\tif (err)\n-\t\treturn err;\n \n-\treturn 0;\n+\treturn ionic_adminq_post_wait(lif, &ctx);\n }\n \n int\n@@ -730,6 +725,7 @@ ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index,\n \tint err;\n \n \tflags = IONIC_QCQ_F_SG;\n+\n \terr = ionic_qcq_alloc(lif,\n \t\tIONIC_QTYPE_RXQ,\n \t\tsizeof(struct ionic_rx_qcq),\ndiff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h\nindex 4aebfe20d0..c3ae96d25b 100644\n--- a/drivers/net/ionic/ionic_lif.h\n+++ b/drivers/net/ionic/ionic_lif.h\n@@ -81,6 +81,7 @@ struct ionic_rx_qcq {\n \n \t/* cacheline2 */\n \tstruct rte_mempool *mb_pool;\n+\tuint16_t frame_size;\t/* Based on configured MTU */\n \tuint16_t flags;\n \n \t/* cacheline3 (inside stats) */\n@@ -123,6 +124,7 @@ struct ionic_lif {\n \tstruct ionic_adapter *adapter;\n \tstruct rte_eth_dev *eth_dev;\n \tuint16_t port_id; /**< Device port identifier */\n+\tuint16_t frame_size;\n \tuint32_t hw_index;\n \tuint32_t state;\n \tuint32_t ntxqcqs;\n@@ -181,7 +183,7 @@ int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr);\n int ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,\n \tvoid *cb_arg);\n \n-int ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu);\n+int ionic_lif_change_mtu(struct ionic_lif *lif, uint32_t new_mtu);\n \n int ionic_dev_add_mac(struct rte_eth_dev *eth_dev,\n \tstruct rte_ether_addr *mac_addr,\ndiff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c\nindex acdfda9312..d77f06c022 100644\n--- a/drivers/net/ionic/ionic_rxtx.c\n+++ b/drivers/net/ionic/ionic_rxtx.c\n@@ -772,8 +772,6 @@ ionic_rx_clean(struct ionic_rx_qcq *rxq,\n \tstruct ionic_rxq_comp *cq_desc_base = cq->base;\n \tstruct ionic_rxq_comp *cq_desc = &cq_desc_base[cq_desc_index];\n \tstruct rte_mbuf *rxm, *rxm_seg;\n-\tuint32_t max_frame_size =\n-\t\trxq->qcq.lif->eth_dev->data->mtu + RTE_ETHER_HDR_LEN;\n \tuint64_t pkt_flags = 0;\n \tuint32_t pkt_type;\n \tstruct ionic_rx_stats *stats = &rxq->stats;\n@@ -814,8 +812,7 @@ ionic_rx_clean(struct ionic_rx_qcq *rxq,\n \t\treturn;\n \t}\n \n-\tif (cq_desc->len > max_frame_size ||\n-\t\t\tcq_desc->len == 0) {\n+\tif (cq_desc->len > rxq->frame_size || cq_desc->len == 0) {\n \t\tstats->bad_len++;\n \t\tionic_rx_recycle(q, q_desc_index, rxm);\n \t\treturn;\n@@ -936,7 +933,7 @@ ionic_rx_recycle(struct ionic_queue *q, uint32_t q_desc_index,\n }\n \n static __rte_always_inline int\n-ionic_rx_fill(struct ionic_rx_qcq *rxq, uint32_t len)\n+ionic_rx_fill(struct ionic_rx_qcq *rxq)\n {\n \tstruct ionic_queue *q = &rxq->qcq.q;\n \tstruct ionic_rxq_desc *desc, *desc_base = q->base;\n@@ -961,7 +958,7 @@ ionic_rx_fill(struct ionic_rx_qcq *rxq, uint32_t len)\n \n \t\tinfo = IONIC_INFO_PTR(q, q->head_idx);\n \n-\t\tnsegs = (len + buf_size - 1) / buf_size;\n+\t\tnsegs = (rxq->frame_size + buf_size - 1) / buf_size;\n \n \t\tdesc = &desc_base[q->head_idx];\n \t\tdma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(rxm));\n@@ -996,9 +993,9 @@ ionic_rx_fill(struct ionic_rx_qcq *rxq, uint32_t len)\n \t\t\tprev_rxm_seg = rxm_seg;\n \t\t}\n \n-\t\tif (size < len)\n+\t\tif (size < rxq->frame_size)\n \t\t\tIONIC_PRINT(ERR, \"Rx SG size is not sufficient (%d < %d)\",\n-\t\t\t\tsize, len);\n+\t\t\t\tsize, rxq->frame_size);\n \n \t\tinfo[0] = rxm;\n \n@@ -1016,7 +1013,6 @@ ionic_rx_fill(struct ionic_rx_qcq *rxq, uint32_t len)\n int __rte_cold\n ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)\n {\n-\tuint32_t frame_size = eth_dev->data->mtu + RTE_ETHER_HDR_LEN;\n \tuint8_t *rx_queue_state = eth_dev->data->rx_queue_state;\n \tstruct ionic_rx_qcq *rxq;\n \tint err;\n@@ -1029,8 +1025,10 @@ ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)\n \n \trxq = eth_dev->data->rx_queues[rx_queue_id];\n \n-\tIONIC_PRINT(DEBUG, \"Starting RX queue %u, %u descs (size: %u)\",\n-\t\trx_queue_id, rxq->qcq.q.num_descs, frame_size);\n+\trxq->frame_size = rxq->qcq.lif->frame_size - RTE_ETHER_CRC_LEN;\n+\n+\tIONIC_PRINT(DEBUG, \"Starting RX queue %u, %u descs, size %u\",\n+\t\trx_queue_id, rxq->qcq.q.num_descs, rxq->frame_size);\n \n \tif (!(rxq->flags & IONIC_QCQ_F_INITED)) {\n \t\terr = ionic_lif_rxq_init(rxq);\n@@ -1041,7 +1039,7 @@ ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)\n \t}\n \n \t/* Allocate buffers for descriptor rings */\n-\tif (ionic_rx_fill(rxq, frame_size) != 0) {\n+\tif (ionic_rx_fill(rxq) != 0) {\n \t\tIONIC_PRINT(ERR, \"Could not alloc mbuf for queue:%d\",\n \t\t\trx_queue_id);\n \t\treturn -1;\n@@ -1129,8 +1127,6 @@ ionic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\tuint16_t nb_pkts)\n {\n \tstruct ionic_rx_qcq *rxq = rx_queue;\n-\tuint32_t frame_size =\n-\t\trxq->qcq.lif->eth_dev->data->mtu + RTE_ETHER_HDR_LEN;\n \tstruct ionic_rx_service service_cb_arg;\n \n \tservice_cb_arg.rx_pkts = rx_pkts;\n@@ -1139,7 +1135,7 @@ ionic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \n \tionic_rxq_service(rxq, nb_pkts, &service_cb_arg);\n \n-\tionic_rx_fill(rxq, frame_size);\n+\tionic_rx_fill(rxq);\n \n \treturn service_cb_arg.nb_rx;\n }\n", "prefixes": [ "08/35" ] }