Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/117469/?format=api
{ "id": 117469, "url": "https://patches.dpdk.org/api/patches/117469/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221006150325.660-5-valex@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221006150325.660-5-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221006150325.660-5-valex@nvidia.com", "date": "2022-10-06T15:03:10", "name": "[v2,04/19] net/mlx5: add port to metadata conversion", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ad5b6a75a7dfd9bbc26b0751fe536f7302df944a", "submitter": { "id": 2858, "url": "https://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221006150325.660-5-valex@nvidia.com/mbox/", "series": [ { "id": 25012, "url": "https://patches.dpdk.org/api/series/25012/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25012", "date": "2022-10-06T15:03:06", "name": "net/mlx5: Add HW steering low level support", "version": 2, "mbox": "https://patches.dpdk.org/series/25012/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117469/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/117469/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3B930A00C2;\n\tThu, 6 Oct 2022 17:05:10 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5BA0B42CC0;\n\tThu, 6 Oct 2022 17:04:26 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2070.outbound.protection.outlook.com [40.107.92.70])\n by mails.dpdk.org (Postfix) with ESMTP id 65F4242CBF\n for <dev@dpdk.org>; Thu, 6 Oct 2022 17:04:24 +0200 (CEST)", "from BN0PR04CA0108.namprd04.prod.outlook.com (2603:10b6:408:ec::23)\n by MW3PR12MB4570.namprd12.prod.outlook.com (2603:10b6:303:5f::12)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.32; Thu, 6 Oct\n 2022 15:04:22 +0000", "from BN8NAM11FT052.eop-nam11.prod.protection.outlook.com\n (2603:10b6:408:ec:cafe::8e) by BN0PR04CA0108.outlook.office365.com\n (2603:10b6:408:ec::23) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.20 via Frontend\n Transport; Thu, 6 Oct 2022 15:04:21 +0000", "from mail.nvidia.com (216.228.117.160) by\n BN8NAM11FT052.mail.protection.outlook.com (10.13.177.210) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.5709.10 via Frontend Transport; Thu, 6 Oct 2022 15:04:21 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 6 Oct 2022\n 08:03:54 -0700", "from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 6 Oct 2022\n 08:03:51 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=H/O0CHPVPupW3eoDAgQAFfRXfJo7RlMbfwLmPvx3gHQCscLfZeFwLHIF3gUmYg/GXmHWg/x/kio0XMC8J8Xe06e/7KMVOrGUqEzA1rwXk3HdK2yb3a0Gx3aad8yU9YlAhNTa8/dbMOSnPai4dVP+egH3f0Iya3mLkZdJoEwe+jxsq80VJJoYsCQKZIgnSnJtBD6OXABK+CSq7mfFuJDtiWqipVrdcqfF5NCw7/nlQ+08d3bdXjzdajb0ZgMFuys3lstF8UunHzDC34X/RmUdasFO5/JC7/0KbIKksl5tJYbXLswZyNQzsmAsBi+yFpojytNGB3DmPQpHzpVTKKgXOA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=pecxAJRvKD3tRF+TdvtVnZdG2ezldrEV2qxSa/90QLw=;\n b=RNctsYw9hjVfmV17PwKf23fD2K9/oZ1T60sd6YE1cCHAxLb5fH3YIezlJxEpdnH6bMKdUiWAsmRoY/0ND68TIJ9bVoZI0gtY0PM3+KmcfvhUzN2lpiCq7e1gZJN950zUKspmSqIhKDdFWQcJv7MsF8CRMFFArMS8++BpOPRLBMt9kmfmDD1JmN2dLO1LM+p354C+NjGKSF/ix/WFjbeU0ySFNrv1gqyLLwZ0rR4d2EsDzfxsV4qgR7IyPjSDpKMajg3Pfbvxu6EFIse76xCfjlNN7GTB/6r1O6pGtnKrvnWWXbq6nY/V497vcMIm/9QwGpU7qlIghXZyiPhORZ2y8w==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=pecxAJRvKD3tRF+TdvtVnZdG2ezldrEV2qxSa/90QLw=;\n b=QToLhY5+qSX0MfyiIDtMAYa27W2zG8D4ULR7slg6dQFQyJYg010Bu1Ype95Id/O20wgWC6vJkM0ERrkUUP0+1/SIMQToGlLzO0TCCv9DHFt6j3B7q8cuhBYFr67srP4mBoF7Gfm76T8C9Tt2YnVpHSEAbKYS1AG8dc4WGI7MtJIUdj/IIWXLCNXVFm/syUOGtKHuPJxaPpesOPXmcogz26HjXAw3O402pl4M4oCeRgDWw2/EVP066wFvg7x/M1bk/aXvJJVTCfncotcnE947BUze6ify/fiR84TCcMYGbW6+Zs0uMDgt8jh8JU9CgsSJSVA4a9F5Lmnnbd1+KulPEw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, Dariusz Sosnowski\n <dsosnowski@nvidia.com>", "Subject": "[v2 04/19] net/mlx5: add port to metadata conversion", "Date": "Thu, 6 Oct 2022 18:03:10 +0300", "Message-ID": "<20221006150325.660-5-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221006150325.660-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221006150325.660-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT052:EE_|MW3PR12MB4570:EE_", "X-MS-Office365-Filtering-Correlation-Id": "484f52d6-7b68-478b-7bd6-08daa7ac0cd5", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n ksHTnncEk4PZKIQLI/LjKqFoxj1UXiLVc0/QrLCtjtI009MDA+kkYNPveiNsb4S6NnIqmrvMqSXbqbtPp9vrYRAiH9dt+oBPL52HdggoKGM7rP6oRHzztutBsDmPKdfW8jff+stqAEKxqp9DH+ST9xRzprx0iy5pzvnMAD9ZlPauI+VGpV+A6teeRnlnG51lEI5/sJt5jB9SCrnZrfDXVzIR61CJMUvD5+AD3+e/BrIP8TwdJwzSrrUY+FMhZ5yQJf4cGS4XEOIZ76vmqZ+Yzrf+g/djH4EWtsF2r9E3GOdcEFV0U3zV5P9bw0FgE6ajxfvT+PJNnMiTJ+F9YY++dFIiQrhPMbLU6EfhGmPSZkPF4UKQ7uVfDiO41S7rYUyyG5e7MoirV5JJHWsvs/r4MdWqKYB3YKy6TcqFDr6HKTnb7sgCL6GBtk/LJece2tURAwFmJo2tufAh/7u55Z5esp417fFiCWbbq+/3eXyGCCA2YsxIol7r2p3/s1WfFg6KDscn/oykv1KQbK+izrfHDcKw9AOhXhdzoEqvKsPDyz+HtzEMKXVVnMB0nXC7Ti8rob9cpJHBGbGV0J0vbpx2jupGFzUL8WbGNDhoM/tOVuMtDhn0HlHYtrmvEdZCX4Xg3s2D0sj+m/gpg7mvMkR1K9b8VV5qWqP7oioK2GeF7nTYatFIqVEFaL4/CkWapaGusGJLVm0XeovK5LhJC4UWgewQN6c8B2yiAh1yxZEdd73RZRxVJsalO5dVSsbU/GgV/7g7+8h6KjxtOMqPSNtch0G8lUgs6l0qNYBnC0Op2im7XNDxxVUX3CbCcdkHFRE4", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(396003)(136003)(376002)(39860400002)(346002)(451199015)(36840700001)(46966006)(40470700004)(2616005)(478600001)(6636002)(83380400001)(54906003)(110136005)(36756003)(6286002)(107886003)(4326008)(41300700001)(26005)(8676002)(5660300002)(70586007)(6666004)(8936002)(70206006)(40460700003)(40480700001)(55016003)(7636003)(86362001)(47076005)(426003)(336012)(2906002)(186003)(1076003)(16526019)(7696005)(316002)(82740400003)(36860700001)(82310400005)(356005)(21314003)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2022 15:04:21.5846 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 484f52d6-7b68-478b-7bd6-08daa7ac0cd5", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT052.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW3PR12MB4570", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Dariusz Sosnowski <dsosnowski@nvidia.com>\n\nThis patch initial version of functions used to:\n\n- convert between ethdev port_id and internal tag/mask value,\n- convert between IB context and internal tag/mask value.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 2 ++\n drivers/net/mlx5/mlx5.c | 1 +\n drivers/net/mlx5/mlx5_flow.c | 6 ++++\n drivers/net/mlx5/mlx5_flow.h | 50 ++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow_hw.c | 29 ++++++++++++++++++\n 5 files changed, 88 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 60677eb8d7..1036b870de 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1541,6 +1541,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tif (!priv->hrxqs)\n \t\tgoto error;\n \trte_rwlock_init(&priv->ind_tbls_lock);\n+\tif (priv->vport_meta_mask)\n+\t\tflow_hw_set_port_info(eth_dev);\n \tif (priv->sh->config.dv_flow_en == 2)\n \t\treturn eth_dev;\n \t/* Port representor shares the same max priority with pf port. */\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 752b60d769..ad561bd86d 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1945,6 +1945,7 @@ mlx5_dev_close(struct rte_eth_dev *dev)\n #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \tflow_hw_resource_release(dev);\n #endif\n+\tflow_hw_clear_port_info(dev);\n \tif (priv->rxq_privs != NULL) {\n \t\t/* XXX race condition if mlx5_rx_burst() is still running. */\n \t\trte_delay_us_sleep(1000);\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex e4744b0a67..acf1467bf6 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -33,6 +33,12 @@\n #include \"mlx5_common_os.h\"\n #include \"rte_pmd_mlx5.h\"\n \n+/*\n+ * Shared array for quick translation between port_id and vport mask/values\n+ * used for HWS rules.\n+ */\n+struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS];\n+\n struct tunnel_default_miss_ctx {\n \tuint16_t *queue;\n \t__extension__\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 86a08074dc..2eb2b46060 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1320,6 +1320,56 @@ struct mlx5_flow_split_info {\n \tuint64_t prefix_layers; /**< Prefix subflow layers. */\n };\n \n+struct flow_hw_port_info {\n+\tuint32_t regc_mask;\n+\tuint32_t regc_value;\n+\tuint32_t is_wire:1;\n+};\n+\n+extern struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS];\n+\n+/*\n+ * Get metadata match tag and mask for given rte_eth_dev port.\n+ * Used in HWS rule creation.\n+ */\n+static __rte_always_inline const struct flow_hw_port_info *\n+flow_hw_conv_port_id(const uint16_t port_id)\n+{\n+\tstruct flow_hw_port_info *port_info;\n+\n+\tif (port_id >= RTE_MAX_ETHPORTS)\n+\t\treturn NULL;\n+\tport_info = &mlx5_flow_hw_port_infos[port_id];\n+\treturn !!port_info->regc_mask ? port_info : NULL;\n+}\n+\n+/*\n+ * Get metadata match tag and mask for the uplink port represented\n+ * by given IB context. Used in HWS context creation.\n+ */\n+static __rte_always_inline const struct flow_hw_port_info *\n+flow_hw_get_wire_port(struct ibv_context *ibctx)\n+{\n+\tstruct ibv_device *ibdev = ibctx->device;\n+\tuint16_t port_id;\n+\n+\tMLX5_ETH_FOREACH_DEV(port_id, NULL) {\n+\t\tconst struct mlx5_priv *priv =\n+\t\t\t\trte_eth_devices[port_id].data->dev_private;\n+\n+\t\tif (priv && priv->master) {\n+\t\t\tstruct ibv_context *port_ibctx = priv->sh->cdev->ctx;\n+\n+\t\t\tif (port_ibctx->device == ibdev)\n+\t\t\t\treturn flow_hw_conv_port_id(port_id);\n+\t\t}\n+\t}\n+\treturn NULL;\n+}\n+\n+void flow_hw_set_port_info(struct rte_eth_dev *dev);\n+void flow_hw_clear_port_info(struct rte_eth_dev *dev);\n+\n typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,\n \t\t\t\t const struct rte_flow_attr *attr,\n \t\t\t\t const struct rte_flow_item items[],\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 12498794a5..fe809a83b9 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -2208,6 +2208,35 @@ flow_hw_resource_release(struct rte_eth_dev *dev)\n \tpriv->nb_queue = 0;\n }\n \n+/* Sets vport tag and mask, for given port, used in HWS rules. */\n+void\n+flow_hw_set_port_info(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tuint16_t port_id = dev->data->port_id;\n+\tstruct flow_hw_port_info *info;\n+\n+\tMLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);\n+\tinfo = &mlx5_flow_hw_port_infos[port_id];\n+\tinfo->regc_mask = priv->vport_meta_mask;\n+\tinfo->regc_value = priv->vport_meta_tag;\n+\tinfo->is_wire = priv->master;\n+}\n+\n+/* Clears vport tag and mask used for HWS rules. */\n+void\n+flow_hw_clear_port_info(struct rte_eth_dev *dev)\n+{\n+\tuint16_t port_id = dev->data->port_id;\n+\tstruct flow_hw_port_info *info;\n+\n+\tMLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);\n+\tinfo = &mlx5_flow_hw_port_infos[port_id];\n+\tinfo->regc_mask = 0;\n+\tinfo->regc_value = 0;\n+\tinfo->is_wire = 0;\n+}\n+\n /**\n * Create shared action.\n *\n", "prefixes": [ "v2", "04/19" ] }