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GET /api/patches/117465/?format=api
{ "id": 117465, "url": "https://patches.dpdk.org/api/patches/117465/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221006150325.660-6-valex@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221006150325.660-6-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221006150325.660-6-valex@nvidia.com", "date": "2022-10-06T15:03:11", "name": "[v2,05/19] common/mlx5: query set capability of registers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "57055007ba8c3792e97e4c560f11c366a0f88c79", "submitter": { "id": 2858, "url": "https://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221006150325.660-6-valex@nvidia.com/mbox/", "series": [ { "id": 25012, "url": "https://patches.dpdk.org/api/series/25012/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25012", "date": "2022-10-06T15:03:06", "name": "net/mlx5: Add HW steering low level support", "version": 2, "mbox": "https://patches.dpdk.org/series/25012/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117465/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/117465/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DF88FA00C2;\n\tThu, 6 Oct 2022 17:04:26 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BFDC242CA2;\n\tThu, 6 Oct 2022 17:04:12 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2041.outbound.protection.outlook.com [40.107.92.41])\n by mails.dpdk.org (Postfix) with ESMTP id 90AED42C9D\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, Bing Zhao <bingz@nvidia.com>", "Subject": "[v2 05/19] common/mlx5: query set capability of registers", "Date": "Thu, 6 Oct 2022 18:03:11 +0300", "Message-ID": "<20221006150325.660-6-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221006150325.660-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221006150325.660-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT013:EE_|MN0PR12MB5956:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d4665a12-6f98-465f-5ce2-08daa7ac0549", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n vn7e0bvN4kVvhDgqey/yJ2QSijYfHnujK+xQCBeb1uDllGgjzrLkWIwUDQe3AOiD3Iv0yZNmMFNKUntFEC8qVxanT0nLoHcNMagrb7nW2+ikbkR8ocpLRTFnqvGwmyHULMN9lZmsm8z6InnVrDPYXwRu/5kOZM96F61zYNNijX2TZIj0QAXHSVSjPWDf/1euvruVvH3PQHOWxOIOf9/Qldb9tRgQIq6yVJg+gxBSUAa69JSkkV+3/Ae1VXDqs6MMpeNZirxVjS3C828DS4fh9RWw1eJfT2IZXtnUwhMoiuVjcB+OkjmUyItgt3um0dLN18zMPWc/c+1j6UpSh+BYPlSAJurHwfbVTusjGa1OaziSyyJsD99dSDmtU0E4Aaaa+h6SjQN6YCNvCfixYmv0fsmMHPBxPa46uXoUla31h6PIsw90dmzaCgvy1ci89M8ItjU/sfIAKYlYFLxfOGSaLF+M6D+tbR9tQu8h5F6Z/ceklypS5i6BgLLvkt6udf2OyEZrtYrAJirVOfIQWNcButod3QpiUA2kxK7RxLKw4ZwVPnBrnW0k/TJn2Dc272ANbBYDuY7jDGcGglyXZZSjiJqEU/uRT6/gYTyvBeZCX0WfGl7S1B4BPLIdPDTy3aymvi0zOUgPlaMxGhbK+dZ/uBN4uAMVdqLAuhJPQ5g+na8aZvnmLauSG+y6PbLcHCCr4y58FkslWTnvcj/p+hjxLXEvGAdhWs11XP5rLJws2CB72CbcXRHwniN37JACLK6NL7eSo83LaHxFOpf3IWgPYQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(376002)(136003)(396003)(346002)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(426003)(47076005)(36860700001)(36756003)(83380400001)(70586007)(336012)(2616005)(1076003)(186003)(82310400005)(16526019)(7636003)(26005)(86362001)(7696005)(356005)(6666004)(107886003)(478600001)(5660300002)(2906002)(82740400003)(6286002)(8676002)(8936002)(55016003)(41300700001)(6636002)(40460700003)(316002)(54906003)(110136005)(4326008)(70206006)(40480700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2022 15:04:08.8910 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d4665a12-6f98-465f-5ce2-08daa7ac0549", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT013.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN0PR12MB5956", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Bing Zhao <bingz@nvidia.com>\n\nIn the flow table capabilities, new fields are added to query the\ncapability to set, add, copy to a REG_C_x.\n\nThe set capability are queried and saved for the future usage.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 30 +++++++++++++++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++\n drivers/common/mlx5/mlx5_prm.h | 44 +++++++++++++++++++++++++---\n 3 files changed, 72 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex fb33023138..ac6891145d 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -1058,6 +1058,24 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->modify_outer_ip_ecn = MLX5_GET\n \t\t(flow_table_nic_cap, hcattr,\n \t\t ft_header_modify_nic_receive.outer_ip_ecn);\n+\tattr->set_reg_c = 0xff;\n+\tif (attr->nic_flow_table) {\n+#define GET_RX_REG_X_BITS \\\n+\t\tMLX5_GET(flow_table_nic_cap, hcattr, \\\n+\t\t\t ft_header_modify_nic_receive.metadata_reg_c_x)\n+#define GET_TX_REG_X_BITS \\\n+\t\tMLX5_GET(flow_table_nic_cap, hcattr, \\\n+\t\t\t ft_header_modify_nic_transmit.metadata_reg_c_x)\n+\n+\t\tuint32_t tx_reg, rx_reg;\n+\n+\t\ttx_reg = GET_TX_REG_X_BITS;\n+\t\trx_reg = GET_RX_REG_X_BITS;\n+\t\tattr->set_reg_c &= (rx_reg & tx_reg);\n+\n+#undef GET_RX_REG_X_BITS\n+#undef GET_TX_REG_X_BITS\n+\t}\n \tattr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);\n \tattr->inner_ipv4_ihl = MLX5_GET\n \t\t(flow_table_nic_cap, hcattr,\n@@ -1157,6 +1175,18 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\tattr->esw_mgr_vport_id =\n \t\t\tMLX5_GET(esw_cap, hcattr, esw_manager_vport_number);\n \t}\n+\tif (attr->eswitch_manager) {\n+\t\tuint32_t esw_reg;\n+\n+\t\thcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,\n+\t\t\t\tMLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE |\n+\t\t\t\tMLX5_HCA_CAP_OPMOD_GET_CUR);\n+\t\tif (!hcattr)\n+\t\t\treturn rc;\n+\t\tesw_reg = MLX5_GET(flow_table_esw_cap, hcattr,\n+\t\t\t\t ft_header_modify_esw_fdb.metadata_reg_c_x);\n+\t\tattr->set_reg_c &= esw_reg;\n+\t}\n \treturn 0;\n error:\n \trc = (rc > 0) ? -rc : rc;\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex af6053a788..d69dad613e 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -260,6 +260,8 @@ struct mlx5_hca_attr {\n \tuint32_t crypto_wrapped_import_method:1;\n \tuint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */\n \tuint16_t max_wqe_sz_sq;\n+\tuint32_t set_reg_c:8;\n+\tuint32_t nic_flow_table:1;\n \tuint32_t modify_outer_ip_ecn:1;\n };\n \ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 4346279c81..12eb7b3b7f 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1892,6 +1892,7 @@ struct mlx5_ifc_roce_caps_bits {\n };\n \n struct mlx5_ifc_ft_fields_support_bits {\n+\t/* set_action_field_support */\n \tu8 outer_dmac[0x1];\n \tu8 outer_smac[0x1];\n \tu8 outer_ether_type[0x1];\n@@ -1919,7 +1920,7 @@ struct mlx5_ifc_ft_fields_support_bits {\n \tu8 outer_gre_key[0x1];\n \tu8 outer_vxlan_vni[0x1];\n \tu8 reserved_at_1a[0x5];\n-\tu8 source_eswitch_port[0x1];\n+\tu8 source_eswitch_port[0x1]; /* end of DW0 */\n \tu8 inner_dmac[0x1];\n \tu8 inner_smac[0x1];\n \tu8 inner_ether_type[0x1];\n@@ -1943,8 +1944,33 @@ struct mlx5_ifc_ft_fields_support_bits {\n \tu8 inner_tcp_sport[0x1];\n \tu8 inner_tcp_dport[0x1];\n \tu8 inner_tcp_flags[0x1];\n-\tu8 reserved_at_37[0x9];\n-\tu8 reserved_at_40[0x40];\n+\tu8 reserved_at_37[0x9]; /* end of DW1 */\n+\tu8 reserved_at_40[0x20]; /* end of DW2 */\n+\tu8 reserved_at_60[0x18];\n+\tunion {\n+\t\tstruct {\n+\t\t\tu8 metadata_reg_c_7[0x1];\n+\t\t\tu8 metadata_reg_c_6[0x1];\n+\t\t\tu8 metadata_reg_c_5[0x1];\n+\t\t\tu8 metadata_reg_c_4[0x1];\n+\t\t\tu8 metadata_reg_c_3[0x1];\n+\t\t\tu8 metadata_reg_c_2[0x1];\n+\t\t\tu8 metadata_reg_c_1[0x1];\n+\t\t\tu8 metadata_reg_c_0[0x1];\n+\t\t};\n+\t\tu8 metadata_reg_c_x[0x8];\n+\t}; /* end of DW3 */\n+\t/* set_action_field_support_2 */\n+\tu8 reserved_at_80[0x80];\n+\t/* add_action_field_support */\n+\tu8 reserved_at_100[0x80];\n+\t/* add_action_field_support_2 */\n+\tu8 reserved_at_180[0x80];\n+\t/* copy_action_field_support */\n+\tu8 reserved_at_200[0x80];\n+\t/* copy_action_field_support_2 */\n+\tu8 reserved_at_280[0x80];\n+\tu8 reserved_at_300[0x100];\n };\n \n /*\n@@ -1989,9 +2015,18 @@ struct mlx5_ifc_flow_table_nic_cap_bits {\n \tu8 reserved_at_e00[0x200];\n \tstruct mlx5_ifc_ft_fields_support_bits\n \t\tft_header_modify_nic_receive;\n-\tu8 reserved_at_1080[0x380];\n \tstruct mlx5_ifc_ft_fields_support_2_bits\n \t\tft_field_support_2_nic_receive;\n+\tu8 reserved_at_1480[0x780];\n+\tstruct mlx5_ifc_ft_fields_support_bits\n+\t\tft_header_modify_nic_transmit;\n+\tu8 reserved_at_2000[0x6000];\n+};\n+\n+struct mlx5_ifc_flow_table_esw_cap_bits {\n+\tu8 reserved_at_0[0x800];\n+\tstruct mlx5_ifc_ft_fields_support_bits ft_header_modify_esw_fdb;\n+\tu8 reserved_at_C00[0x7400];\n };\n \n /*\n@@ -2041,6 +2076,7 @@ union mlx5_ifc_hca_cap_union_bits {\n \tstruct mlx5_ifc_qos_cap_bits qos_cap;\n \tstruct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;\n \tstruct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;\n+\tstruct mlx5_ifc_flow_table_esw_cap_bits flow_table_esw_cap;\n \tstruct mlx5_ifc_esw_cap_bits esw_cap;\n \tstruct mlx5_ifc_roce_caps_bits roce_caps;\n \tu8 reserved_at_0[0x8000];\n", "prefixes": [ "v2", "05/19" ] }