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GET /api/patches/117455/?format=api
{ "id": 117455, "url": "https://patches.dpdk.org/api/patches/117455/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221006110105.2986966-8-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221006110105.2986966-8-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221006110105.2986966-8-dsosnowski@nvidia.com", "date": "2022-10-06T11:01:04", "name": "[v2,7/8] app/testpmd: add hairpin queues memory modes", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "af0f2c84e1269cd8bc8526bcfc3eadeb086e029f", "submitter": { "id": 2386, "url": "https://patches.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221006110105.2986966-8-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 25009, "url": "https://patches.dpdk.org/api/series/25009/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25009", "date": "2022-10-06T11:00:57", "name": "ethdev: introduce hairpin memory capabilities", "version": 2, "mbox": "https://patches.dpdk.org/series/25009/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117455/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/117455/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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b=Aq+rvI9wxCz2WNTne7E6JGwnfG6BZEzmYNbwrvv+HNrynrcslK49aKJujObEnXNVW6sGt1OadrMSbi8G+MJlOkQ8vfQN2QoHtwOzIoHamdPdSVCXQubRV5BC81yLPijMtBFzA25C6JNyNCp30399CjeCO3u6iM6hN9RV7bzZd6xb0inxqzhqHEtirAK6i23XTnmW0pjebjYKWJAdeq1z3SppUHc4+CRQkLGnXFb8AHaS88iNXuSO2oCgNb31OOOW7wsiqDamgikPbOgCIHi3c5WDLjhhtahsioL8eu2Zecs7zNXcsd7QKa7zxKWPwxC5VECb8fiZ4DrDK3zuDbZ80g==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Aman Singh <aman.deep.singh@intel.com>, Yuying Zhang\n <yuying.zhang@intel.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v2 7/8] app/testpmd: add hairpin queues memory modes", "Date": "Thu, 6 Oct 2022 11:01:04 +0000", "Message-ID": "<20221006110105.2986966-8-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "References": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT079:EE_|LV2PR12MB5967:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a7847205-e7d8-47b2-8296-08daa78a3f4e", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 63XGb6otXnSsOkGkzEdTnUNwJAp2g1VDw4hltHQJ9odwE7GVAkoiwrlQl90TNri3uw/abd5mrLwxaRePOhm3111zV9U6fxm9e/1CDC+QYlV8TTgopk4iBq7M7yBLvucJK7py9ILC6L0uQJoXLyocg4agieYDMqEOTPNd39ZlOD4Rkns0ey8Cnfo0aiHLpdbEluYCKl+65i2dAObG9nRDcUzmgDEhGzA2QuXynzuGIg1JxZc0U/YuHFtgIdt7ESL3auOM+YmCDpdbtLGaJM4ef+ah/MqsyshsYLYNUXiCCiRwucbwqqoMCyUrpeewxyOJMp6twSRkNNNbdJMnn/alrvu0Nb4+vUwoZxK9fucs4/blBItFoT+iOIrLbaCIBRm3iZFS8FSyD6yQJDC6l98kLC1yAEIRzWmqISapbf08Eyg5Pcp8jMk4nm1I3QOnrc8Yypmi3LtsLTNEyEH8paayXneqY5JAM5g7+o2/9vtWqlAa5gwy8jtAUAmBayQTNeecYg/aeQ6WHQDaeE3TXuOqChdxZXvoTltD0mBnIPEYxfWjKNJhX4odE0vMSSnqNcH40ibapYZB3KcvDDYO6c6TOOjCCka10eELe5r5X2dY+dqeEt3KcCS+l5K74QsZpE1F69ArwmjsZoMON1s0LlapeFI3USVK0OH7KJ3v2E1qzYCf7LqkEhXqfRkEq8CkYDwz+5qk7D3G5LKcfCkRJk7J/8fSY3iPWTJ7Kf26dF7QThc1zTjOqBgdsMm6mKDbfeFsO3PpmPL2QTjq639D6dAZDhpQnsseBqI4fqVo/T45904=", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(346002)(396003)(376002)(136003)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(2906002)(8936002)(70206006)(316002)(36756003)(8676002)(478600001)(41300700001)(86362001)(70586007)(4326008)(5660300002)(110136005)(36860700001)(55016003)(16526019)(83380400001)(356005)(26005)(2616005)(1076003)(47076005)(6286002)(40460700003)(186003)(336012)(7636003)(82740400003)(7696005)(40480700001)(426003)(82310400005)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2022 11:02:23.3750 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a7847205-e7d8-47b2-8296-08daa78a3f4e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT079.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV2PR12MB5967", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch extends hairpin-mode command line option of test-pmd\napplication with an ability to configure whether Rx/Tx hairpin queue\nshould use locked device memory or RTE memory.\n\nFor purposes of this configurations the following bits of 32 bit\nhairpin-mode are reserved:\n\n- Bit 8 - If set, then force_memory flag will be set for hairpin RX\n queue.\n- Bit 9 - If set, then force_memory flag will be set for hairpin TX\n queue.\n- Bits 12-15 - Memory options for hairpin Rx queue:\n - Bit 12 - If set, then use_locked_device_memory will be set.\n - Bit 13 - If set, then use_rte_memory will be set.\n - Bit 14 - Reserved for future use.\n - Bit 15 - Reserved for future use.\n- Bits 16-19 - Memory options for hairpin Tx queue:\n - Bit 16 - If set, then use_locked_device_memory will be set.\n - Bit 17 - If set, then use_rte_memory will be set.\n - Bit 18 - Reserved for future use.\n - Bit 19 - Reserved for future use.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n app/test-pmd/parameters.c | 2 +-\n app/test-pmd/testpmd.c | 24 +++++++++++++++++++++++-\n app/test-pmd/testpmd.h | 2 +-\n doc/guides/testpmd_app_ug/run_app.rst | 10 ++++++++--\n 4 files changed, 33 insertions(+), 5 deletions(-)", "diff": "diff --git a/app/test-pmd/parameters.c b/app/test-pmd/parameters.c\nindex 1024b5419c..14752f9571 100644\n--- a/app/test-pmd/parameters.c\n+++ b/app/test-pmd/parameters.c\n@@ -1085,7 +1085,7 @@ launch_args_parse(int argc, char** argv)\n \t\t\t\tif (errno != 0 || end == optarg)\n \t\t\t\t\trte_exit(EXIT_FAILURE, \"hairpin mode invalid\\n\");\n \t\t\t\telse\n-\t\t\t\t\thairpin_mode = (uint16_t)n;\n+\t\t\t\t\thairpin_mode = (uint32_t)n;\n \t\t\t}\n \t\t\tif (!strcmp(lgopts[opt_idx].name, \"burst\")) {\n \t\t\t\tn = atoi(optarg);\ndiff --git a/app/test-pmd/testpmd.c b/app/test-pmd/testpmd.c\nindex 39ee3d331d..bb1c901742 100644\n--- a/app/test-pmd/testpmd.c\n+++ b/app/test-pmd/testpmd.c\n@@ -409,7 +409,7 @@ bool setup_on_probe_event = true;\n uint8_t clear_ptypes = true;\n \n /* Hairpin ports configuration mode. */\n-uint16_t hairpin_mode;\n+uint32_t hairpin_mode;\n \n /* Pretty printing of ethdev events */\n static const char * const eth_event_desc[] = {\n@@ -2519,6 +2519,16 @@ port_is_started(portid_t port_id)\n \treturn 1;\n }\n \n+#define HAIRPIN_MODE_RX_FORCE_MEMORY RTE_BIT32(8)\n+#define HAIRPIN_MODE_TX_FORCE_MEMORY RTE_BIT32(9)\n+\n+#define HAIRPIN_MODE_RX_LOCKED_MEMORY RTE_BIT32(12)\n+#define HAIRPIN_MODE_RX_RTE_MEMORY RTE_BIT32(13)\n+\n+#define HAIRPIN_MODE_TX_LOCKED_MEMORY RTE_BIT32(16)\n+#define HAIRPIN_MODE_TX_RTE_MEMORY RTE_BIT32(17)\n+\n+\n /* Configure the Rx and Tx hairpin queues for the selected port. */\n static int\n setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi)\n@@ -2534,6 +2544,12 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi)\n \tuint16_t peer_tx_port = pi;\n \tuint32_t manual = 1;\n \tuint32_t tx_exp = hairpin_mode & 0x10;\n+\tuint32_t rx_force_memory = hairpin_mode & HAIRPIN_MODE_RX_FORCE_MEMORY;\n+\tuint32_t rx_locked_memory = hairpin_mode & HAIRPIN_MODE_RX_LOCKED_MEMORY;\n+\tuint32_t rx_rte_memory = hairpin_mode & HAIRPIN_MODE_RX_RTE_MEMORY;\n+\tuint32_t tx_force_memory = hairpin_mode & HAIRPIN_MODE_TX_FORCE_MEMORY;\n+\tuint32_t tx_locked_memory = hairpin_mode & HAIRPIN_MODE_TX_LOCKED_MEMORY;\n+\tuint32_t tx_rte_memory = hairpin_mode & HAIRPIN_MODE_TX_RTE_MEMORY;\n \n \tif (!(hairpin_mode & 0xf)) {\n \t\tpeer_rx_port = pi;\n@@ -2573,6 +2589,9 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi)\n \t\thairpin_conf.peers[0].queue = i + nb_rxq;\n \t\thairpin_conf.manual_bind = !!manual;\n \t\thairpin_conf.tx_explicit = !!tx_exp;\n+\t\thairpin_conf.force_memory = !!tx_force_memory;\n+\t\thairpin_conf.use_locked_device_memory = !!tx_locked_memory;\n+\t\thairpin_conf.use_rte_memory = !!tx_rte_memory;\n \t\tdiag = rte_eth_tx_hairpin_queue_setup\n \t\t\t(pi, qi, nb_txd, &hairpin_conf);\n \t\ti++;\n@@ -2596,6 +2615,9 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi)\n \t\thairpin_conf.peers[0].queue = i + nb_txq;\n \t\thairpin_conf.manual_bind = !!manual;\n \t\thairpin_conf.tx_explicit = !!tx_exp;\n+\t\thairpin_conf.force_memory = !!rx_force_memory;\n+\t\thairpin_conf.use_locked_device_memory = !!rx_locked_memory;\n+\t\thairpin_conf.use_rte_memory = !!rx_rte_memory;\n \t\tdiag = rte_eth_rx_hairpin_queue_setup\n \t\t\t(pi, qi, nb_rxd, &hairpin_conf);\n \t\ti++;\ndiff --git a/app/test-pmd/testpmd.h b/app/test-pmd/testpmd.h\nindex 627a42ce3b..2244c25e97 100644\n--- a/app/test-pmd/testpmd.h\n+++ b/app/test-pmd/testpmd.h\n@@ -562,7 +562,7 @@ extern uint16_t stats_period;\n extern struct rte_eth_xstat_name *xstats_display;\n extern unsigned int xstats_display_num;\n \n-extern uint16_t hairpin_mode;\n+extern uint32_t hairpin_mode;\n \n #ifdef RTE_LIB_LATENCYSTATS\n extern uint8_t latencystats_enabled;\ndiff --git a/doc/guides/testpmd_app_ug/run_app.rst b/doc/guides/testpmd_app_ug/run_app.rst\nindex 8b41b960c8..abc3ec10a0 100644\n--- a/doc/guides/testpmd_app_ug/run_app.rst\n+++ b/doc/guides/testpmd_app_ug/run_app.rst\n@@ -529,10 +529,16 @@ The command line options are:\n \n Enable display of RX and TX burst stats.\n \n-* ``--hairpin-mode=0xXX``\n+* ``--hairpin-mode=0xXXXX``\n \n- Set the hairpin port mode with bitmask, only valid when hairpin queues number is set::\n+ Set the hairpin port configuration with bitmask, only valid when hairpin queues number is set::\n \n+\tbit 18 - hairpin TX queues will use RTE memory\n+\tbit 16 - hairpin TX queues will use locked device memory\n+\tbit 13 - hairpin RX queues will use RTE memory\n+\tbit 12 - hairpin RX queues will use locked device memory\n+\tbit 9 - force memory settings of hairpin TX queue\n+\tbit 8 - force memory settings of hairpin RX queue\n \tbit 4 - explicit Tx flow rule\n \tbit 1 - two hairpin ports paired\n \tbit 0 - two hairpin ports loop\n", "prefixes": [ "v2", "7/8" ] }