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GET /api/patches/117454/?format=api
{ "id": 117454, "url": "https://patches.dpdk.org/api/patches/117454/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221006110105.2986966-7-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221006110105.2986966-7-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221006110105.2986966-7-dsosnowski@nvidia.com", "date": "2022-10-06T11:01:03", "name": "[v2,6/8] doc: add notes for hairpin to mlx5 documentation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a72410dfffe64ba5bac8ba999fc8326fd03d422e", "submitter": { "id": 2386, "url": "https://patches.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221006110105.2986966-7-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 25009, "url": "https://patches.dpdk.org/api/series/25009/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25009", "date": "2022-10-06T11:00:57", "name": "ethdev: introduce hairpin memory capabilities", "version": 2, "mbox": "https://patches.dpdk.org/series/25009/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117454/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/117454/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 064CFA00C2;\n\tThu, 6 Oct 2022 13:02:47 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1DB4242C1B;\n\tThu, 6 Oct 2022 13:02:22 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2054.outbound.protection.outlook.com [40.107.244.54])\n by mails.dpdk.org (Postfix) with ESMTP id 1AD5442C17\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v2 6/8] doc: add notes for hairpin to mlx5 documentation", "Date": "Thu, 6 Oct 2022 11:01:03 +0000", "Message-ID": "<20221006110105.2986966-7-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "References": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT020:EE_|SN7PR12MB6689:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a924439b-a36e-455b-a0d1-08daa78a3c10", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n /+LUd9RefP+E5jOmjHgXVHwbhyFuWV1+PeqVdxFyQse9kYh1qcj7vQrOypYU6SMbAwELnQ11AxOnR2dUjezz9MEicy9yvGYwJZVbXLoeBzernq+2o/3y7wyFR7ZhGdx0fmPb6O8bYRY+YStRnzQZpYomm4zeipDZf6u1/UDetWBKAgoahqh3q3DnNRg4B4IrwsuKGfflVPkc7LkT4MVklLUlNq9fxWu7ZVuvsepuNw1c+r3VltuWFQPAnb7rX8FoXiw/oa/UrhkmX46nGl82KrgEXC9ueUdLvRi9yN/vEtcmQhQuVG9QUuHqT4A1Ymjasx8EdtTyQahHY5vBLee2BtERGOCoooo3TrnRKVOWUkDkw7UwHAo4e5ISmwjzO8TvcmMypOijtgDxbD4dsqizNPOpKK1aZC2yM0iXSHLvTzbqHi7VRLXJA/GnOPOVswGk/e1Q8jUDaKdPap6CXKxfA+4NizVzfa7jlfVY3+xJHj4Yc2TXcIUgfiB5A9ViAPpc38pi70EzYa4zav2PLNbzB0QxZ0m8Q+K344WkDIeQQWV16ka5lWjV4anRo2xILdpfpp6NAYKzEKhE8CBPq1OnnZ0fi4rXdFYl39WTgyPyxlzlZLSKmi8kpiN/he27VVxF2+/ny1qvLM4xAKtwAE4kZTcTuBs2431Ts7uVIYQiR/lai2UiDhkk0KjOC4CJGDxkqUSfVsbrDdjULCuBH7EzXz9/ADOEQ7O58N4ES8cljv/N2wr0cgLakZKlUWEgtk3oh5j1sHI4NLsgBib0QN3j5A==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(346002)(136003)(39860400002)(376002)(396003)(451199015)(36840700001)(46966006)(40470700004)(16526019)(186003)(40460700003)(2616005)(86362001)(1076003)(7636003)(6636002)(7696005)(110136005)(5660300002)(41300700001)(316002)(356005)(6286002)(478600001)(36756003)(70206006)(4326008)(70586007)(26005)(8676002)(82310400005)(55016003)(40480700001)(36860700001)(8936002)(47076005)(82740400003)(426003)(83380400001)(336012)(2906002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2022 11:02:17.9363 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a924439b-a36e-455b-a0d1-08daa78a3c10", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT020.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR12MB6689", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch extends mlx5 PMD documentation with more information\nregarding hairpin support.\n\nThe following is added to mlx5 PMD documentation:\n\n- description of the default behavior of hairpin queues,\n- description of use_locked_device_memory effect on hairpin queue\n configuration,\n- description of use_rte_memory effect on hairpin queue configuration,\n- DPDK and OFED requirements for new memory options for hairpin.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 37 +++++++++++++++++++++++++++++++++++++\n 1 file changed, 37 insertions(+)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 3d4ee31f8d..997cb19ba2 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -1517,6 +1517,43 @@ behavior as librte_net_mlx4::\n > port config all rss all\n > port start all\n \n+Notes for hairpin\n+-----------------\n+\n+NVIDIA Connect-X and BlueField devices support specifying memory\n+placement for hairpin Rx and Tx queues. This feature requires OFED 5.8.\n+\n+By default, data buffers and packet descriptors for hairpin queues are placed\n+in device memory which is shared with other resources (e.g. flow rules).\n+\n+Starting with DPDK 22.11 and OFED 5.8 applications are allowed to:\n+\n+#. Place data buffers and Rx packet descriptors in dedicated device memory.\n+ Application can request that configuration through ``use_locked_device_memory``\n+ configuration option.\n+\n+ Placing data buffers and Rx packet descriptors in dedicated device memory\n+ can decrease latency on hairpinned traffic, since traffic processing\n+ for the hairpin queue will not be memory starved.\n+\n+ However, reserving device memory for hairpin Rx queues may decrease throughput\n+ under heavy load, since less resources will be available on device.\n+\n+ This option is supported only for Rx hairpin queues.\n+\n+#. Place Tx packet descriptors in host memory.\n+ Application can request that configuration through ``use_rte_memory``\n+ configuration option.\n+\n+ Placing Tx packet descritors in host memory can increase traffic throughput.\n+ This results in more resources available on the device for other purposes,\n+ which reduces memory contention on device.\n+ Side effect of this option is visible increase in latency, since each packet\n+ incurs additional PCI transactions.\n+\n+ This option is supported only for Tx hairpin queues.\n+\n+\n Usage example\n -------------\n \n", "prefixes": [ "v2", "6/8" ] }