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GET /api/patches/117451/?format=api
{ "id": 117451, "url": "https://patches.dpdk.org/api/patches/117451/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221006110105.2986966-4-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221006110105.2986966-4-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221006110105.2986966-4-dsosnowski@nvidia.com", "date": "2022-10-06T11:01:00", "name": "[v2,3/8] common/mlx5: add hairpin RQ buffer type capabilities", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "163657b1e4624d8a46cb72c6cf627afb9569261c", "submitter": { "id": 2386, "url": "https://patches.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221006110105.2986966-4-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 25009, "url": "https://patches.dpdk.org/api/series/25009/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25009", "date": "2022-10-06T11:00:57", "name": "ethdev: introduce hairpin memory capabilities", "version": 2, "mbox": "https://patches.dpdk.org/series/25009/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117451/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/117451/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 718DCA00C2;\n\tThu, 6 Oct 2022 13:02:24 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7396F42C11;\n\tThu, 6 Oct 2022 13:02:11 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2061.outbound.protection.outlook.com [40.107.223.61])\n by mails.dpdk.org (Postfix) with ESMTP id 4682E42C11\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v2 3/8] common/mlx5: add hairpin RQ buffer type capabilities", "Date": "Thu, 6 Oct 2022 11:01:00 +0000", "Message-ID": "<20221006110105.2986966-4-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "References": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT024:EE_|BL3PR12MB6473:EE_", "X-MS-Office365-Filtering-Correlation-Id": "e1270f39-6215-4938-9160-08daa78a3619", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n PTwRUHVQMz+qv7ILmNuYbkrb3hOvCFNdl3zu9UquqsKRwCmyRFgfswCQh7iGbaBnQnAJJqDgNmQLAkJVPljVosI6r4TZd2G+c5INnfcRMFT8HTn+xaAE2c76qzm1f7tj9wMKEnCQ4Hu1sADA6ORQZERQOHSNNsv+SsGSuiT0ER2jI8udccQ6X0p11p+HK4TzBTH3NknqFfA6UEeLfpmmjBGIu3n28+KQ6MDvPKs6FBOxgp1HkZHP0bLJ0UuexcNdi1nj+TD+nX/ZS5c/STBukJXUsx86h/anqctfRT2lmJcYpU5EemKbxYCM37h69DiZJ3ro2XWy5wQQAqaWaa1UgnWW7ft5qYVifhB2xKiFeLQJ58qcx7PHW6v1gC8M3iJDWCGzJEviCi8uII37/aiNbv1rF/vFR3zj+j1kGFtKnKEOkExvmjJzUOl23iRVb6XcFnhQYmxDrqFlS4B+K9rU7ZJ95QEAJjyB/1kC7tHcDXPVXfDKbjs2a3Fe5m9r1EhvnwUGgkgsoz/GynIXN9RXU7davjjA/nZRgAZ9w0o3U5ouaTLmWHufW6w5+qytADf/K/b6cZlcfypJcL0miaYY+/Xm3fs+Ra64LfUWiTg6KC/9z1+8OCuAEQu3C3QioCWV4fzMK0k/p0iMqf7ZhLMeybYCj/PTnRx+TDQ4wzutrE+zfTrJSknQwnfRoDgqcPZ67lwdNHXU1BZN3NRAWQzE45HQck+HZfit4s/52Q9mu1B9xH5ZfwmOkmS+NRVGv//WszU8TVfcEOUS+YI5vQDSkQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(346002)(376002)(39860400002)(396003)(136003)(451199015)(40470700004)(36840700001)(46966006)(1076003)(36756003)(55016003)(82310400005)(40480700001)(40460700003)(110136005)(83380400001)(2616005)(426003)(70206006)(47076005)(16526019)(41300700001)(6666004)(8676002)(2906002)(478600001)(186003)(7696005)(8936002)(6286002)(86362001)(5660300002)(336012)(356005)(36860700001)(82740400003)(26005)(4326008)(70586007)(6636002)(316002)(7636003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2022 11:02:07.9598 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e1270f39-6215-4938-9160-08daa78a3619", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT024.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL3PR12MB6473", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds new HCA capability related to hairpin RQs. This new\ncapability, hairpin_data_buffer_locked, indicates whether HCA supports\nlocking data buffer of hairpin RQ in ICMC (Interconnect Context Memory\nCache).\n\nStruct used to define RQ configuration (RQ context) is extended with\nhairpin_data_buffer_type field, which configures data buffer for hairpin\nRQ. It can take the following values:\n\n- MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER - hairpin\n RQ's data buffer is stored in unlocked memory in ICMC.\n- MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER - hairpin\n RQ's data buffer is stored in locked memory in ICMC.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++\n drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++\n drivers/common/mlx5/mlx5_prm.h | 12 ++++++++++--\n 3 files changed, 15 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex a1e8179568..76f0b6724f 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -993,6 +993,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t\t\t\t\t\thairpin_sq_wqe_bb_size);\n \t\tattr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr,\n \t\t\t\t\t\t\t hairpin_sq_wq_in_host_mem);\n+\t\tattr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr,\n+\t\t\t\t\t\t\t hairpin_data_buffer_locked);\n \t}\n \tif (attr->log_min_stride_wqe_sz == 0)\n \t\tattr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;\n@@ -1293,6 +1295,7 @@ mlx5_devx_cmd_create_rq(void *ctx,\n \tMLX5_SET(rqc, rq_ctx, state, rq_attr->state);\n \tMLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);\n \tMLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);\n+\tMLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type);\n \tMLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);\n \tMLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);\n \tMLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 9ac2d75df4..cceaf3411d 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -193,6 +193,7 @@ struct mlx5_hca_attr {\n \tuint32_t log_max_hairpin_num_packets:5;\n \tuint32_t hairpin_sq_wqe_bb_size:4;\n \tuint32_t hairpin_sq_wq_in_host_mem:1;\n+\tuint32_t hairpin_data_buffer_locked:1;\n \tuint32_t vhca_id:16;\n \tuint32_t relaxed_ordering_write:1;\n \tuint32_t relaxed_ordering_read:1;\n@@ -313,6 +314,7 @@ struct mlx5_devx_create_rq_attr {\n \tuint32_t state:4;\n \tuint32_t flush_in_error_en:1;\n \tuint32_t hairpin:1;\n+\tuint32_t hairpin_data_buffer_type:3;\n \tuint32_t ts_format:2;\n \tuint32_t user_index:24;\n \tuint32_t cqn:24;\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 04d35ca845..9c1c93f916 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -2024,7 +2024,8 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {\n \tu8 reserved_at_160[0x3];\n \tu8 hairpin_sq_wqe_bb_size[0x5];\n \tu8 hairpin_sq_wq_in_host_mem[0x1];\n-\tu8 reserved_at_169[0x697];\n+\tu8 hairpin_data_buffer_locked[0x1];\n+\tu8 reserved_at_16a[0x696];\n };\n \n struct mlx5_ifc_esw_cap_bits {\n@@ -2304,7 +2305,9 @@ struct mlx5_ifc_rqc_bits {\n \tu8 reserved_at_c[0x1];\n \tu8 flush_in_error_en[0x1];\n \tu8 hairpin[0x1];\n-\tu8 reserved_at_f[0xB];\n+\tu8 reserved_at_f[0x6];\n+\tu8 hairpin_data_buffer_type[0x3];\n+\tu8 reserved_at_a8[0x2];\n \tu8 ts_format[0x02];\n \tu8 reserved_at_1c[0x4];\n \tu8 reserved_at_20[0x8];\n@@ -2813,6 +2816,11 @@ enum {\n \tMLX5_CQE_SIZE_128B = 0x1,\n };\n \n+enum {\n+\tMLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER = 0x0,\n+\tMLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER = 0x1,\n+};\n+\n struct mlx5_ifc_cqc_bits {\n \tu8 status[0x4];\n \tu8 as_notify[0x1];\n", "prefixes": [ "v2", "3/8" ] }