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{ "id": 117449, "url": "https://patches.dpdk.org/api/patches/117449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221006110105.2986966-2-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221006110105.2986966-2-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221006110105.2986966-2-dsosnowski@nvidia.com", "date": "2022-10-06T11:00:58", "name": "[v2,1/8] ethdev: introduce hairpin memory capabilities", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3f5313c7ea5ef6ff250a0695112b463cb865818a", "submitter": { "id": 2386, "url": "https://patches.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221006110105.2986966-2-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 25009, "url": "https://patches.dpdk.org/api/series/25009/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25009", "date": "2022-10-06T11:00:57", "name": "ethdev: introduce hairpin memory capabilities", "version": 2, "mbox": "https://patches.dpdk.org/series/25009/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117449/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/117449/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 73A97A00C2;\n\tThu, 6 Oct 2022 13:02:09 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 562C442C0A;\n\tThu, 6 Oct 2022 13:02:05 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41])\n by mails.dpdk.org (Postfix) with ESMTP id 518FA42BF0\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Thomas Monjalon <thomas@monjalon.net>, Ferruh Yigit\n <ferruh.yigit@amd.com>, Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v2 1/8] ethdev: introduce hairpin memory capabilities", "Date": "Thu, 6 Oct 2022 11:00:58 +0000", "Message-ID": "<20221006110105.2986966-2-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "References": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT011:EE_|BY5PR12MB4871:EE_", "X-MS-Office365-Filtering-Correlation-Id": "adc2a582-1e92-4f6d-ec90-08daa78a31f8", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 0SG4v7UN0zTfdiMVYrKZa5AYaVAz/UwsWP6Mj8FEGV2TsEA7guek9UklchJ/ij4o4sr5s6bo/0vxiOuxdzzQC4A0ZdK86VR0GV2zNtjuSE8yJomh3os3/0AjJ5T/J4NTkv8LEz9BaWpvrkmZEl/34Ou5Uuy4NB60tJM2Yr2o6VZUGwKEXau4gCH/bxBtcwpC2JxXPJTWUT14JSdCutYyM5BpvNJ2Wb+b9J0Nkl6tf71dS3bDWUZiuv5+TpZRrb9xbqG0agydcYWaKC8v3igkCarMjZaYdz/aq48XGBcdGqYl0QEaPdwdQqOZKmL14Wr/YC7hac2glKXGN0280q64h7ngTtiAwo3naZ4Yi6yKkPCKG0xkILFMC7x0YZinnvtFSx570lp3O5VZc0wvx42CyKM1Nj5Z/jrHDOPUh4LVHzgkRhZxtZl8VRvSEP0fjtVF1YYlXOvO9Z7ZIWn3AO6bjyRjkNhjrXYoGNwCYhR5/ottzAbFgxQKgsl3+gJFWj9tm5H/Ct6HZW/JmTj49jj5UNDvafZiljhU8XKkI6FYno8OpZt1cWSqnviop7BF4K+yjp1KqbxfxpiP1D1KXJx81acdeXNj9JUV/pr8KMBByIbVYiTxM3IwFjQ0J0Nke5WjLpk/99I+txs7v68evXo2G2BtPj4fL5cBPz8rEO3y65sVtjqfQ8QPx8u1HQUXLqpme5Z/Ua5cr6D5yia7E09Ms/Yrau46L9fPZeCfSfhkjTFwDF8gfdbFavye9EaG10hkKKB+e+prVJjbFSmDniEAQQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(136003)(346002)(39860400002)(376002)(396003)(451199015)(36840700001)(46966006)(40470700004)(1076003)(186003)(2616005)(16526019)(356005)(2906002)(82310400005)(316002)(70206006)(6666004)(40460700003)(70586007)(4326008)(110136005)(8676002)(55016003)(86362001)(478600001)(41300700001)(5660300002)(6286002)(26005)(336012)(426003)(7636003)(8936002)(7696005)(40480700001)(47076005)(36756003)(82740400003)(83380400001)(36860700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2022 11:02:01.0037 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n adc2a582-1e92-4f6d-ec90-08daa78a31f8", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT011.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB4871", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Before this patch, implementation details and configuration of hairpin\nqueues were decided internally by the PMD. Applications had no control\nover the configuration of Rx and Tx hairpin queues, despite number of\ndescriptors, explicit Tx flow mode and disabling automatic binding.\nThis patch addresses that by adding:\n\n- Hairpin queue capabilities reported by PMDs.\n- New configuration options for Rx and Tx hairpin queues.\n\nMain goal of this patch is to allow applications to provide\nconfiguration hints regarding placement of hairpin queues.\nThese hints specify whether buffers of hairpin queues should be placed\nin host memory or in dedicated device memory. Different memory options\nmay have different performance characteristics and hairpin configuration\nshould be fine-tuned to the specific application and use case.\n\nThis patch introduces new hairpin queue configuration options through\nrte_eth_hairpin_conf struct, allowing to tune Rx and Tx hairpin queues\nmemory configuration. Hairpin configuration is extended with the\nfollowing fields:\n\n- use_locked_device_memory - If set, PMD will use specialized on-device\n memory to store RX or TX hairpin queue data.\n- use_rte_memory - If set, PMD will use DPDK-managed memory to store RX\n or TX hairpin queue data.\n- force_memory - If set, PMD will be forced to use provided memory\n settings. If no appropriate resources are available, then device start\n will fail. If unset and no resources are available, PMD will fallback\n to using default type of resource for given queue.\n\nIf application chooses to use PMD default memory configuration, all of\nthese flags should remain unset.\n\nHairpin capabilities are also extended, to allow verification of support\nof given hairpin memory configurations. Struct rte_eth_hairpin_cap is\nextended with two additional fields of type rte_eth_hairpin_queue_cap:\n\n- rx_cap - memory capabilities of hairpin RX queues.\n- tx_cap - memory capabilities of hairpin TX queues.\n\nStruct rte_eth_hairpin_queue_cap exposes whether given queue type\nsupports use_locked_device_memory and use_rte_memory flags.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n doc/guides/rel_notes/release_22_11.rst | 10 ++++\n lib/ethdev/rte_ethdev.c | 44 +++++++++++++++++\n lib/ethdev/rte_ethdev.h | 68 +++++++++++++++++++++++++-\n 3 files changed, 120 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst\nindex ac67e7e710..e5c48c6b18 100644\n--- a/doc/guides/rel_notes/release_22_11.rst\n+++ b/doc/guides/rel_notes/release_22_11.rst\n@@ -66,6 +66,16 @@ New Features\n Added new function ``rte_flow_async_action_handle_query()``,\n to query the action asynchronously.\n \n+* **Added hairpin memory configurations options in ethdev API.**\n+\n+ Added new configuration flags for hairpin queues in ``rte_eth_hairpin_conf``:\n+\n+ * ``use_locked_device_memory``\n+ * ``use_rte_memory``\n+ * ``force_memory``\n+\n+ Each flag has a corresponding capability flag in ``rte_eth_hairpin_queue_cap`` struct.\n+\n * **Updated Intel iavf driver.**\n \n * Added flow subscription support.\ndiff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c\nindex 2821770e2d..bece83eb91 100644\n--- a/lib/ethdev/rte_ethdev.c\n+++ b/lib/ethdev/rte_ethdev.c\n@@ -1961,6 +1961,28 @@ rte_eth_rx_hairpin_queue_setup(uint16_t port_id, uint16_t rx_queue_id,\n \t\t\tconf->peer_count, cap.max_rx_2_tx);\n \t\treturn -EINVAL;\n \t}\n+\tif (conf->use_locked_device_memory && !cap.rx_cap.locked_device_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to use locked device memory for Rx queue, which is not supported\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (conf->use_rte_memory && !cap.rx_cap.rte_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to use DPDK memory for Rx queue, which is not supported\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (conf->use_locked_device_memory && conf->use_rte_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to use mutually exclusive memory settings for Rx queue\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (conf->force_memory &&\n+\t !conf->use_locked_device_memory &&\n+\t !conf->use_rte_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to force Rx queue memory settings, but none is set\");\n+\t\treturn -EINVAL;\n+\t}\n \tif (conf->peer_count == 0) {\n \t\tRTE_ETHDEV_LOG(ERR,\n \t\t\t\"Invalid value for number of peers for Rx queue(=%u), should be: > 0\",\n@@ -2128,6 +2150,28 @@ rte_eth_tx_hairpin_queue_setup(uint16_t port_id, uint16_t tx_queue_id,\n \t\t\tconf->peer_count, cap.max_tx_2_rx);\n \t\treturn -EINVAL;\n \t}\n+\tif (conf->use_locked_device_memory && !cap.tx_cap.locked_device_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to use locked device memory for Tx queue, which is not supported\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (conf->use_rte_memory && !cap.tx_cap.rte_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to use DPDK memory for Tx queue, which is not supported\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (conf->use_locked_device_memory && conf->use_rte_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to use mutually exclusive memory settings for Tx queue\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (conf->force_memory &&\n+\t !conf->use_locked_device_memory &&\n+\t !conf->use_rte_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to force Tx queue memory settings, but none is set\");\n+\t\treturn -EINVAL;\n+\t}\n \tif (conf->peer_count == 0) {\n \t\tRTE_ETHDEV_LOG(ERR,\n \t\t\t\"Invalid value for number of peers for Tx queue(=%u), should be: > 0\",\ndiff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h\nindex a21f58b9cd..eab931d3b2 100644\n--- a/lib/ethdev/rte_ethdev.h\n+++ b/lib/ethdev/rte_ethdev.h\n@@ -1092,6 +1092,28 @@ struct rte_eth_txconf {\n \tvoid *reserved_ptrs[2]; /**< Reserved for future fields */\n };\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * A structure used to return the Tx or Rx hairpin queue capabilities that are supported.\n+ */\n+struct rte_eth_hairpin_queue_cap {\n+\t/**\n+\t * When set, PMD supports placing descriptors and/or data buffers\n+\t * in dedicated device memory.\n+\t */\n+\tuint32_t locked_device_memory:1;\n+\n+\t/**\n+\t * When set, PMD supports placing descriptors and/or data buffers\n+\t * in host memory managed by DPDK.\n+\t */\n+\tuint32_t rte_memory:1;\n+\n+\tuint32_t reserved:30; /**< Reserved for future fields */\n+};\n+\n /**\n * @warning\n * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n@@ -1106,6 +1128,8 @@ struct rte_eth_hairpin_cap {\n \t/** Max number of Tx queues to be connected to one Rx queue. */\n \tuint16_t max_tx_2_rx;\n \tuint16_t max_nb_desc; /**< The max num of descriptors. */\n+\tstruct rte_eth_hairpin_queue_cap rx_cap; /**< Rx hairpin queue capabilities. */\n+\tstruct rte_eth_hairpin_queue_cap tx_cap; /**< Tx hairpin queue capabilities. */\n };\n \n #define RTE_ETH_MAX_HAIRPIN_PEERS 32\n@@ -1149,11 +1173,51 @@ struct rte_eth_hairpin_conf {\n \t * function after all the queues are set up properly and the ports are\n \t * started. Also, the hairpin unbind function should be called\n \t * accordingly before stopping a port that with hairpin configured.\n-\t * - When clear, the PMD will try to enable the hairpin with the queues\n+\t * - When cleared, the PMD will try to enable the hairpin with the queues\n \t * configured automatically during port start.\n \t */\n \tuint32_t manual_bind:1;\n-\tuint32_t reserved:14; /**< Reserved bits. */\n+\n+\t/**\n+\t * Use locked device memory as a backing storage.\n+\t *\n+\t * - When set, PMD will attempt place descriptors and/or data buffers\n+\t * in dedicated device memory.\n+\t * - When cleared, PMD will use default memory type as a backing storage.\n+\t * Please refer to PMD documentation for details.\n+\t *\n+\t * API user should check if PMD supports this configuration flag using\n+\t * @see rte_eth_dev_hairpin_capability_get.\n+\t */\n+\tuint32_t use_locked_device_memory:1;\n+\n+\t/**\n+\t * Use DPDK memory as backing storage.\n+\t *\n+\t * - When set, PMD will attempt place descriptors and/or data buffers\n+\t * in host memory managed by DPDK.\n+\t * - When cleared, PMD will use default memory type as a backing storage.\n+\t * Please refer to PMD documentation for details.\n+\t *\n+\t * API user should check if PMD supports this configuration flag using\n+\t * @see rte_eth_dev_hairpin_capability_get.\n+\t */\n+\tuint32_t use_rte_memory:1;\n+\n+\t/**\n+\t * Force usage of hairpin memory configuration.\n+\t *\n+\t * - When set, PMD will attempt to use specified memory settings.\n+\t * If resource allocation fails, then hairpin queue allocation\n+\t * will result in an error.\n+\t * - When clear, PMD will attempt to use specified memory settings.\n+\t * If resource allocation fails, then PMD will retry\n+\t * allocation with default configuration.\n+\t */\n+\tuint32_t force_memory:1;\n+\n+\tuint32_t reserved:11; /**< Reserved bits. */\n+\n \tstruct rte_eth_hairpin_peer peers[RTE_ETH_MAX_HAIRPIN_PEERS];\n };\n \n", "prefixes": [ "v2", "1/8" ] }