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GET /api/patches/117102/?format=api
{ "id": 117102, "url": "https://patches.dpdk.org/api/patches/117102/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220929050304.1678012-2-abdullah.sevincer@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220929050304.1678012-2-abdullah.sevincer@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220929050304.1678012-2-abdullah.sevincer@intel.com", "date": "2022-09-29T05:03:03", "name": "[v10,2/3] event/dlb2: add fence bypass option for producer ports", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "84909ba31e9b341801139e9e7c93dd84ca647c2a", "submitter": { "id": 2843, "url": "https://patches.dpdk.org/api/people/2843/?format=api", "name": "Sevincer, Abdullah", "email": "abdullah.sevincer@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220929050304.1678012-2-abdullah.sevincer@intel.com/mbox/", "series": [ { "id": 24897, "url": "https://patches.dpdk.org/api/series/24897/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=24897", "date": "2022-09-29T05:03:04", "name": "[v10,1/3] event/dlb2: add producer port probing optimization", "version": 10, "mbox": "https://patches.dpdk.org/series/24897/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117102/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/117102/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3D687A00C5;\n\tThu, 29 Sep 2022 07:03:24 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 432FC427F5;\n\tThu, 29 Sep 2022 07:03:16 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id B2BD540FAE\n for <dev@dpdk.org>; Thu, 29 Sep 2022 07:03:12 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 28 Sep 2022 22:03:10 -0700", "from txanpdk02.an.intel.com ([10.123.117.76])\n by orsmga005.jf.intel.com with ESMTP; 28 Sep 2022 22:03:07 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1664427792; x=1695963792;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=VkabtjjukNabY6kku20RObaxlU9mXIoYFE3pxHo0LkA=;\n b=O0a5Auy1Nj8LT4KIawdXkoHDcNDVocil4pYTAvnLhoorgJ+9v+CFMG9W\n IzXczowMgJPqYLoSN981aRB7PFmabywtuEZuTl8iBG/pdCIR2oCda+Oab\n s992ItNy3flfxrsdD8PX+dTiZTXnm5QPNQ1NWeNLHv4IDecw8NuwBaZ4x\n ReYcReREKVJsMcjkyePkc74CA1MkWQM9T88vmS6KEp9hepgBGe4Sg5fgO\n 842J3bFGstYipceCJSZxW+gxShbfR2ZSDpkhsOturRZe1ZEiacQJ/m+Xv\n VFIvRc8ZpQoI6nJd9bKSMCRt5JbHIvHZ2IVLz3+WZ7kSJXB/H6p8fEVkz g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10484\"; a=\"284928578\"", "E=Sophos;i=\"5.93,354,1654585200\"; d=\"scan'208\";a=\"284928578\"", "E=McAfee;i=\"6500,9779,10484\"; a=\"797417388\"", "E=Sophos;i=\"5.93,354,1654585200\"; d=\"scan'208\";a=\"797417388\"" ], "X-ExtLoop1": "1", "From": "Abdullah Sevincer <abdullah.sevincer@intel.com>", "To": "dev@dpdk.org", "Cc": "jerinj@marvell.com,\n\tAbdullah Sevincer <abdullah.sevincer@intel.com>", "Subject": "[PATCH v10 2/3] event/dlb2: add fence bypass option for producer\n ports", "Date": "Thu, 29 Sep 2022 00:03:03 -0500", "Message-Id": "<20220929050304.1678012-2-abdullah.sevincer@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220929050304.1678012-1-abdullah.sevincer@intel.com>", "References": "<20220820005957.2986689-2-timothy.mcdaniel@intel.com>\n <20220929050304.1678012-1-abdullah.sevincer@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "If producer thread is only acting as a bridge between NIC and DLB, then\nperformance can be greatly improved by bypassing the fence instruction.\nDLB enqueue API calls memory fence once per enqueue burst. If prodcuer\nthread is just reading from NIC and sending to DLB without updating\nthe read buffers or buffer headers OR producer is not writing\nto data structures with dependencies on the enqueue write order, then\nfencing can be safely disabled.\n\nSigned-off-by: Abdullah Sevincer <abdullah.sevincer@intel.com>\n---\n drivers/event/dlb2/dlb2.c | 29 +++++++++++++++++++++--------\n 1 file changed, 21 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex 6a9db4b642..4dd1d55ddc 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -35,6 +35,16 @@\n #include \"dlb2_iface.h\"\n #include \"dlb2_inline_fns.h\"\n \n+/*\n+ * Bypass memory fencing instructions when port is of Producer type.\n+ * This should be enabled very carefully with understanding that producer\n+ * is not doing any writes which need fencing. The movdir64 instruction used to\n+ * enqueue events to DLB is a weakly-ordered instruction and movdir64 write\n+ * to DLB can go ahead of relevant application writes like updates to buffers\n+ * being sent with event\n+ */\n+#define DLB2_BYPASS_FENCE_ON_PP 0 /* 1 == Bypass fence, 0 == do not bypass */\n+\n /*\n * Resources exposed to eventdev. Some values overridden at runtime using\n * values returned by the DLB kernel driver.\n@@ -1985,21 +1995,15 @@ dlb2_eventdev_port_setup(struct rte_eventdev *dev,\n \tsw_credit_quanta = dlb2->sw_credit_quanta;\n \thw_credit_quanta = dlb2->hw_credit_quanta;\n \n+\tev_port->qm_port.is_producer = false;\n \tev_port->qm_port.is_directed = port_conf->event_port_cfg &\n \t\tRTE_EVENT_PORT_CFG_SINGLE_LINK;\n \n-\t/*\n-\t * Validate credit config before creating port\n-\t */\n-\n-\t/* Default for worker ports */\n-\tsw_credit_quanta = dlb2->sw_credit_quanta;\n-\thw_credit_quanta = dlb2->hw_credit_quanta;\n-\n \tif (port_conf->event_port_cfg & RTE_EVENT_PORT_CFG_HINT_PRODUCER) {\n \t\t/* Producer type ports. Mostly enqueue */\n \t\tsw_credit_quanta = DLB2_SW_CREDIT_P_QUANTA_DEFAULT;\n \t\thw_credit_quanta = DLB2_SW_CREDIT_P_BATCH_SZ;\n+\t\tev_port->qm_port.is_producer = true;\n \t}\n \tif (port_conf->event_port_cfg & RTE_EVENT_PORT_CFG_HINT_CONSUMER) {\n \t\t/* Consumer type ports. Mostly dequeue */\n@@ -2009,6 +2013,10 @@ dlb2_eventdev_port_setup(struct rte_eventdev *dev,\n \tev_port->credit_update_quanta = sw_credit_quanta;\n \tev_port->qm_port.hw_credit_quanta = hw_credit_quanta;\n \n+\t/*\n+\t * Validate credit config before creating port\n+\t */\n+\n \tif (port_conf->enqueue_depth > sw_credit_quanta ||\n \t port_conf->enqueue_depth > hw_credit_quanta) {\n \t\tDLB2_LOG_ERR(\"Invalid port config. Enqueue depth %d must be <= credit quanta %d and batch size %d\\n\",\n@@ -3073,7 +3081,12 @@ __dlb2_event_enqueue_burst(void *event_port,\n \t\tdlb2_event_build_hcws(qm_port, &events[i], j - pop_offs,\n \t\t\t\t sched_types, queue_ids);\n \n+#if DLB2_BYPASS_FENCE_ON_PP == 1\n+\t\t/* Bypass fence instruction for producer ports */\n+\t\tdlb2_hw_do_enqueue(qm_port, i == 0 && !qm_port->is_producer, port_data);\n+#else\n \t\tdlb2_hw_do_enqueue(qm_port, i == 0, port_data);\n+#endif\n \n \t\t/* Don't include the token pop QE in the enqueue count */\n \t\ti += j - pop_offs;\n", "prefixes": [ "v10", "2/3" ] }