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{
    "id": 117,
    "url": "https://patches.dpdk.org/api/patches/117/?format=api",
    "web_url": "https://patches.dpdk.org/patch/117/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1406876916-24869-5-git-send-email-jingjing.wu@intel.com>",
    "date": "2014-08-01T07:08:34",
    "name": "[dpdk-dev,4/6] i40e: function implement in i40e for flow director filter programming",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "629e4ce2b725995362161ead95eb2f6b05f4d87f",
    "submitter": {
        "id": 47,
        "url": "https://patches.dpdk.org/api/people/47/?format=api",
        "name": "Wu, Jingjing",
        "email": "jingjing.wu@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/patch/117/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/117/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/117/checks/",
    "tags": {},
    "headers": {
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "Return-Path": "<wujingji@shecgisg004.sh.intel.com>",
        "Message-Id": "<1406876916-24869-5-git-send-email-jingjing.wu@intel.com>",
        "X-Mailer": "git-send-email 1.7.0.7",
        "To": "dev@dpdk.org",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-BeenThere": "dev@dpdk.org",
        "Received": [
            "from mga03.intel.com (mga03.intel.com [143.182.124.21])\n\tby dpdk.org (Postfix) with ESMTP id D5D1DB37A\n\tfor <dev@dpdk.org>; Fri,  1 Aug 2014 09:06:57 +0200 (CEST)",
            "from azsmga001.ch.intel.com ([10.2.17.19])\n\tby azsmga101.ch.intel.com with ESMTP; 01 Aug 2014 00:09:01 -0700",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby azsmga001.ch.intel.com with ESMTP; 01 Aug 2014 00:08:59 -0700",
            "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s7178voe014916;\n\tFri, 1 Aug 2014 15:08:57 +0800",
            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s7178ssI025056; Fri, 1 Aug 2014 15:08:56 +0800",
            "(from wujingji@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s7178sfK025052; \n\tFri, 1 Aug 2014 15:08:54 +0800"
        ],
        "Subject": "[dpdk-dev] [PATCH 4/6] i40e: function implement in i40e for flow\n\tdirector filter programming",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "In-Reply-To": "<1406876916-24869-1-git-send-email-jingjing.wu@intel.com>",
        "X-ExtLoop1": "1",
        "Precedence": "list",
        "From": "Jingjing Wu <jingjing.wu@intel.com>",
        "X-IronPort-AV": "E=Sophos;i=\"5.01,778,1400050800\"; d=\"scan'208\";a=\"463889067\"",
        "References": "<1406876916-24869-1-git-send-email-jingjing.wu@intel.com>",
        "X-List-Received-Date": "Fri, 01 Aug 2014 07:06:59 -0000",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Date": "Fri,  1 Aug 2014 15:08:34 +0800",
        "X-Mailman-Version": "2.1.15"
    },
    "content": "support the API ops defined in ethdev, the behavior according to each command:\n\n  RTE_CMD_FDIR_RULE_ADD: add a new FDIR filter rule.\n  RTE_CMD_FDIR_RULE_DEL: delete a FDIR filter rule. \n  RTE_CMD_FDIR_FLUSH   : clear all FDIR filter rules.\n  RTE_CMD_FDIR_INFO_GET: get FDIR information.\n\nSigned-off-by: jingjing.wu <jingjing.wu@intel.com>\n---\n lib/librte_pmd_i40e/Makefile      |   4 +\n lib/librte_pmd_i40e/i40e_ethdev.c |  53 +++++++++\n lib/librte_pmd_i40e/i40e_ethdev.h |  10 ++\n lib/librte_pmd_i40e/i40e_fdir.c   | 220 ++++++++++++++++++++++++++++++++++++++\n lib/librte_pmd_i40e/rte_i40e.h    | 125 ++++++++++++++++++++++\n 5 files changed, 412 insertions(+)\n create mode 100644 lib/librte_pmd_i40e/rte_i40e.h",
    "diff": "diff --git a/lib/librte_pmd_i40e/Makefile b/lib/librte_pmd_i40e/Makefile\nindex 6537654..3da20c5 100644\n--- a/lib/librte_pmd_i40e/Makefile\n+++ b/lib/librte_pmd_i40e/Makefile\n@@ -88,6 +88,10 @@ SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_rxtx.c\n SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_ethdev_vf.c\n SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_pf.c\n SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_fdir.c\n+\n+# install this header file\n+SYMLINK-$(CONFIG_RTE_LIBRTE_I40E_PMD)-include := rte_i40e.h\n+\n # this lib depends upon:\n DEPDIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += lib/librte_eal lib/librte_ether\n DEPDIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += lib/librte_mempool lib/librte_mbuf\ndiff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c\nindex 47125c7..c4637be 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.c\n@@ -48,6 +48,7 @@\n #include <rte_malloc.h>\n #include <rte_memcpy.h>\n #include <rte_dev.h>\n+#include <rte_eth_features.h>\n \n #include \"i40e_logs.h\"\n #include \"i40e/i40e_register_x710_int.h\"\n@@ -203,6 +204,9 @@ static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,\n \t\t\t\t    struct rte_eth_rss_conf *rss_conf);\n static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n \t\t\t\t      struct rte_eth_rss_conf *rss_conf);\n+static int i40e_rx_classification_filter_ctl(struct rte_eth_dev *dev,\n+\t\t\t\t\t     enum rte_eth_command cmd,\n+\t\t\t\t\t     void *args);\n \n /* Default hash key buffer for RSS */\n static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];\n@@ -248,6 +252,7 @@ static struct eth_dev_ops i40e_eth_dev_ops = {\n \t.reta_query                   = i40e_dev_rss_reta_query,\n \t.rss_hash_update              = i40e_dev_rss_hash_update,\n \t.rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,\n+\t.rx_classification_filter_ctl = i40e_rx_classification_filter_ctl,\n };\n \n static struct eth_driver rte_i40e_pmd = {\n@@ -3984,3 +3989,51 @@ i40e_pf_config_mq_rx(struct i40e_pf *pf)\n \n \treturn 0;\n }\n+\n+static int\n+i40e_rx_classification_filter_ctl(struct rte_eth_dev *dev,\n+\t\t\t\t  enum rte_eth_command cmd,\n+\t\t\t\t  void *args)\n+{\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct rte_i40e_fdir_entry *fdir_entry;\n+\tstruct rte_i40e_fdir_info *fdir_info;\n+\tint ret = I40E_SUCCESS;\n+\n+\tswitch (cmd) {\n+\tcase RTE_CMD_FDIR_RULE_ADD:\n+\t\tif (args == NULL)\n+\t\t\treturn I40E_ERR_PARAM;\n+\t\tfdir_entry = (struct rte_i40e_fdir_entry *)args;\n+\t\tret = i40e_fdir_filter_programming(pf,\n+\t\t\tfdir_entry->soft_id,\n+\t\t\t&fdir_entry->input,\n+\t\t\t&fdir_entry->action,\n+\t\t\tTRUE);\n+\t\tbreak;\n+\tcase RTE_CMD_FDIR_RULE_DEL:\n+\t\tif (args == NULL)\n+\t\t\treturn I40E_ERR_PARAM;\n+\t\tfdir_entry = (struct rte_i40e_fdir_entry *)args;\n+\t\tret = i40e_fdir_filter_programming(pf,\n+\t\t\tfdir_entry->soft_id,\n+\t\t\t&fdir_entry->input,\n+\t\t\t&fdir_entry->action,\n+\t\t\tFALSE);\n+\t\tbreak;\n+\tcase RTE_CMD_FDIR_INFO_GET:\n+\t\tif (args == NULL)\n+\t\t\treturn I40E_ERR_PARAM;\n+\t\tfdir_info = (struct rte_i40e_fdir_info *)args;\n+\t\ti40e_fdir_info_get(dev, fdir_info);\n+\t\tbreak;\n+\tcase RTE_CMD_FDIR_FLUSH:\n+\t\tret = i40e_fdir_flush(pf);\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"unknown command type %u\\n\", cmd);\n+\t\tret = I40E_ERR_PARAM;\n+\t\tbreak;\n+\t}\n+\treturn ret;\n+}\ndiff --git a/lib/librte_pmd_i40e/i40e_ethdev.h b/lib/librte_pmd_i40e/i40e_ethdev.h\nindex c2c7fa9..7755f5a 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.h\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.h\n@@ -34,6 +34,8 @@\n #ifndef _I40E_ETHDEV_H_\n #define _I40E_ETHDEV_H_\n \n+#include \"rte_i40e.h\"\n+\n #define I40E_AQ_LEN               32\n #define I40E_AQ_BUF_SZ            4096\n /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */\n@@ -332,6 +334,14 @@ i40e_fdir_setup_rx_resources(struct i40e_pf *pf,\n \t\t\t\t    unsigned int socket_id);\n int i40e_fdir_setup(struct i40e_pf *pf);\n void i40e_fdir_teardown(struct i40e_pf *pf);\n+int i40e_fdir_flush(struct i40e_pf *pf);\n+int i40e_fdir_filter_programming(struct i40e_pf *pf,\n+\t\t\tuint16_t soft_id,\n+\t\t\tstruct rte_i40e_fdir_input *fdir_filter,\n+\t\t\tstruct rte_i40e_fdir_action *fdir_action,\n+\t\t\tbool add);\n+void i40e_fdir_info_get(struct rte_eth_dev *dev,\n+\t\t\t   struct rte_i40e_fdir_info *fdir);\n \n /* I40E_DEV_PRIVATE_TO */\n #define I40E_DEV_PRIVATE_TO_PF(adapter) \\\ndiff --git a/lib/librte_pmd_i40e/i40e_fdir.c b/lib/librte_pmd_i40e/i40e_fdir.c\nindex ecb4a95..373a366 100644\n--- a/lib/librte_pmd_i40e/i40e_fdir.c\n+++ b/lib/librte_pmd_i40e/i40e_fdir.c\n@@ -48,10 +48,23 @@\n #include \"i40e/i40e_type.h\"\n #include \"i40e_ethdev.h\"\n #include \"i40e_rxtx.h\"\n+/* Wait count and inteval for fdir filter programming */\n+#define I40E_FDIR_WAIT_COUNT       10\n+#define I40E_FDIR_WAIT_INTERVAL_US 1000\n+/* Wait count and inteval for fdir filter flush */\n+#define I40E_FDIR_FLUSH_RETRY       5\n+#define I40E_FDIR_FLUSH_INTERVAL_MS 5000\n \n #define I40E_COUNTER_PF           2\n #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)\n \n+#ifndef RTE_MBUF_DATA_DMA_ADDR\n+#define RTE_MBUF_DATA_DMA_ADDR(mb) \\\n+\t((uint64_t)((mb)->buf_physaddr + \\\n+\t(uint64_t)((char *)((mb)->pkt.data) - \\\n+\t(char *)(mb)->buf_addr)))\n+#endif\n+\n /*\n  * i40e_fdir_setup - reserve and initialize the Flow Director resources\n  * @pf: board private structure\n@@ -133,3 +146,210 @@ i40e_fdir_teardown(struct i40e_pf *pf)\n \tpf->fdir.fdir_vsi = NULL;\n \treturn;\n }\n+\n+/*\n+ * i40e_fdir_flush - clear all filters of Flow Director\n+ * @pf: board private structure\n+ */\n+int\n+i40e_fdir_flush(struct i40e_pf *pf)\n+{\n+\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n+\tuint32_t reg;\n+\tuint16_t guarant_cnt, best_cnt;\n+\tint i;\n+\n+\tI40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);\n+\tI40E_WRITE_FLUSH(hw);\n+\n+\tfor (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {\n+\t\trte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);\n+\t\treg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);\n+\t\tif (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))\n+\t\t\tbreak;\n+\t}\n+\tif (i >= I40E_FDIR_FLUSH_RETRY) {\n+\t\tPMD_DRV_LOG(ERR, \"FD table did not flush, may need more time\\n\");\n+\t\treturn I40E_ERR_TIMEOUT;\n+\t}\n+\tguarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &\n+\t\t\t\tI40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>\n+\t\t\t\tI40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);\n+\tbest_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &\n+\t\t\t\tI40E_PFQF_FDSTAT_BEST_CNT_MASK) >>\n+\t\t\t\tI40E_PFQF_FDSTAT_BEST_CNT_SHIFT);\n+\tif (guarant_cnt != 0 || best_cnt != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to flush FD table\\n\");\n+\t\treturn I40E_ERR_CONFIG;\n+\t} else\n+\t\tPMD_DRV_LOG(INFO, \"FD table Flush success\\n\");\n+\treturn I40E_SUCCESS;\n+}\n+\n+/* Construct the tx flags */\n+static inline uint64_t\n+i40e_build_ctob(uint32_t td_cmd,\n+\t\tuint32_t td_offset,\n+\t\tunsigned int size,\n+\t\tuint32_t td_tag)\n+{\n+\treturn rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |\n+\t\t\t((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |\n+\t\t\t((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |\n+\t\t\t((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |\n+\t\t\t((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));\n+}\n+\n+/*\n+ * Program A flow diretor filter rule.\n+ * Is done by Flow Director Programming\n+ * Descriptor  followed by packet structure that contains the filter fields\n+ * need to match.\n+ */\n+int\n+i40e_fdir_filter_programming(struct i40e_pf *pf,\n+\t\t\tuint16_t soft_id,\n+\t\t\tstruct rte_i40e_fdir_input *fdir_input,\n+\t\t\tstruct rte_i40e_fdir_action *fdir_action,\n+\t\t\tbool add)\n+{\n+\tstruct i40e_tx_queue *txq = pf->fdir.txq;\n+\tvolatile struct i40e_tx_desc *txdp;\n+\tstruct rte_mbuf *mbuf = fdir_input->data;\n+\tvolatile struct i40e_filter_program_desc *fdirdp;\n+\tuint64_t dma_addr;\n+\tuint32_t td_cmd;\n+\tuint16_t i;\n+\tuint8_t dest;\n+\n+\tPMD_DRV_LOG(INFO, \"filling filter prgramming descriptor\\n\");\n+\tfdirdp = (volatile struct i40e_filter_program_desc *)\n+\t\t\t(&(txq->tx_ring[txq->tx_tail]));\n+\n+\tfdirdp->qindex_flex_ptype_vsi =\n+\t\t\trte_cpu_to_le_32((fdir_action->rx_queue <<\n+\t\t\t\t\t  I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &\n+\t\t\t\t\t  I40E_TXD_FLTR_QW0_QINDEX_MASK);\n+\n+\tfdirdp->qindex_flex_ptype_vsi |=\n+\t\t\trte_cpu_to_le_32((fdir_input->flex_off <<\n+\t\t\t\t\t  I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &\n+\t\t\t\t\t  I40E_TXD_FLTR_QW0_FLEXOFF_MASK);\n+\n+\tfdirdp->qindex_flex_ptype_vsi |=\n+\t\t\trte_cpu_to_le_32((fdir_input->pctype <<\n+\t\t\t\t\t  I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &\n+\t\t\t\t\t  I40E_TXD_FLTR_QW0_PCTYPE_MASK);\n+\n+\t/* Use LAN VSI Id if not programmed by user */\n+\tif (fdir_input->dest_vsi == 0)\n+\t\tfdirdp->qindex_flex_ptype_vsi |=\n+\t\t\trte_cpu_to_le_32((pf->main_vsi->vsi_id <<\n+\t\t\t\t\t  I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &\n+\t\t\t\t\t  I40E_TXD_FLTR_QW0_DEST_VSI_MASK);\n+\telse\n+\t\tfdirdp->qindex_flex_ptype_vsi |=\n+\t\t\trte_cpu_to_le_32((fdir_input->dest_vsi <<\n+\t\t\t\t\t  I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &\n+\t\t\t\t\t  I40E_TXD_FLTR_QW0_DEST_VSI_MASK);\n+\n+\tfdirdp->dtype_cmd_cntindex =\n+\t\t\trte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);\n+\n+\tif (add)\n+\t\tfdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(\n+\t\t\t\tI40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<\n+\t\t\t\tI40E_TXD_FLTR_QW1_PCMD_SHIFT);\n+\telse\n+\t\tfdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(\n+\t\t\t\tI40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<\n+\t\t\t\tI40E_TXD_FLTR_QW1_PCMD_SHIFT);\n+\n+\tif (fdir_action->drop == RTE_I40E_DEST_DROP_PACKET)\n+\t\tdest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;\n+\telse\n+\t\tdest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;\n+\tfdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<\n+\t\t\t\tI40E_TXD_FLTR_QW1_DEST_SHIFT) &\n+\t\t\t\tI40E_TXD_FLTR_QW1_DEST_MASK);\n+\n+\tfdirdp->dtype_cmd_cntindex |=\n+\t\trte_cpu_to_le_32((fdir_action->report_status<<\n+\t\t\t\tI40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &\n+\t\t\t\tI40E_TXD_FLTR_QW1_FD_STATUS_MASK);\n+\n+\tfdirdp->dtype_cmd_cntindex |=\n+\t\t\trte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);\n+\tif (fdir_action->cnt_index != 0)\n+\t\tfdirdp->dtype_cmd_cntindex |=\n+\t\t\t\trte_cpu_to_le_32((fdir_action->cnt_index <<\n+\t\t\t\tI40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &\n+\t\t\t\tI40E_TXD_FLTR_QW1_CNTINDEX_MASK);\n+\telse\n+\t\tfdirdp->dtype_cmd_cntindex |=\n+\t\t\t\trte_cpu_to_le_32((pf->fdir.match_counter_index <<\n+\t\t\t\tI40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &\n+\t\t\t\tI40E_TXD_FLTR_QW1_CNTINDEX_MASK);\n+\n+\tfdirdp->fd_id = rte_cpu_to_le_32(soft_id);\n+\ttxq->tx_tail++;\n+\tif (txq->tx_tail >= txq->nb_tx_desc)\n+\t\ttxq->tx_tail = 0;\n+\n+\tPMD_DRV_LOG(INFO, \"filling transmit descriptor\\n\");\n+\ttxdp = &(txq->tx_ring[txq->tx_tail]);\n+\tdma_addr = RTE_MBUF_DATA_DMA_ADDR(mbuf);\n+\ttxdp->buffer_addr = rte_cpu_to_le_64(dma_addr);\n+\ttd_cmd = I40E_TX_DESC_CMD_EOP |\n+\t\t I40E_TX_DESC_CMD_RS  |\n+\t\t I40E_TX_DESC_CMD_DUMMY;\n+\n+\ttxdp->cmd_type_offset_bsz =\n+\t\ti40e_build_ctob(td_cmd, 0,\n+\t\t\t\tmbuf->pkt.data_len, 0);\n+\n+\ttxq->tx_tail++;\n+\tif (txq->tx_tail >= txq->nb_tx_desc)\n+\t\ttxq->tx_tail = 0;\n+\t/* Update the tx tail register */\n+\trte_wmb();\n+\tI40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);\n+\n+\tfor (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {\n+\t\trte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);\n+\t\tif (txdp->cmd_type_offset_bsz &\n+\t\t\t\trte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))\n+\t\t\tbreak;\n+\t}\n+\tif (i >= I40E_FDIR_WAIT_COUNT) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to program FDIR filter\\n\");\n+\t\treturn I40E_ERR_TIMEOUT;\n+\t}\n+\n+\treturn I40E_SUCCESS;\n+}\n+\n+/*\n+ * i40e_fdir_info_get - get information of Flow Director\n+ * @dev: ethernet device to add filter to\n+ * @fdir: a pointer to a structure of type *rte_eth_dev_fdir* to be filled with\n+ *    the flow director information.\n+ **/\n+void\n+i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_i40e_fdir_info *fdir)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint32_t pfqf_ctl;\n+\n+\tpfqf_ctl = I40E_READ_REG(hw, I40E_PFQF_CTL_0);\n+\tfdir->mode = pfqf_ctl & I40E_PFQF_CTL_0_FD_ENA_MASK ? 1 : 0;\n+\tfdir->guarant_spc = (uint16_t)hw->func_caps.fd_filters_guaranteed;\n+\tfdir->guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &\n+\t\t\t\tI40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>\n+\t\t\t\tI40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);\n+\tfdir->best_spc = (uint16_t)hw->func_caps.fd_filters_best_effort;\n+\tfdir->best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &\n+\t\t\t\tI40E_PFQF_FDSTAT_BEST_CNT_MASK) >>\n+\t\t\t\tI40E_PFQF_FDSTAT_BEST_CNT_SHIFT);\n+\treturn;\n+}\ndiff --git a/lib/librte_pmd_i40e/rte_i40e.h b/lib/librte_pmd_i40e/rte_i40e.h\nnew file mode 100644\nindex 0000000..699ea53\n--- /dev/null\n+++ b/lib/librte_pmd_i40e/rte_i40e.h\n@@ -0,0 +1,125 @@\n+/*-\n+ *   BSD LICENSE\n+ *\n+ *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+ *   All rights reserved.\n+ *\n+ *   Redistribution and use in source and binary forms, with or without\n+ *   modification, are permitted provided that the following conditions\n+ *   are met:\n+ *\n+ *     * Redistributions of source code must retain the above copyright\n+ *       notice, this list of conditions and the following disclaimer.\n+ *     * Redistributions in binary form must reproduce the above copyright\n+ *       notice, this list of conditions and the following disclaimer in\n+ *       the documentation and/or other materials provided with the\n+ *       distribution.\n+ *     * Neither the name of Intel Corporation nor the names of its\n+ *       contributors may be used to endorse or promote products derived\n+ *       from this software without specific prior written permission.\n+ *\n+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_I40E_H_\n+#define _RTE_I40E_H_\n+\n+/**\n+ * @file\n+ *\n+ * RTE I40E\n+ *\n+ * The I40E defines the commands and structures specifically for i40e hardware\n+ * features. As different types of NIC hardware may have different features,\n+ * they might not be common for all types of NIC hardwares. The commands and\n+ * structures can be used in applications directly together with generalized\n+ * APIs declared in rte_ethdev.h. The commands couldn't be supported by\n+ * non-i40e PMD.\n+ */\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#define I40E_FDIR_PKT_LEN                   512\n+#define I40E_FDIR_IP_DEFAULT_LEN            0x003C\n+#define I40E_FDIR_IP_DEFAULT_TTL            0x40\n+#define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45\n+#define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50\n+#define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60300000\n+#define I40E_FDIR_IPv6_DEFAULT_PAYLOAD_LEN  0x0014\n+#define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF\n+#define I40E_FDIR_UDP_DEFAULT_LEN           0x0028\n+\n+enum rte_i40e_fdir_status {\n+\tRTE_I40E_FDIR_NO_REPORT_STATUS = 0, /**< no report FDIR. */\n+\tRTE_I40E_FDIR_REPORT_FD_ID,         /**< only report FD ID. */\n+\tRTE_I40E_FDIR_REPORT_FD_ID_FLEX_4,  /**< report FD ID and 4 flex bytes. */\n+\tRTE_I40E_FDIR_REPORT_FLEX_8,        /**< report 8 flex bytes. */\n+};\n+\n+#define RTE_I40E_DEST_DROP_PACKET          0x01\n+#define RTE_I40E_DEST_DIRECT_PACKET_QINDEX 0x02\n+\n+/**\n+ * A structure used to define the input for an flow director filter entry\n+ */\n+struct rte_i40e_fdir_input {\n+\tuint8_t  pctype;\n+\tuint8_t  flex_off;\n+\tuint16_t dest_vsi; /**< destination VSI*/\n+\tstruct rte_mbuf *data; /**< mbuf store raw packet used to program */\n+};\n+\n+/**\n+ * A structure used to define an action when match FDIR packet filter.\n+ */\n+struct rte_i40e_fdir_action {\n+\tuint16_t rx_queue;       /**< queue assigned to if fdir match. */\n+\tuint16_t cnt_index;      /**< statistic count index */\n+\tuint8_t  drop;            /**< accept or reject */\n+\tenum rte_i40e_fdir_status report_status;  /**< status report. */\n+};\n+\n+/**\n+ * For commands:\n+ * 'RTE_CMD_FDIR_RULE_ADD'\n+ * 'RTE_CMD_FDIR_RULE_DEL'\n+ *\n+ * A structure used to define the flow director filter entry\n+ */\n+struct rte_i40e_fdir_entry {\n+\tuint16_t soft_id;               /**< id */\n+\tstruct rte_i40e_fdir_input input;   /**< input set */\n+\tstruct rte_i40e_fdir_action action; /**< action taken when match */\n+};\n+\n+/**\n+ * For commands:\n+ * 'RTE_CMD_FDIR_INFO_GET'\n+ *\n+ * A structure used for user to get the information of fdir feature.\n+ */\n+struct rte_i40e_fdir_info {\n+\tuint8_t  mode;         /**< 0 is disable, 1 is enable. */\n+\tuint16_t guarant_spc;  /**< guaranteed spaces.*/\n+\tuint16_t guarant_cnt;  /**< Number of filters in guaranteed spaces. */\n+\tuint16_t best_spc;     /**< best effort spaces.*/\n+\tuint16_t best_cnt;     /**< Number of filters in best effort spaces. */\n+};\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_I40E_H_ */\n",
    "prefixes": [
        "dpdk-dev",
        "4/6"
    ]
}