Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/116755/?format=api
{ "id": 116755, "url": "https://patches.dpdk.org/api/patches/116755/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220923144334.27736-18-suanmingm@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220923144334.27736-18-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220923144334.27736-18-suanmingm@nvidia.com", "date": "2022-09-23T14:43:24", "name": "[17/27] net/mlx5: add pattern and table attribute validation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d87a80ab2cd14c9a8a9d4a48c20181f2c58fc494", "submitter": { "id": 1887, "url": "https://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220923144334.27736-18-suanmingm@nvidia.com/mbox/", "series": [ { "id": 24805, "url": "https://patches.dpdk.org/api/series/24805/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=24805", "date": "2022-09-23T14:43:07", "name": "net/mlx5: HW steering PMD update", "version": 1, "mbox": "https://patches.dpdk.org/series/24805/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/116755/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/116755/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 17DE8A054A;\n\tFri, 23 Sep 2022 16:46:34 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 436FD42C18;\n\tFri, 23 Sep 2022 16:44:41 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40])\n by mails.dpdk.org (Postfix) with ESMTP id C55B342C0D\n for <dev@dpdk.org>; Fri, 23 Sep 2022 16:44:39 +0200 (CEST)", "from MW4PR03CA0227.namprd03.prod.outlook.com (2603:10b6:303:b9::22)\n by CH2PR12MB4071.namprd12.prod.outlook.com (2603:10b6:610:7b::16)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.20; Fri, 23 Sep\n 2022 14:44:37 +0000", "from CO1NAM11FT026.eop-nam11.prod.protection.outlook.com\n (2603:10b6:303:b9:cafe::a8) by MW4PR03CA0227.outlook.office365.com\n (2603:10b6:303:b9::22) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.20 via Frontend\n Transport; Fri, 23 Sep 2022 14:44:37 +0000", "from mail.nvidia.com (216.228.117.161) by\n CO1NAM11FT026.mail.protection.outlook.com (10.13.175.67) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.5654.14 via Frontend Transport; Fri, 23 Sep 2022 14:44:37 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 23 Sep\n 2022 07:44:19 -0700", "from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 23 Sep\n 2022 07:44:18 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=Px3dKEugVBaeOSSBBrHwyqq8jyFdMIVc5xquEhUAYEZ4/4Hm9g5rREQOYEfM+ZManmRZcN6e7EJWlX7SgawGRNbllrHWNdkhw89sTKymNnI4RTyJqQnX76nLRP11s5CMrdFA/14a9ubBI7U9un8qoFBB1TDm6ZwlfxHRwYLEdx0aT5NeMvpFcu6VePQOA/7Da/HLr2wAoSYBl6fzVQOU3sT66REOgGbmlJ27v1I4Eigh6G7h4EDOih2VTqgDNdWHtBfEwlYGyDuInMTzqq06Kn5jhDNgiFQXXQxfci/igmfTQ7l0k4eqd2xIBqzgM+lTS+QeIn4aFbKtvXOUSW4HMA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=F71ghNs8KQUyvk7+8WEoACTT34XlaLCOz0GVovVyO3g=;\n b=WOqFWZ7urkIDj78dnTzUvqwkFyFpTTixlPV9SKzhTciosTWKT/fZJTve/A0VKdaHUeZTy5+BhETVqe+vSYtEhcrTeAjCAOiWQ8pxa5pSMaYY+qCDwcjgy58WpVRe5209EQB3hbvtTyLqeaeTkPN6SDxRKRCdF0Uf3jzaIl9tc/LkjIp2ZRbCfBZntTznwM982rhAdn/r4IwHikAo3PJy+QdRjAegz2dWOA/80ouJHmaNd7zZNNC0mpTodUkW5PN9HrSDnSu12/LKAjAgBTlB4caap1PZGqfHJKSurN27ujjkH4+xeaCOGAKnP2GB/AkOFYEVyi7MeM5mxWIohnqQow==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=F71ghNs8KQUyvk7+8WEoACTT34XlaLCOz0GVovVyO3g=;\n b=bPAKxlbnTmYPCt7tMNXF0b17MLT5YXIvTcUbzwrAQW0712KIW1ryRvL3Xt6ZBqUk5XXQDBmd3MneQw9sp4t9YLARDLkBaePIu+FcCzZFkjYrvTw7A8jwoyOsQ3M92Lts94SUX2OPqIdlKWJZRLbi+STXYnHyfH1Au+6VaEZBzbvqgA+HN/qsip4F4edVaP9nUeDGg9WI9uxzOYZc4lKr0PlTTblqvjc1EEhbH37rbGBME1/YZq/osVw+P5BoZcavyvlPlwzrqcCpC4yxgrzwbqADeZV4k7jzj71pLRr/zkf2pa06HTy0sXTD8w2QqFT3Cj/eUxHqmZVGy6gIFx34Qg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>, Dariusz Sosnowski <dsosnowski@nvidia.com>", "Subject": "[PATCH 17/27] net/mlx5: add pattern and table attribute validation", "Date": "Fri, 23 Sep 2022 17:43:24 +0300", "Message-ID": "<20220923144334.27736-18-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220923144334.27736-1-suanmingm@nvidia.com>", "References": "<20220923144334.27736-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT026:EE_|CH2PR12MB4071:EE_", "X-MS-Office365-Filtering-Correlation-Id": "0824ef34-d9de-43ba-ae0c-08da9d7223be", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n X/ADU2shSYEHtVNEumEHvgFxgixBHaaWfjhk1XE0CFui5t/vXF6S2Z8JYegooETYRk7FE3zVd85XdlNUkSryBZ1mm6p55Xo0/tFxZdvNjW4NwdSYJtSKu+S/c/aneO8D0fCSAaRhUYbseJlnUTKfiLP9uk3uN6zKD4aEGUviRTD0YUnoWEtA5aUaFqvWVSJD/oXmCB4R5aNvVA7QP4DPCBoRCe38mkvlIemqknuElR1gpJqeJPmPfEcIx72PtReSoR8i3MEAAy0cqoSvl8kcP5g3hLvK9dloS2J/nYHqW38b85T3aYuhYIZXSAYUwiub0YuTGAtGBWK8qbf4tc5P8ua9FGr3KSv9pvRCok/f1P2aEnkCudyetjNgoBE/Byz4AI6vBE+pmHb7gXTjHZdg93x1nQd2Us4fmhBRtnDG4eLLjEE9IFhNJRUDOm9c1mflPz6VP3XuqJvQVk2FjlemNWISGcjRyhqxNfxDI2MUrd0DWz54CsrrOkqtN1tw74WA7T9/oPDPDZ9lhnb/ulWwWqNrXscF8YaqwgYaWqG3BRBNIVVyE1HCYoziJi2LWWmjG75nSuew/+W2HLmpokacWAUvouZ9BCaXmwKK0nOFCWxjGhEbvi8QfXATQohUrFuRu3Lr6LGeIVvfjEksN1peydw+xWmr8K7EmjC2ROfuJr+PtGkDWtwy7ipEVGPVzd2d8gU+x+qVSrU7nQFP2DY/bFdzmUi5DLxJZeTBWq9lNwUqv9bir/mBBmHQ3u8UGKd8BQD/ZuNyRN/6coyLtQ55xQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(376002)(136003)(396003)(39860400002)(346002)(451199015)(46966006)(36840700001)(40470700004)(36860700001)(26005)(6636002)(107886003)(36756003)(2906002)(7696005)(110136005)(54906003)(6666004)(2616005)(1076003)(16526019)(86362001)(186003)(4326008)(70586007)(70206006)(83380400001)(336012)(426003)(8676002)(55016003)(6286002)(316002)(41300700001)(40480700001)(47076005)(8936002)(5660300002)(7636003)(478600001)(40460700003)(82740400003)(82310400005)(356005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Sep 2022 14:44:37.6315 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0824ef34-d9de-43ba-ae0c-08da9d7223be", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT026.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB4071", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Dariusz Sosnowski <dsosnowski@nvidia.com>\n\nThis patch adds validation of direction attributes of pattern templates\nand template tables.\n\nIn case of pattern templates the following configurations are allowed\n(and if this configuration requires addition of implicit pattern items):\n\n1. If E-Switch is enabled (i.e. dv_esw_en devarg is set to 1):\n 1. If a port is a VF/SF representor:\n 1. Ingress only - implicit pattern items are added.\n 2. Egress only - implicit pattern items are added.\n 2. If a port is a transfer proxy port (E-Switch Manager/PF\n representor):\n 1. Ingress, egress and transfer - no implicit items are added.\n This setting is useful for applications which require to\n receive traffic from devices connected to the E-Switch and\n did not hit any transfer flow rules.\n 2. Ingress only - implicit pattern items are added.\n 3. Egress only - implicit pattern items are added.\n 4. Transfer only - no implicit pattern items are added.\n2. If E-Switch is disabled (i.e. dv_esw_en devarg is set to 0):\n 1. Ingress only - no implicit pattern items are added.\n 2. Egress only - no implicit pattern items are added.\n 3. Ingress and egress - no implicit pattern items are added.\n 4. Transfer is not allowed.\n\nIn case of template tables, the table attributes must be consistent\nwith attributes associated with pattern template attributes.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_hw.c | 80 +++++++++++++++++++++++++--------\n 1 file changed, 62 insertions(+), 18 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 92b61b63d1..dfbc434d54 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -2379,6 +2379,13 @@ flow_hw_table_create(struct rte_eth_dev *dev,\n \tfor (i = 0; i < nb_item_templates; i++) {\n \t\tuint32_t ret;\n \n+\t\tif ((flow_attr.ingress && !item_templates[i]->attr.ingress) ||\n+\t\t (flow_attr.egress && !item_templates[i]->attr.egress) ||\n+\t\t (flow_attr.transfer && !item_templates[i]->attr.transfer)) {\n+\t\t\tDRV_LOG(ERR, \"pattern template and template table attribute mismatch\");\n+\t\t\trte_errno = EINVAL;\n+\t\t\tgoto it_error;\n+\t\t}\n \t\tret = __atomic_add_fetch(&item_templates[i]->refcnt, 1,\n \t\t\t\t\t __ATOMIC_RELAXED);\n \t\tif (ret <= 1) {\n@@ -2557,6 +2564,7 @@ flow_hw_template_table_create(struct rte_eth_dev *dev,\n \t\t\t uint8_t nb_action_templates,\n \t\t\t struct rte_flow_error *error)\n {\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_flow_template_table_cfg cfg = {\n \t\t.attr = *attr,\n \t\t.external = true,\n@@ -2565,6 +2573,12 @@ flow_hw_template_table_create(struct rte_eth_dev *dev,\n \n \tif (flow_hw_translate_group(dev, &cfg, group, &cfg.attr.flow_attr.group, error))\n \t\treturn NULL;\n+\tif (priv->sh->config.dv_esw_en && cfg.attr.flow_attr.egress) {\n+\t\trte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL,\n+\t\t\t\t \"egress flows are not supported with HW Steering\"\n+\t\t\t\t \" when E-Switch is enabled\");\n+\t\treturn NULL;\n+\t}\n \treturn flow_hw_table_create(dev, &cfg, item_templates, nb_item_templates,\n \t\t\t\t action_templates, nb_action_templates, error);\n }\n@@ -3254,11 +3268,48 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\t\t const struct rte_flow_item items[],\n \t\t\t struct rte_flow_error *error)\n {\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n \tint i;\n \tbool items_end = false;\n-\tRTE_SET_USED(dev);\n-\tRTE_SET_USED(attr);\n \n+\tif (!attr->ingress && !attr->egress && !attr->transfer)\n+\t\treturn rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL,\n+\t\t\t\t\t \"at least one of the direction attributes\"\n+\t\t\t\t\t \" must be specified\");\n+\tif (priv->sh->config.dv_esw_en) {\n+\t\tMLX5_ASSERT(priv->master || priv->representor);\n+\t\tif (priv->master) {\n+\t\t\t/*\n+\t\t\t * It is allowed to specify ingress, egress and transfer attributes\n+\t\t\t * at the same time, in order to construct flows catching all missed\n+\t\t\t * FDB traffic and forwarding it to the master port.\n+\t\t\t */\n+\t\t\tif (!(attr->ingress ^ attr->egress ^ attr->transfer))\n+\t\t\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ATTR, NULL,\n+\t\t\t\t\t\t\t \"only one or all direction attributes\"\n+\t\t\t\t\t\t\t \" at once can be used on transfer proxy\"\n+\t\t\t\t\t\t\t \" port\");\n+\t\t} else {\n+\t\t\tif (attr->transfer)\n+\t\t\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL,\n+\t\t\t\t\t\t\t \"transfer attribute cannot be used with\"\n+\t\t\t\t\t\t\t \" port representors\");\n+\t\t\tif (attr->ingress && attr->egress)\n+\t\t\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ATTR, NULL,\n+\t\t\t\t\t\t\t \"ingress and egress direction attributes\"\n+\t\t\t\t\t\t\t \" cannot be used at the same time on\"\n+\t\t\t\t\t\t\t \" port representors\");\n+\t\t}\n+\t} else {\n+\t\tif (attr->transfer)\n+\t\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL,\n+\t\t\t\t\t\t \"transfer attribute cannot be used when\"\n+\t\t\t\t\t\t \" E-Switch is disabled\");\n+\t}\n \tfor (i = 0; !items_end; i++) {\n \t\tint type = items[i].type;\n \n@@ -3289,7 +3340,15 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t\t\t\t NULL,\n \t\t\t\t\t\t\t \"Unsupported internal tag index\");\n+\t\t\tbreak;\n \t\t}\n+\t\tcase RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:\n+\t\t\tif (attr->ingress || attr->egress)\n+\t\t\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, NULL,\n+\t\t\t\t\t\t \"represented port item cannot be used\"\n+\t\t\t\t\t\t \" when transfer attribute is set\");\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_VOID:\n \t\tcase RTE_FLOW_ITEM_TYPE_ETH:\n \t\tcase RTE_FLOW_ITEM_TYPE_VLAN:\n@@ -3299,7 +3358,6 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ITEM_TYPE_TCP:\n \t\tcase RTE_FLOW_ITEM_TYPE_GTP:\n \t\tcase RTE_FLOW_ITEM_TYPE_GTP_PSC:\n-\t\tcase RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:\n \t\tcase RTE_FLOW_ITEM_TYPE_VXLAN:\n \t\tcase MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:\n \t\tcase RTE_FLOW_ITEM_TYPE_META:\n@@ -3350,21 +3408,7 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev,\n \n \tif (flow_hw_pattern_validate(dev, attr, items, error))\n \t\treturn NULL;\n-\tif (priv->sh->config.dv_esw_en && attr->ingress) {\n-\t\t/*\n-\t\t * Disallow pattern template with ingress and egress/transfer\n-\t\t * attributes in order to forbid implicit port matching\n-\t\t * on egress and transfer traffic.\n-\t\t */\n-\t\tif (attr->egress || attr->transfer) {\n-\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t\t\t NULL,\n-\t\t\t\t\t \"item template for ingress traffic\"\n-\t\t\t\t\t \" cannot be used for egress/transfer\"\n-\t\t\t\t\t \" traffic when E-Switch is enabled\");\n-\t\t\treturn NULL;\n-\t\t}\n+\tif (priv->sh->config.dv_esw_en && attr->ingress && !attr->egress && !attr->transfer) {\n \t\tcopied_items = flow_hw_copy_prepend_port_item(items, error);\n \t\tif (!copied_items)\n \t\t\treturn NULL;\n", "prefixes": [ "17/27" ] }