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GET /api/patches/1167/?format=api
https://patches.dpdk.org/api/patches/1167/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1415283932-20724-9-git-send-email-helin.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1415283932-20724-9-git-send-email-helin.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1415283932-20724-9-git-send-email-helin.zhang@intel.com", "date": "2014-11-06T14:25:32", "name": "[dpdk-dev,v5,8/8] i40evf: support of updating/querying redirection table", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0958abd0af47ef1e71094601bd39afd0386e28bb", "submitter": { "id": 14, "url": "https://patches.dpdk.org/api/people/14/?format=api", "name": "Zhang, Helin", "email": "helin.zhang@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1415283932-20724-9-git-send-email-helin.zhang@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/1167/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/1167/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 20A5D7F35;\n\tThu, 6 Nov 2014 15:16:32 +0100 (CET)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id 09E427F18\n\tfor <dev@dpdk.org>; Thu, 6 Nov 2014 15:16:29 +0100 (CET)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga103.jf.intel.com with ESMTP; 06 Nov 2014 06:23:51 -0800", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga001.jf.intel.com with ESMTP; 06 Nov 2014 06:25:56 -0800", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id sA6EPrPC003525;\n\tThu, 6 Nov 2014 22:25:53 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid sA6EPprj020815; Thu, 6 Nov 2014 22:25:53 +0800", "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id sA6EPpf3020811; \n\tThu, 6 Nov 2014 22:25:51 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.07,326,1413270000\"; d=\"scan'208\";a=\"603474086\"", "From": "Helin Zhang <helin.zhang@intel.com>", "To": "dev@dpdk.org", "Date": "Thu, 6 Nov 2014 22:25:32 +0800", "Message-Id": "<1415283932-20724-9-git-send-email-helin.zhang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1415283932-20724-1-git-send-email-helin.zhang@intel.com>", "References": "<1414746215-17327-1-git-send-email-helin.zhang@intel.com>\n\t<1415283932-20724-1-git-send-email-helin.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 8/8] i40evf: support of updating/querying\n\tredirection table", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Support of updating/querying redirection table has been added for VF.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\n---\n lib/librte_pmd_i40e/i40e_ethdev_vf.c | 99 ++++++++++++++++++++++++++++++++++--\n 1 file changed, 94 insertions(+), 5 deletions(-)\n\nv2 changes:\n* Add support of updating/querying i40e reta of VF.\n\nv4 changes:\n* Renamed RTE_BIT_WIDTH_64 to RTE_RETA_GROUP_SIZE.", "diff": "diff --git a/lib/librte_pmd_i40e/i40e_ethdev_vf.c b/lib/librte_pmd_i40e/i40e_ethdev_vf.c\nindex 3e64666..03bc28e 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev_vf.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev_vf.c\n@@ -126,11 +126,6 @@ static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);\n static int i40evf_get_link_status(struct rte_eth_dev *dev,\n \t\t\t\t struct rte_eth_link *link);\n static int i40evf_init_vlan(struct rte_eth_dev *dev);\n-static int i40evf_config_rss(struct i40e_vf *vf);\n-static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,\n-\t\t\t\t struct rte_eth_rss_conf *rss_conf);\n-static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n-\t\t\t\t\tstruct rte_eth_rss_conf *rss_conf);\n static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,\n \t\t\t\t uint16_t rx_queue_id);\n static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,\n@@ -139,6 +134,17 @@ static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,\n \t\t\t\t uint16_t tx_queue_id);\n static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,\n \t\t\t\t uint16_t tx_queue_id);\n+static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,\n+\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\tuint16_t reta_size);\n+static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,\n+\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\tuint16_t reta_size);\n+static int i40evf_config_rss(struct i40e_vf *vf);\n+static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_eth_rss_conf *rss_conf);\n+static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n+\t\t\t\t\tstruct rte_eth_rss_conf *rss_conf);\n \n /* Default hash key buffer for RSS */\n static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];\n@@ -166,6 +172,8 @@ static struct eth_dev_ops i40evf_eth_dev_ops = {\n \t.rx_queue_release = i40e_dev_rx_queue_release,\n \t.tx_queue_setup = i40e_dev_tx_queue_setup,\n \t.tx_queue_release = i40e_dev_tx_queue_release,\n+\t.reta_update = i40evf_dev_rss_reta_update,\n+\t.reta_query = i40evf_dev_rss_reta_query,\n \t.rss_hash_update = i40evf_dev_rss_hash_update,\n \t.rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,\n };\n@@ -1611,6 +1619,87 @@ i40evf_dev_close(struct rte_eth_dev *dev)\n }\n \n static int\n+i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t uint16_t reta_size)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint32_t lut, l;\n+\tuint16_t i, j;\n+\tuint16_t idx, shift;\n+\tuint8_t mask;\n+\n+\tif (reta_size != ETH_RSS_RETA_SIZE_64) {\n+\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n+\t\t\t\"(%d) doesn't match the number of hardware can\"\n+\t\t\t\"support (%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_64);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {\n+\t\tidx = i / RTE_RETA_GROUP_SIZE;\n+\t\tshift = i % RTE_RETA_GROUP_SIZE;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n+\t\t\t\t\t\tI40E_4_BIT_MASK);\n+\t\tif (!mask)\n+\t\t\tcontinue;\n+\t\tif (mask == I40E_4_BIT_MASK)\n+\t\t\tl = 0;\n+\t\telse\n+\t\t\tl = I40E_READ_REG(hw, I40E_VFQF_HLUT(i >> 2));\n+\n+\t\tfor (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {\n+\t\t\tif (mask & (0x1 << j))\n+\t\t\t\tlut |= reta_conf[idx].reta[shift + j] <<\n+\t\t\t\t\t\t\t(CHAR_BIT * j);\n+\t\t\telse\n+\t\t\t\tlut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));\n+\t\t}\n+\t\tI40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t uint16_t reta_size)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint32_t lut;\n+\tuint16_t i, j;\n+\tuint16_t idx, shift;\n+\tuint8_t mask;\n+\n+\tif (reta_size != ETH_RSS_RETA_SIZE_64) {\n+\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n+\t\t\t\"(%d) doesn't match the number of hardware can\"\n+\t\t\t\"support (%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_64);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {\n+\t\tidx = i / RTE_RETA_GROUP_SIZE;\n+\t\tshift = i % RTE_RETA_GROUP_SIZE;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n+\t\t\t\t\t\tI40E_4_BIT_MASK);\n+\t\tif (!mask)\n+\t\t\tcontinue;\n+\n+\t\tlut = I40E_READ_REG(hw, I40E_VFQF_HLUT(i >> 2));\n+\t\tfor (j = 0; j < I40E_4_BIT_WIDTH; j++) {\n+\t\t\tif (mask & (0x1 << j))\n+\t\t\t\treta_conf[idx].reta[shift] =\n+\t\t\t\t\t((lut >> (CHAR_BIT * j)) &\n+\t\t\t\t\t\tI40E_8_BIT_MASK);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n i40evf_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)\n {\n \tuint32_t *hash_key;\n", "prefixes": [ "dpdk-dev", "v5", "8/8" ] }{ "id": 1167, "url": "