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GET /api/patches/116583/?format=api
{ "id": 116583, "url": "https://patches.dpdk.org/api/patches/116583/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220921152957.733863-1-abdullah.sevincer@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220921152957.733863-1-abdullah.sevincer@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220921152957.733863-1-abdullah.sevincer@intel.com", "date": "2022-09-21T15:29:57", "name": "[v1] event/dlb2: fix max cq_depth/enq_depth cli override", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "141d6edf21d72dec960e3904107d539c3ab2db64", "submitter": { "id": 2843, "url": "https://patches.dpdk.org/api/people/2843/?format=api", "name": "Sevincer, Abdullah", "email": "abdullah.sevincer@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220921152957.733863-1-abdullah.sevincer@intel.com/mbox/", "series": [ { "id": 24758, "url": "https://patches.dpdk.org/api/series/24758/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=24758", "date": "2022-09-21T15:29:57", "name": "[v1] event/dlb2: fix max cq_depth/enq_depth cli override", "version": 1, "mbox": "https://patches.dpdk.org/series/24758/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/116583/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/116583/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 20FDAA00C3;\n\tWed, 21 Sep 2022 17:30:08 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id F3D5740691;\n\tWed, 21 Sep 2022 17:30:07 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 6A8D74067C\n for <dev@dpdk.org>; Wed, 21 Sep 2022 17:30:06 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Sep 2022 08:30:05 -0700", "from txanpdk02.an.intel.com ([10.123.117.76])\n by orsmga008.jf.intel.com with ESMTP; 21 Sep 2022 08:30:04 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1663774206; x=1695310206;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=reGO35qZV6Plf7RAF6oJNjy9L6mb6C8mBWTTy2NQfvo=;\n b=Opy9o3uFUc8HbvTunf1gwevSVLE0M8GKBIMweF77kmn7LRcf1eVl8f9d\n 9o8//DhpwWv5xGd3RY7l00DfEr3PeQ3b8RtIs7Cvxl4GTXIESnKAkGDiU\n qwI2TO9mCEZbAghPW4GFRvx170l3fPdw8HDot2E6anJElW7Du6wINHVf9\n 0ZV2Cte9cbeNvzUM4oA2O1aVfpE0FcVMLdEVy9B4nHHjOYolITWqgbbU+\n ErCp/ISn8LJy1/lIIEZNSjmoZN9jQtf4Hw8F7qvnkibCYV5jKRpkz7UEy\n lJ3VR+cd+2KeULHo/b+uzxAG7pr7SLA15AOcCdXlCYI7FsQX8mhB+kAoS Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10477\"; a=\"287108920\"", "E=Sophos;i=\"5.93,333,1654585200\"; d=\"scan'208\";a=\"287108920\"", "E=Sophos;i=\"5.93,333,1654585200\"; d=\"scan'208\";a=\"650119578\"" ], "X-ExtLoop1": "1", "From": "Abdullah Sevincer <abdullah.sevincer@intel.com>", "To": "dev@dpdk.org", "Cc": "jerinj@marvell.com, rashmi.shetty@intel.com, pravin.pathak@intel.com,\n mike.ximing.chen@intel.com, timothy.mcdaniel@intel.com,\n shivani.doneria@intel.com, tirthendu.sarkar@intel.com,\n Abdullah Sevincer <abdullah.sevincer@intel.com>", "Subject": "[PATCH v1] event/dlb2: fix max cq_depth/enq_depth cli override", "Date": "Wed, 21 Sep 2022 10:29:57 -0500", "Message-Id": "<20220921152957.733863-1-abdullah.sevincer@intel.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch addresses an issue of enqueuing more than\nmax_enq_depth and not able to dequeuing events equal\nto max_cq_depth in a single call of rte_event_enqueue_burst\nand rte_event_dequeue_burst.\n\nApply fix for restricting enqueue of events to max_enq_depth\nso that in a single rte_event_enqueue_burst() call at most\nmax_enq_depth events are enqueued.\n\nAlso set per port and domain history list sizes based on\ncq_depth. This results in dequeing correct number of\nevents as set by max_cq_depth.\n\nSigned-off-by: Abdullah Sevincer <abdullah.sevincer@intel.com>\n---\n drivers/event/dlb2/dlb2.c | 9 +++++----\n 1 file changed, 5 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex 5a443acff8..e8c21c41fd 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -813,7 +813,7 @@ dlb2_hw_create_sched_domain(struct dlb2_eventdev *dlb2,\n \t\tcfg->num_ldb_queues;\n \n \tcfg->num_hist_list_entries = resources_asked->num_ldb_ports *\n-\t\tDLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;\n+\t\tevdev_dlb2_default_info.max_event_port_dequeue_depth;\n \n \tif (device_version == DLB2_HW_V2_5) {\n \t\tDLB2_LOG_DBG(\"sched domain create - ldb_qs=%d, ldb_ports=%d, dir_ports=%d, atomic_inflights=%d, hist_list_entries=%d, credits=%d\\n\",\n@@ -1538,7 +1538,7 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,\n \tcfg.cq_depth = rte_align32pow2(dequeue_depth);\n \tcfg.cq_depth_threshold = 1;\n \n-\tcfg.cq_history_list_size = DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;\n+\tcfg.cq_history_list_size = cfg.cq_depth;\n \n \tcfg.cos_id = ev_port->cos_id;\n \tcfg.cos_strict = 0;/* best effots */\n@@ -2966,6 +2966,7 @@ __dlb2_event_enqueue_burst(void *event_port,\n \tstruct dlb2_port *qm_port = &ev_port->qm_port;\n \tstruct process_local_port_data *port_data;\n \tint retries = ev_port->enq_retries;\n+\tint num_tx;\n \tint i;\n \n \tRTE_ASSERT(ev_port->enq_configured);\n@@ -2974,8 +2975,8 @@ __dlb2_event_enqueue_burst(void *event_port,\n \ti = 0;\n \n \tport_data = &dlb2_port[qm_port->id][PORT_TYPE(qm_port)];\n-\n-\twhile (i < num) {\n+\tnum_tx = RTE_MIN(num, ev_port->conf.enqueue_depth);\n+\twhile (i < num_tx) {\n \t\tuint8_t sched_types[DLB2_NUM_QES_PER_CACHE_LINE];\n \t\tuint8_t queue_ids[DLB2_NUM_QES_PER_CACHE_LINE];\n \t\tint pop_offs = 0;\n", "prefixes": [ "v1" ] }