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GET /api/patches/116439/?format=api
{ "id": 116439, "url": "https://patches.dpdk.org/api/patches/116439/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220919163731.1540454-2-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220919163731.1540454-2-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220919163731.1540454-2-dsosnowski@nvidia.com", "date": "2022-09-19T16:37:24", "name": "[1/7] ethdev: introduce hairpin memory capabilities", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "75a9bfcaa8c4d72bf77d683493fd2b57de09d0d9", "submitter": { "id": 2386, "url": "https://patches.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220919163731.1540454-2-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 24715, "url": "https://patches.dpdk.org/api/series/24715/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=24715", "date": "2022-09-19T16:37:23", "name": "ethdev: introduce hairpin memory capabilities", "version": 1, "mbox": "https://patches.dpdk.org/series/24715/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/116439/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/116439/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 795DEA00C3;\n\tMon, 19 Sep 2022 18:39:02 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 669A541148;\n\tMon, 19 Sep 2022 18:39:02 +0200 (CEST)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2067.outbound.protection.outlook.com [40.107.220.67])\n by mails.dpdk.org (Postfix) with ESMTP id 6BC5A41145\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Thomas Monjalon <thomas@monjalon.net>, Ferruh Yigit\n <ferruh.yigit@xilinx.com>, Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 1/7] ethdev: introduce hairpin memory capabilities", "Date": "Mon, 19 Sep 2022 16:37:24 +0000", "Message-ID": "<20220919163731.1540454-2-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220919163731.1540454-1-dsosnowski@nvidia.com>", "References": "<20220919163731.1540454-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT093:EE_|PH8PR12MB7027:EE_", "X-MS-Office365-Filtering-Correlation-Id": "6ec2470a-e5a1-4890-2082-08da9a5d737a", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n etKxYgXKdg3wMlt0x1ZtA/bA80fBOOSmtpG2ciSrU3lljAOS+wfygvArPGoBNUnU4SHRAk5BAwJK3o/8zdWvYAtE51kJ87PVH+P1gFX9Hr7CYbf4VtA8+saSFgyyp48MUKGWKPxczvkx5m+ycn/HolEfAiaGTeIazvEi2pV22EJTd4Bj/BZyUgVh8FUgRGzSLmEvtdnkOjpnh8bML21SKDrhWVF+ChlGuDgEgfoMVyUKWOvTBLuJwLbXunU+NH8HmoVTWT2xhhvO+hY52xwRJ5QhbrSqb7RJwvjq/yqLaD/SXrlvm4qtV3u6mCoFpkRZKmEOLukOJqaWb/OhZcJmp+d6gKuyhdDKrmnuEM575+zDk8P9TIdoU6NSFYq0/qBnPPkVhyGIiBhfhQNBi60NyhWAJkZJ4EuAgastI18FThgLRaaw3oriLSGhYAGntoS4YKzyitNdNZeUsPjE+Tut9dwNfvtdBgG8g4j1+74ywpnEb2cTemF250j5O7TY81VrkUIInr+9Q67uXKeNIknPCCeLN+OLSObryUqX62jZpU6Nc2IaxQLqM3PaJs4sdC/LcbWYqd4+soU/F8dIPCOq5dvUP3pGp55XEEQR8u4YUsOinnqgxghw1+/obyv3m1dl/LQUTHbp0Ce58+wmCxPk2zq7q+0Uq24Xp10CnnMyDHKfvr0NOqUV8u2BuWdKxhGySn58ZYDTzeX1HT0oWFndaidu7J0ZGBiz7NSofeCB+Uv0jY5NZ0cJgWg91kU+I8BnOYzc7rHm0unjJ1Ff9woA1IgALzY/FwXDJ1+3c9Ouj0fXRl3OQXyOqOe+YUyeCwfw", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(396003)(346002)(376002)(39860400002)(136003)(451199015)(40470700004)(36840700001)(46966006)(2906002)(8936002)(36756003)(7636003)(356005)(82740400003)(47076005)(86362001)(36860700001)(82310400005)(83380400001)(7696005)(6286002)(6666004)(55016003)(426003)(1076003)(2616005)(26005)(186003)(40460700003)(16526019)(336012)(70586007)(110136005)(5660300002)(4326008)(478600001)(70206006)(8676002)(316002)(40480700001)(41300700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Sep 2022 16:38:58.4803 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6ec2470a-e5a1-4890-2082-08da9a5d737a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT093.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH8PR12MB7027", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch introduces new hairpin queue configuration options through\nrte_eth_hairpin_conf struct, allowing to tune Rx and Tx hairpin queues\nmemory configuration. Hairpin configuration is extended with the\nfollowing fields:\n\n- use_locked_device_memory - If set, PMD will use specialized on-device\n memory to store RX or TX hairpin queue data.\n- use_rte_memory - If set, PMD will use DPDK-managed memory to store RX\n or TX hairpin queue data.\n- force_memory - If set, PMD will be forced to use provided memory\n settings. If no appropriate resources are available, then device start\n will fail. If unset and no resources are available, PMD will fallback\n to using default type of resource for given queue.\n\nHairpin capabilities are also extended, to allow verification of support\nof given hairpin memory configurations. Struct rte_eth_hairpin_cap is\nextended with two additional fields of type rte_eth_hairpin_queue_cap:\n\n- rx_cap - memory capabilities of hairpin RX queues.\n- tx_cap - memory capabilities of hairpin TX queues.\n\nStruct rte_eth_hairpin_queue_cap exposes whether given queue type\nsupports use_locked_device_memory and use_rte_memory flags.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n lib/ethdev/rte_ethdev.c | 44 ++++++++++++++++++++++++++++\n lib/ethdev/rte_ethdev.h | 65 ++++++++++++++++++++++++++++++++++++++++-\n 2 files changed, 108 insertions(+), 1 deletion(-)", "diff": "diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c\nindex 1979dc0850..edcec08231 100644\n--- a/lib/ethdev/rte_ethdev.c\n+++ b/lib/ethdev/rte_ethdev.c\n@@ -1945,6 +1945,28 @@ rte_eth_rx_hairpin_queue_setup(uint16_t port_id, uint16_t rx_queue_id,\n \t\t\tconf->peer_count, cap.max_rx_2_tx);\n \t\treturn -EINVAL;\n \t}\n+\tif (conf->use_locked_device_memory && !cap.rx_cap.locked_device_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to use locked device memory for Rx queue, which is not supported\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (conf->use_rte_memory && !cap.rx_cap.rte_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to use DPDK memory for Rx queue, which is not supported\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (conf->use_locked_device_memory && conf->use_rte_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to use mutually exclusive memory settings for Rx queue\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (conf->force_memory &&\n+\t !conf->use_locked_device_memory &&\n+\t !conf->use_rte_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to force Rx queue memory settings, but none is set\");\n+\t\treturn -EINVAL;\n+\t}\n \tif (conf->peer_count == 0) {\n \t\tRTE_ETHDEV_LOG(ERR,\n \t\t\t\"Invalid value for number of peers for Rx queue(=%u), should be: > 0\",\n@@ -2111,6 +2133,28 @@ rte_eth_tx_hairpin_queue_setup(uint16_t port_id, uint16_t tx_queue_id,\n \t\t\tconf->peer_count, cap.max_tx_2_rx);\n \t\treturn -EINVAL;\n \t}\n+\tif (conf->use_locked_device_memory && !cap.tx_cap.locked_device_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to use locked device memory for Tx queue, which is not supported\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (conf->use_rte_memory && !cap.tx_cap.rte_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to use DPDK memory for Tx queue, which is not supported\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (conf->use_locked_device_memory && conf->use_rte_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to use mutually exclusive memory settings for Tx queue\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (conf->force_memory &&\n+\t !conf->use_locked_device_memory &&\n+\t !conf->use_rte_memory) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Attempt to force Tx queue memory settings, but none is set\");\n+\t\treturn -EINVAL;\n+\t}\n \tif (conf->peer_count == 0) {\n \t\tRTE_ETHDEV_LOG(ERR,\n \t\t\t\"Invalid value for number of peers for Tx queue(=%u), should be: > 0\",\ndiff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h\nindex de9e970d4d..e179b0e79b 100644\n--- a/lib/ethdev/rte_ethdev.h\n+++ b/lib/ethdev/rte_ethdev.h\n@@ -1273,6 +1273,28 @@ struct rte_eth_txconf {\n \tvoid *reserved_ptrs[2]; /**< Reserved for future fields */\n };\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * A structure used to return the Tx or Rx hairpin queue capabilities that are supported.\n+ */\n+struct rte_eth_hairpin_queue_cap {\n+\t/**\n+\t * When set, a specialized on-device memory type can be used as a backing\n+\t * storage for a given hairpin queue type.\n+\t */\n+\tuint32_t locked_device_memory:1;\n+\n+\t/**\n+\t * When set, memory managed by DPDK can be used as a backing storage\n+\t * for a given hairpin queue type.\n+\t */\n+\tuint32_t rte_memory:1;\n+\n+\tuint32_t reserved:30; /**< Reserved for future fields */\n+};\n+\n /**\n * @warning\n * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n@@ -1287,6 +1309,8 @@ struct rte_eth_hairpin_cap {\n \t/** Max number of Tx queues to be connected to one Rx queue. */\n \tuint16_t max_tx_2_rx;\n \tuint16_t max_nb_desc; /**< The max num of descriptors. */\n+\tstruct rte_eth_hairpin_queue_cap rx_cap; /**< Rx hairpin queue capabilities. */\n+\tstruct rte_eth_hairpin_queue_cap tx_cap; /**< Tx hairpin queue capabilities. */\n };\n \n #define RTE_ETH_MAX_HAIRPIN_PEERS 32\n@@ -1334,7 +1358,46 @@ struct rte_eth_hairpin_conf {\n \t * configured automatically during port start.\n \t */\n \tuint32_t manual_bind:1;\n-\tuint32_t reserved:14; /**< Reserved bits. */\n+\n+\t/**\n+\t * Use locked device memory as a backing storage.\n+\t *\n+\t * - When set, PMD will attempt to use on-device memory as a backing storage for descriptors\n+\t * and/or data in hairpin queue.\n+\t * - When set, PMD will use detault memory type as a backing storage. Please refer to PMD\n+\t * documentation for details.\n+\t *\n+\t * API user should check if PMD supports this configuration flag using\n+\t * @see rte_eth_dev_hairpin_capability_get.\n+\t */\n+\tuint32_t use_locked_device_memory:1;\n+\n+\t/**\n+\t * Use DPDK memory as backing storage.\n+\t *\n+\t * - When set, PMD will attempt to use memory managed by DPDK as a backing storage\n+\t * for descriptors and/or data in hairpin queue.\n+\t * - When clear, PMD will use default memory type as a backing storage. Please refer\n+\t * to PMD documentation for details.\n+\t *\n+\t * API user should check if PMD supports this configuration flag using\n+\t * @see rte_eth_dev_hairpin_capability_get.\n+\t */\n+\tuint32_t use_rte_memory:1;\n+\n+\t/**\n+\t * Force usage of hairpin memory configuration.\n+\t *\n+\t * - When set, PMD will attempt to use specified memory settings and\n+\t * if resource allocation fails, then hairpin queue setup will result in an\n+\t * error.\n+\t * - When clear, PMD will attempt to use specified memory settings and\n+\t * if resource allocation fails, then PMD will retry allocation with default\n+\t * configuration.\n+\t */\n+\tuint32_t force_memory:1;\n+\n+\tuint32_t reserved:11; /**< Reserved bits. */\n \tstruct rte_eth_hairpin_peer peers[RTE_ETH_MAX_HAIRPIN_PEERS];\n };\n \n", "prefixes": [ "1/7" ] }