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GET /api/patches/116325/?format=api
{ "id": 116325, "url": "https://patches.dpdk.org/api/patches/116325/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220915070732.182542-1-hpothula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220915070732.182542-1-hpothula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220915070732.182542-1-hpothula@marvell.com", "date": "2022-09-15T07:07:30", "name": "[v4,1/3] ethdev: Add support for mulitiple mbuf pools per Rx queue", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "1191f7431cf8d912fe0e1d8ddedb698c0cc8be02", "submitter": { "id": 2319, "url": "https://patches.dpdk.org/api/people/2319/?format=api", "name": "Hanumanth Pothula", "email": "hpothula@marvell.com" }, "delegate": { "id": 3961, "url": "https://patches.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220915070732.182542-1-hpothula@marvell.com/mbox/", "series": [ { "id": 24672, "url": "https://patches.dpdk.org/api/series/24672/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=24672", "date": "2022-09-15T07:07:30", "name": "[v4,1/3] ethdev: Add support for mulitiple mbuf pools per Rx queue", "version": 4, "mbox": "https://patches.dpdk.org/series/24672/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/116325/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/116325/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2169DA00C5;\n\tThu, 15 Sep 2022 09:09:50 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 11A574021D;\n\tThu, 15 Sep 2022 09:09:50 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 54C0440156\n for <dev@dpdk.org>; Thu, 15 Sep 2022 09:09:49 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 28ENmMJv023140;\n Thu, 15 Sep 2022 00:07:42 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3jjy0272xe-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 15 Sep 2022 00:07:42 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 15 Sep 2022 00:07:40 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 15 Sep 2022 00:07:40 -0700", "from localhost.localdomain (unknown [10.28.36.155])\n by maili.marvell.com (Postfix) with ESMTP id ECB4F3F70A2;\n Thu, 15 Sep 2022 00:07:35 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=IhfQqvO7LBU4pQuxD4YZ53Z6lK+xGIyQlnwvCYUTV5M=;\n b=c69ai7c22jjVngs2IVRifZfw50WkJaP7RVQCyZnkJhdiBDGUQXsS5d84VtgsutNyan5y\n DRcE5vEbQpTjiExzwLztPnsq3XdRHR8xEiOoj/RUetz6OsxIPazyVNISDozD3pS106nD\n Hh7cnVXXXLshhp25IbjoU8v3lHY0O1cySczoqSGK6+x0tvkHA4XTPpp/VXLMIGi6OCbc\n Og4MsZbz6PNMsjdUkOA49X3L/uUEsT8LHrErMdK0rcYrViMZ9ZVwfRxb2EouTxDZK350\n DllMOyl0Izw+mDqBK411zh5pmIp/mCTafzyDPCD1yPahBpKM38wTmcgFYW/3S69MkYAT OA==", "From": "Hanumanth Pothula <hpothula@marvell.com>", "To": "Thomas Monjalon <thomas@monjalon.net>, Ferruh Yigit\n <ferruh.yigit@xilinx.com>, Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>", "CC": "<dev@dpdk.org>, <xuan.ding@intel.com>, <wenxuanx.wu@intel.com>,\n <xiaoyun.li@intel.com>, <stephen@networkplumber.org>,\n <yuanx.wang@intel.com>, <mdr@ashroe.eu>, <yuying.zhang@intel.com>,\n <qi.z.zhang@intel.com>, <viacheslavo@nvidia.com>, <jerinj@marvell.com>,\n <ndabilpuram@marvell.com>, Hanumanth Pothula <hpothula@marvell.com>", "Subject": "[PATCH v4 1/3] ethdev: Add support for mulitiple mbuf pools per Rx\n queue", "Date": "Thu, 15 Sep 2022 12:37:30 +0530", "Message-ID": "<20220915070732.182542-1-hpothula@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220902070047.2812906-1-hpothula@marvell.com>", "References": "<20220902070047.2812906-1-hpothula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "8RlTzE4G0B99pR70wgygw7uphDd7-11u", "X-Proofpoint-ORIG-GUID": "8RlTzE4G0B99pR70wgygw7uphDd7-11u", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1\n definitions=2022-09-15_03,2022-09-14_04,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds support for multiple mempool capability.\nSome of the HW has support for choosing memory pools based on the\npacket's size. Thiscapability allows PMD to choose a memory pool\nbased on the packet's length.\n\nThis is often useful for saving the memory where the application\ncan create a different pool to steer the specific size of the\npacket, thus enabling effective use of memory.\n\nFor example, let's say HW has a capability of three pools,\n - pool-1 size is 2K\n - pool-2 size is > 2K and < 4K\n - pool-3 size is > 4K\nHere,\n pool-1 can accommodate packets with sizes < 2K\n pool-2 can accommodate packets with sizes > 2K and < 4K\n pool-3 can accommodate packets with sizes > 4K\n\nWith multiple mempool capability enabled in SW, an application may\ncreate three pools of different sizes and send them to PMD. Allowing\nPMD to program HW based on the packet lengths. So that packets with\nless than 2K are received on pool-1, packets with lengths between 2K\nand 4K are received on pool-2 and finally packets greater than 4K\nare received on pool-3.\n\nSigned-off-by: Hanumanth Pothula <hpothula@marvell.com>\n\nv4:\n - Renamed Offload capability name from RTE_ETH_RX_OFFLOAD_BUFFER_SORT\n to RTE_ETH_RX_OFFLOAD_MUL_MEMPOOL.\n - In struct rte_eth_rxconf, defined new pointer, which holds array of\n type struct rte_eth_rx_mempool(memory pools). This array is used\n by PMD to program multiple mempools.\nv3:\n - Implemented Pool Sort capability as new Rx offload capability,\n RTE_ETH_RX_OFFLOAD_BUFFER_SORT.\nv2:\n - Along with spec changes, uploading testpmd and driver changes.\n---\n lib/ethdev/rte_ethdev.c | 78 ++++++++++++++++++++++++++++++++++-------\n lib/ethdev/rte_ethdev.h | 24 +++++++++++++\n 2 files changed, 89 insertions(+), 13 deletions(-)", "diff": "diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c\nindex 1979dc0850..8618d6b01d 100644\n--- a/lib/ethdev/rte_ethdev.c\n+++ b/lib/ethdev/rte_ethdev.c\n@@ -1634,6 +1634,45 @@ rte_eth_dev_is_removed(uint16_t port_id)\n \treturn ret;\n }\n \n+static int\n+rte_eth_rx_queue_check_mempool(const struct rte_eth_rx_mempool *rx_mempool,\n+\t\t\t uint16_t n_pool, uint32_t *mbp_buf_size,\n+\t\t\t const struct rte_eth_dev_info *dev_info)\n+{\n+\tuint16_t pool_idx;\n+\n+\tif (n_pool > dev_info->max_pools) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t \"Invalid capabilities, max pools supported %u\\n\",\n+\t\t\t dev_info->max_pools);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (pool_idx = 0; pool_idx < n_pool; pool_idx++) {\n+\t\tstruct rte_mempool *mpl = rx_mempool[pool_idx].mp;\n+\n+\t\tif (mpl == NULL) {\n+\t\t\tRTE_ETHDEV_LOG(ERR, \"null mempool pointer\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\t*mbp_buf_size = rte_pktmbuf_data_room_size(mpl);\n+\t\tif (*mbp_buf_size < dev_info->min_rx_bufsize +\n+\t\t RTE_PKTMBUF_HEADROOM) {\n+\t\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\t \"%s mbuf_data_room_size %u < %u (RTE_PKTMBUF_HEADROOM=%u + min_rx_bufsize(dev)=%u)\\n\",\n+\t\t\t\t\tmpl->name, *mbp_buf_size,\n+\t\t\t\t\tRTE_PKTMBUF_HEADROOM + dev_info->min_rx_bufsize,\n+\t\t\t\t\tRTE_PKTMBUF_HEADROOM,\n+\t\t\t\t\tdev_info->min_rx_bufsize);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n rte_eth_rx_queue_check_split(const struct rte_eth_rxseg_split *rx_seg,\n \t\t\t uint16_t n_seg, uint32_t *mbp_buf_size,\n@@ -1733,7 +1772,8 @@ rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id,\n \n \tif (mp != NULL) {\n \t\t/* Single pool configuration check. */\n-\t\tif (rx_conf != NULL && rx_conf->rx_nseg != 0) {\n+\t\tif (rx_conf != NULL &&\n+\t\t (rx_conf->rx_nseg != 0 || rx_conf->rx_npool)) {\n \t\t\tRTE_ETHDEV_LOG(ERR,\n \t\t\t\t \"Ambiguous segment configuration\\n\");\n \t\t\treturn -EINVAL;\n@@ -1763,30 +1803,42 @@ rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id,\n \t\t\t\t dev_info.min_rx_bufsize);\n \t\t\treturn -EINVAL;\n \t\t}\n-\t} else {\n-\t\tconst struct rte_eth_rxseg_split *rx_seg;\n-\t\tuint16_t n_seg;\n+\t} else if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT ||\n+\t\t rx_conf->offloads & RTE_ETH_RX_OFFLOAD_MUL_MEMPOOL) {\n \n-\t\t/* Extended multi-segment configuration check. */\n-\t\tif (rx_conf == NULL || rx_conf->rx_seg == NULL || rx_conf->rx_nseg == 0) {\n+\t\t/* Extended multi-segment/pool configuration check. */\n+\t\tif (rx_conf == NULL ||\n+\t\t (rx_conf->rx_seg == NULL && rx_conf->rx_mempool == NULL) ||\n+\t\t (rx_conf->rx_nseg == 0 && rx_conf->rx_npool == 0)) {\n \t\t\tRTE_ETHDEV_LOG(ERR,\n \t\t\t\t \"Memory pool is null and no extended configuration provided\\n\");\n \t\t\treturn -EINVAL;\n \t\t}\n \n-\t\trx_seg = (const struct rte_eth_rxseg_split *)rx_conf->rx_seg;\n-\t\tn_seg = rx_conf->rx_nseg;\n-\n \t\tif (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT) {\n+\t\t\tconst struct rte_eth_rxseg_split *rx_seg =\n+\t\t\t\t(const struct rte_eth_rxseg_split *)rx_conf->rx_seg;\n+\t\t\tuint16_t n_seg = rx_conf->rx_nseg;\n \t\t\tret = rte_eth_rx_queue_check_split(rx_seg, n_seg,\n \t\t\t\t\t\t\t &mbp_buf_size,\n \t\t\t\t\t\t\t &dev_info);\n-\t\t\tif (ret != 0)\n+\t\t\tif (ret)\n \t\t\t\treturn ret;\n-\t\t} else {\n-\t\t\tRTE_ETHDEV_LOG(ERR, \"No Rx segmentation offload configured\\n\");\n-\t\t\treturn -EINVAL;\n \t\t}\n+\t\tif (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_MUL_MEMPOOL) {\n+\t\t\tconst struct rte_eth_rx_mempool *rx_mempool =\n+\t\t\t\t(const struct rte_eth_rx_mempool *)rx_conf->rx_mempool;\n+\t\t\tret = rte_eth_rx_queue_check_mempool(rx_mempool,\n+\t\t\t\t\t\t\t rx_conf->rx_npool,\n+\t\t\t\t\t\t\t &mbp_buf_size,\n+\t\t\t\t\t\t\t &dev_info);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\n+\t\t}\n+\t} else {\n+\t\tRTE_ETHDEV_LOG(ERR, \"No Rx offload is configured\\n\");\n+\t\treturn -EINVAL;\n \t}\n \n \t/* Use default specified by driver, if nb_rx_desc is zero */\ndiff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h\nindex b62ac5bb6f..17deec2cbd 100644\n--- a/lib/ethdev/rte_ethdev.h\n+++ b/lib/ethdev/rte_ethdev.h\n@@ -1035,6 +1035,11 @@ union rte_eth_rxseg {\n \t/* The other features settings should be added here. */\n };\n \n+/* A common structure used to describe mbuf pools per Rx queue */\n+struct rte_eth_rx_mempool {\n+\tstruct rte_mempool *mp;\n+};\n+\n /**\n * A structure used to configure an Rx ring of an Ethernet port.\n */\n@@ -1067,6 +1072,23 @@ struct rte_eth_rxconf {\n \t */\n \tunion rte_eth_rxseg *rx_seg;\n \n+\t/**\n+\t * Points to an array of mempools.\n+\t *\n+\t * This provides support for multiple mbuf pools per Rx queue.\n+\t *\n+\t * This is often useful for saving the memory where the application can\n+\t * create a different pools to steer the specific size of the packet, thus\n+\t * enabling effective use of memory.\n+\t *\n+\t * Note that on Rx scatter enable, a packet may be delivered using a chain\n+\t * of mbufs obtained from single mempool or multiple mempools based on\n+\t * the NIC implementation.\n+\t *\n+\t */\n+\tstruct rte_eth_rx_mempool *rx_mempool;\n+\tuint16_t rx_npool; /** < number of mempools */\n+\n \tuint64_t reserved_64s[2]; /**< Reserved for future fields */\n \tvoid *reserved_ptrs[2]; /**< Reserved for future fields */\n };\n@@ -1395,6 +1417,7 @@ struct rte_eth_conf {\n #define RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM RTE_BIT64(18)\n #define RTE_ETH_RX_OFFLOAD_RSS_HASH RTE_BIT64(19)\n #define RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT RTE_BIT64(20)\n+#define RTE_ETH_RX_OFFLOAD_MUL_MEMPOOL RTE_BIT64(21)\n \n #define RTE_ETH_RX_OFFLOAD_CHECKSUM (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | \\\n \t\t\t\t RTE_ETH_RX_OFFLOAD_UDP_CKSUM | \\\n@@ -1615,6 +1638,7 @@ struct rte_eth_dev_info {\n \t/** Configured number of Rx/Tx queues */\n \tuint16_t nb_rx_queues; /**< Number of Rx queues. */\n \tuint16_t nb_tx_queues; /**< Number of Tx queues. */\n+\tuint16_t max_pools;\n \t/** Rx parameter recommendations */\n \tstruct rte_eth_dev_portconf default_rxportconf;\n \t/** Tx parameter recommendations */\n", "prefixes": [ "v4", "1/3" ] }