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GET /api/patches/115466/?format=api
{ "id": 115466, "url": "https://patches.dpdk.org/api/patches/115466/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220826103605.1579589-5-cristian.dumitrescu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220826103605.1579589-5-cristian.dumitrescu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220826103605.1579589-5-cristian.dumitrescu@intel.com", "date": "2022-08-26T10:36:02", "name": "[4/7] pipeline: support direct registers on the control path", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "74a7cbac7eb14f550234e401d144e4f16cba01a6", "submitter": { "id": 19, "url": "https://patches.dpdk.org/api/people/19/?format=api", "name": "Cristian Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220826103605.1579589-5-cristian.dumitrescu@intel.com/mbox/", "series": [ { "id": 24426, "url": "https://patches.dpdk.org/api/series/24426/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=24426", "date": "2022-08-26T10:35:58", "name": "pipeline: support direct registers and meters", "version": 1, "mbox": "https://patches.dpdk.org/series/24426/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/115466/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/115466/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1D98BA0554;\n\tFri, 26 Aug 2022 12:36:30 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CD9B942829;\n\tFri, 26 Aug 2022 12:36:15 +0200 (CEST)", "from mga06.intel.com (mga06b.intel.com [134.134.136.31])\n by mails.dpdk.org (Postfix) with ESMTP id 5549F40143\n for <dev@dpdk.org>; Fri, 26 Aug 2022 12:36:11 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Aug 2022 03:36:10 -0700", "from silpixa00400573.ir.intel.com (HELO\n silpixa00400573.ger.corp.intel.com.) ([10.237.223.157])\n by fmsmga008.fm.intel.com with ESMTP; 26 Aug 2022 03:36:09 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1661510171; x=1693046171;\n h=from:to:subject:date:message-id:in-reply-to:references:\n mime-version:content-transfer-encoding;\n bh=kohfYz5OkYujxjOl5j8VnlJCSwrypbwXmoBsOpYBPio=;\n b=IeKGE18fwDNcm08qpd+Jj291HBen59Grh0s+0vMG1ASUjOehOydXCiR6\n Ij3SHcTXw8nRa+IURnEOQlSfaJ2LBOwM2QsSnVdeKPWG5pSKvV+3F6nLl\n 9TMn6iVzpV0yCyUses0216kumD5oZyTzdhI1TGAOkkeJt5KQTSJRF//il\n vZVpQ2/pLZKP63XbGW2Gk9K07zzXOBOcMTRasRO1T/jYYp9VP132Cje1u\n 85+sWqledPUx/hUCb4vkHIfJ2LgPdVdwhD0XfVF5UPuLCHJSkpbvbjbzS\n +OV0RUY5Eb0lja59lpMd5ETGk79BnDk78v52ZAoYdJiu9PDWfZjhbGHlr Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10450\"; a=\"356194327\"", "E=Sophos;i=\"5.93,265,1654585200\"; d=\"scan'208\";a=\"356194327\"", "E=Sophos;i=\"5.93,265,1654585200\"; d=\"scan'208\";a=\"671414283\"" ], "X-ExtLoop1": "1", "From": "Cristian Dumitrescu <cristian.dumitrescu@intel.com>", "To": "dev@dpdk.org", "Subject": "[PATCH 4/7] pipeline: support direct registers on the control path", "Date": "Fri, 26 Aug 2022 10:36:02 +0000", "Message-Id": "<20220826103605.1579589-5-cristian.dumitrescu@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20220826103605.1579589-1-cristian.dumitrescu@intel.com>", "References": "<20220826103605.1579589-1-cristian.dumitrescu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add pipeline control path API to read/write direct registers. These\nregisters are identified by a table key, whose entry ID is used as the\nindex into the register array.\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\n---\n lib/pipeline/rte_swx_ctl.h | 52 ++++++++\n lib/pipeline/rte_swx_pipeline.c | 214 ++++++++++++++++++++++++++++++++\n lib/pipeline/version.map | 2 +\n 3 files changed, 268 insertions(+)", "diff": "diff --git a/lib/pipeline/rte_swx_ctl.h b/lib/pipeline/rte_swx_ctl.h\nindex 0694df557a..1b47820441 100644\n--- a/lib/pipeline/rte_swx_ctl.h\n+++ b/lib/pipeline/rte_swx_ctl.h\n@@ -1237,6 +1237,58 @@ rte_swx_ctl_pipeline_regarray_write(struct rte_swx_pipeline *p,\n \t\t\t\t uint32_t regarray_index,\n \t\t\t\t uint64_t value);\n \n+/**\n+ * Register read with table key lookup\n+ *\n+ * @param[in] p\n+ * Pipeline handle.\n+ * @param[in] regarray_name\n+ * Register array name.\n+ * @param[in] table_name\n+ * Regular or learner table name.\n+ * @param[in] table_key\n+ * Table key.\n+ * @param[out] value\n+ * Current register value.\n+ * @return\n+ * 0 on success or the following error codes otherwise:\n+ * -EINVAL: Invalid argument;\n+ * -ENOMEM: Not enough memory.\n+ */\n+__rte_experimental\n+int\n+rte_swx_ctl_pipeline_regarray_read_with_key(struct rte_swx_pipeline *p,\n+\t\t\t\t\t const char *regarray_name,\n+\t\t\t\t\t const char *table_name,\n+\t\t\t\t\t uint8_t *table_key,\n+\t\t\t\t\t uint64_t *value);\n+\n+/**\n+ * Register write with table key lookup\n+ *\n+ * @param[in] p\n+ * Pipeline handle.\n+ * @param[in] regarray_name\n+ * Register array name.\n+ * @param[in] table_name\n+ * Regular or learner table name.\n+ * @param[in] table_key\n+ * Table key.\n+ * @param[in] value\n+ * Value to be written to the register.\n+ * @return\n+ * 0 on success or the following error codes otherwise:\n+ * -EINVAL: Invalid argument;\n+ * -ENOMEM: Not enough memory.\n+ */\n+__rte_experimental\n+int\n+rte_swx_ctl_pipeline_regarray_write_with_key(struct rte_swx_pipeline *p,\n+\t\t\t\t\t const char *regarray_name,\n+\t\t\t\t\t const char *table_name,\n+\t\t\t\t\t uint8_t *table_key,\n+\t\t\t\t\t uint64_t value);\n+\n /*\n * Meter Array Query and Configuration API.\n */\ndiff --git a/lib/pipeline/rte_swx_pipeline.c b/lib/pipeline/rte_swx_pipeline.c\nindex ec8268b7f8..e726bf1575 100644\n--- a/lib/pipeline/rte_swx_pipeline.c\n+++ b/lib/pipeline/rte_swx_pipeline.c\n@@ -11101,6 +11101,220 @@ rte_swx_ctl_pipeline_mirroring_session_set(struct rte_swx_pipeline *p,\n \treturn 0;\n }\n \n+static int\n+rte_swx_ctl_pipeline_table_lookup(struct rte_swx_pipeline *p,\n+\t\t\t\t const char *table_name,\n+\t\t\t\t uint8_t *key,\n+\t\t\t\t uint64_t *action_id,\n+\t\t\t\t uint8_t **action_data,\n+\t\t\t\t size_t *entry_id,\n+\t\t\t\t int *hit)\n+{\n+\tstruct table *t;\n+\tvoid *mailbox = NULL;\n+\n+\t/* Check input arguments. */\n+\tif (!p ||\n+\t !p->build_done ||\n+\t !table_name ||\n+\t !table_name[0] ||\n+\t !key ||\n+\t !entry_id ||\n+\t !hit)\n+\t\treturn -EINVAL;\n+\n+\t/* Find the table. */\n+\tt = table_find(p, table_name);\n+\tif (!t)\n+\t\treturn -EINVAL;\n+\n+\tif (!t->type) {\n+\t\t*hit = 0;\n+\t\treturn 0;\n+\t}\n+\n+\t/* Setup mailbox. */\n+\tif (t->type->ops.mailbox_size_get) {\n+\t\tuint64_t mailbox_size;\n+\n+\t\tmailbox_size = t->type->ops.mailbox_size_get();\n+\t\tif (mailbox_size) {\n+\t\t\tmailbox = calloc(1, mailbox_size);\n+\t\t\tif (!mailbox)\n+\t\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\n+\t/* Table lookup operation. */\n+\tfor ( ; ; ) {\n+\t\tstruct rte_swx_table_state *ts = &p->table_state[t->id];\n+\t\tint done;\n+\n+\t\tdone = t->type->ops.lkp(ts->obj,\n+\t\t\t\t\tmailbox,\n+\t\t\t\t\t&key,\n+\t\t\t\t\taction_id,\n+\t\t\t\t\taction_data,\n+\t\t\t\t\tentry_id,\n+\t\t\t\t\thit);\n+\t\tif (done)\n+\t\t\tbreak;\n+\t}\n+\n+\t/* Free mailbox. */\n+\tfree(mailbox);\n+\n+\treturn 0;\n+}\n+\n+static int\n+rte_swx_ctl_pipeline_learner_lookup(struct rte_swx_pipeline *p,\n+\t\t\t\t const char *learner_name,\n+\t\t\t\t uint8_t *key,\n+\t\t\t\t uint64_t *action_id,\n+\t\t\t\t uint8_t **action_data,\n+\t\t\t\t size_t *entry_id,\n+\t\t\t\t int *hit)\n+{\n+\tstruct learner *l;\n+\tvoid *mailbox = NULL;\n+\tuint64_t mailbox_size, time;\n+\n+\t/* Check input arguments. */\n+\tif (!p ||\n+\t !p->build_done ||\n+\t !learner_name ||\n+\t !learner_name[0] ||\n+\t !key ||\n+\t !entry_id ||\n+\t !hit)\n+\t\treturn -EINVAL;\n+\n+\t/* Find the learner table. */\n+\tl = learner_find(p, learner_name);\n+\tif (!l)\n+\t\treturn -EINVAL;\n+\n+\t/* Setup mailbox. */\n+\tmailbox_size = rte_swx_table_learner_mailbox_size_get();\n+\tif (mailbox_size) {\n+\t\tmailbox = calloc(1, mailbox_size);\n+\t\tif (!mailbox)\n+\t\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* Learner table lookup operation. */\n+\ttime = rte_get_tsc_cycles();\n+\tfor ( ; ; ) {\n+\t\tuint32_t pos = p->n_tables + p->n_selectors + l->id;\n+\t\tstruct rte_swx_table_state *ts = &p->table_state[pos];\n+\t\tint done;\n+\n+\t\tdone = rte_swx_table_learner_lookup(ts->obj,\n+\t\t\t\t\t\t mailbox,\n+\t\t\t\t\t\t time,\n+\t\t\t\t\t\t &key,\n+\t\t\t\t\t\t action_id,\n+\t\t\t\t\t\t action_data,\n+\t\t\t\t\t\t entry_id,\n+\t\t\t\t\t\t hit);\n+\t\tif (done)\n+\t\t\tbreak;\n+\t}\n+\n+\t/* Free mailbox. */\n+\tfree(mailbox);\n+\n+\treturn 0;\n+}\n+\n+static int\n+rte_swx_ctl_pipeline_table_entry_id_get(struct rte_swx_pipeline *p,\n+\t\t\t\t\tconst char *table_name,\n+\t\t\t\t\tuint8_t *table_key,\n+\t\t\t\t\tsize_t *table_entry_id)\n+{\n+\tstruct table *t;\n+\tstruct learner *l;\n+\tuint64_t action_id;\n+\tuint8_t *action_data;\n+\tsize_t entry_id = 0;\n+\tint hit = 0, status;\n+\n+\t/* Check input arguments. */\n+\tif (!p ||\n+\t !p->build_done ||\n+\t !table_name ||\n+\t !table_name[0] ||\n+\t !table_key ||\n+\t !table_entry_id)\n+\t\treturn -EINVAL;\n+\n+\tt = table_find(p, table_name);\n+\tl = learner_find(p, table_name);\n+\tif (!t && !l)\n+\t\treturn -EINVAL;\n+\n+\t/* Table lookup operation. */\n+\tif (t)\n+\t\tstatus = rte_swx_ctl_pipeline_table_lookup(p,\n+\t\t\t\t\t\t\t table_name,\n+\t\t\t\t\t\t\t table_key,\n+\t\t\t\t\t\t\t &action_id,\n+\t\t\t\t\t\t\t &action_data,\n+\t\t\t\t\t\t\t &entry_id,\n+\t\t\t\t\t\t\t &hit);\n+\telse\n+\t\tstatus = rte_swx_ctl_pipeline_learner_lookup(p,\n+\t\t\t\t\t\t\t table_name,\n+\t\t\t\t\t\t\t table_key,\n+\t\t\t\t\t\t\t &action_id,\n+\t\t\t\t\t\t\t &action_data,\n+\t\t\t\t\t\t\t &entry_id,\n+\t\t\t\t\t\t\t &hit);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Reserve entry ID 0 for the table default entry. */\n+\t*table_entry_id = hit ? (1 + entry_id) : 0;\n+\n+\treturn 0;\n+}\n+\n+int\n+rte_swx_ctl_pipeline_regarray_read_with_key(struct rte_swx_pipeline *p,\n+\t\t\t\t\t const char *regarray_name,\n+\t\t\t\t\t const char *table_name,\n+\t\t\t\t\t uint8_t *table_key,\n+\t\t\t\t\t uint64_t *value)\n+{\n+\tsize_t entry_id = 0;\n+\tint status;\n+\n+\tstatus = rte_swx_ctl_pipeline_table_entry_id_get(p, table_name, table_key, &entry_id);\n+\tif (status)\n+\t\treturn status;\n+\n+\treturn rte_swx_ctl_pipeline_regarray_read(p, regarray_name, entry_id, value);\n+}\n+\n+int\n+rte_swx_ctl_pipeline_regarray_write_with_key(struct rte_swx_pipeline *p,\n+\t\t\t\t\t const char *regarray_name,\n+\t\t\t\t\t const char *table_name,\n+\t\t\t\t\t uint8_t *table_key,\n+\t\t\t\t\t uint64_t value)\n+{\n+\tsize_t entry_id = 0;\n+\tint status;\n+\n+\tstatus = rte_swx_ctl_pipeline_table_entry_id_get(p, table_name, table_key, &entry_id);\n+\tif (status)\n+\t\treturn status;\n+\n+\treturn rte_swx_ctl_pipeline_regarray_write(p, regarray_name, entry_id, value);\n+}\n+\n /*\n * Pipeline compilation.\n */\ndiff --git a/lib/pipeline/version.map b/lib/pipeline/version.map\nindex 16806e6802..8ed92042d6 100644\n--- a/lib/pipeline/version.map\n+++ b/lib/pipeline/version.map\n@@ -147,6 +147,8 @@ EXPERIMENTAL {\n \n \t#added in 22.11\n \trte_swx_ctl_pipeline_find;\n+\trte_swx_ctl_pipeline_regarray_read_with_key;\n+\trte_swx_ctl_pipeline_regarray_write_with_key;\n \trte_swx_pipeline_build_from_lib;\n \trte_swx_pipeline_codegen;\n \trte_swx_pipeline_find;\n", "prefixes": [ "4/7" ] }