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GET /api/patches/114278/?format=api
{ "id": 114278, "url": "https://patches.dpdk.org/api/patches/114278/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220727122406.1609242-1-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220727122406.1609242-1-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220727122406.1609242-1-michaelba@nvidia.com", "date": "2022-07-27T12:24:06", "name": "net/mlx5: fix detection of LRO support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "82d110a0e9c98356e7c13bd782d6beec1d416822", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220727122406.1609242-1-michaelba@nvidia.com/mbox/", "series": [ { "id": 24105, "url": "https://patches.dpdk.org/api/series/24105/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=24105", "date": "2022-07-27T12:24:06", "name": "net/mlx5: fix detection of LRO support", "version": 1, "mbox": "https://patches.dpdk.org/series/24105/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/114278/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/114278/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 10A79A00C4;\n\tWed, 27 Jul 2022 14:24:18 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A066440141;\n\tWed, 27 Jul 2022 14:24:17 +0200 (CEST)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2085.outbound.protection.outlook.com [40.107.237.85])\n by mails.dpdk.org (Postfix) with ESMTP id DE44D400D7;\n Wed, 27 Jul 2022 14:24:15 +0200 (CEST)", "from BN9PR03CA0858.namprd03.prod.outlook.com (2603:10b6:408:13d::23)\n by CH2PR12MB4279.namprd12.prod.outlook.com (2603:10b6:610:af::24)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5458.19; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, <michaelba@nvidia.com>,\n <stable@dpdk.org>, Gal Shalom <galshalom@nvidia.com>", "Subject": "[PATCH] net/mlx5: fix detection of LRO support", "Date": "Wed, 27 Jul 2022 15:24:06 +0300", "Message-ID": "<20220727122406.1609242-1-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "6f240ab0-972c-4e1c-16b3-08da6fcaeacb", "X-MS-TrafficTypeDiagnostic": "CH2PR12MB4279:EE_", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n F2HyRAVIkiJ9EBk7UCwqP3LkL9LrPo2tjwgfvD2GnilU3gYijVwIF7YbEqhE5Fenfd1OZ0NWXkBx3TUyDj1n3GUlVVeVkYASJ3sdAKd6aB0dha/zZl05Xq0h3ZsiZdOkMrVKMsh8lodajRLivjHBnb5U3mnGWt+Qfz+vJoHzh8Zzjj+h8VyjSlD30D2XUuSSYWg8VGzpAejEui7Kw3fMi9shW1foQxCFsYsmIBam/TO2db5fjr16VO8d7BkwRitvZ2y0lkeYm4FTuECkzCp+pp4dkai6GphhPoDeXc7C3GttgjTLjianuvJLsCSHU9C92SScrxvf6BgHx/M+GarilgrTwmeMW/D+PdvMsJG3cxsno4FVtH8qxc1DI7t29U2oWdwVO+D3n68Hc1If3mdGXAoDx0FCE2s1P1L+b3AFf3CzgilXUoH3/RYV2iVamQKuk0hGtozXuvSMRHIiHKjEALtcfyxd+4/pnhwrm6xebw1CaSZXAJZsUxiRGw8Dqz7ZuICec7MVlNfsrfaJT0F3fk2NdSTrJQIYa0L1B26JHaPjZ4vNOAvBZJI7XgwMsObxu/o59cxV/QxX/rDIHJnDoQOAuSZcv/NWxbvoGP9ziaDmG6dkMHcNuhoff9sASTef9f0S5Rop8WYmnJFWOBZI9sXZNGvLPFZEAlq1TwX1pGr735uoMs5+d4xE2muefijhEvKeLE+NnHqXd8mrlanpwg0TO2K0cQLmhQs0PX4THwiLxphqFCJVC7YtoRmX+N0c2yiOG27AYrv2VRQmUFpEQw+bkPOturibTiPnGtyiINp6nJjCRxDRWzp4vT7fz3/7S/o2eHFkUjFgJQgtrlVu4Q==", "X-Forefront-Antispam-Report": "CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230016)(4636009)(376002)(136003)(396003)(39860400002)(346002)(46966006)(40470700004)(36840700001)(186003)(5660300002)(336012)(40460700003)(6916009)(316002)(2616005)(82740400003)(426003)(36860700001)(2906002)(6286002)(107886003)(83380400001)(81166007)(1076003)(55016003)(450100002)(40480700001)(8936002)(54906003)(8676002)(82310400005)(70586007)(356005)(70206006)(6666004)(7696005)(41300700001)(36756003)(47076005)(478600001)(4326008)(26005)(86362001)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Jul 2022 12:24:13.7726 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6f240ab0-972c-4e1c-16b3-08da6fcaeacb", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT021.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB4279", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "One of the conditions to allow LRO offload is the DV configuration.\n\nThe function incorrectly checks the DV configuration before initializing\nit by the user devarg; hence, LRO cannot be allowed.\n\nThis patch moves this check to mlx5_shared_dev_ctx_args_config, where DV\nconfiguration is initialized.\n\nFixes: c4b862013598 (\"net/mlx5: refactor to detect operation by DevX\")\nCc: michaelba@nvidia.com\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nReported-by: Gal Shalom <galshalom@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 9 ---------\n drivers/net/mlx5/mlx5.c | 14 ++++++++++----\n drivers/net/mlx5/mlx5.h | 2 +-\n drivers/net/mlx5/mlx5_devx.c | 2 +-\n drivers/net/mlx5/mlx5_rxq.c | 6 +++---\n 5 files changed, 15 insertions(+), 18 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 0741028dab..1bba89d3c0 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -369,15 +369,6 @@ mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh)\n \t\t\"DevX does not provide UAR offset, can't create queues for packet pacing.\");\n \tsh->dev_cap.txpp_en = 0;\n #endif\n-\t/* Check for LRO support. */\n-\tif (mlx5_devx_obj_ops_en(sh) && hca_attr->lro_cap) {\n-\t\t/* TBD check tunnel lro caps. */\n-\t\tsh->dev_cap.lro_supported = 1;\n-\t\tDRV_LOG(DEBUG, \"Device supports LRO.\");\n-\t\tDRV_LOG(DEBUG,\n-\t\t\t\"LRO minimal size of TCP segment required for coalescing is %d bytes.\",\n-\t\t\thca_attr->lro_min_mss_size);\n-\t}\n \tsh->dev_cap.scatter_fcs_w_decap_disable =\n \t\t\t\t\thca_attr->scatter_fcs_w_decap_disable;\n \tsh->dev_cap.rq_delay_drop_en = hca_attr->rq_delay_drop;\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 998846adbe..5829b66b0b 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1327,6 +1327,15 @@ mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh,\n \t\tDRV_LOG(WARNING,\n \t\t\t\"\\\"tx_skew\\\" doesn't affect without \\\"tx_pp\\\".\");\n \t}\n+\t/* Check for LRO support. */\n+\tif (mlx5_devx_obj_ops_en(sh) && sh->cdev->config.hca_attr.lro_cap) {\n+\t\t/* TBD check tunnel lro caps. */\n+\t\tconfig->lro_allowed = 1;\n+\t\tDRV_LOG(DEBUG, \"LRO is allowed.\");\n+\t\tDRV_LOG(DEBUG,\n+\t\t\t\"LRO minimal size of TCP segment required for coalescing is %d bytes.\",\n+\t\t\tsh->cdev->config.hca_attr.lro_min_mss_size);\n+\t}\n \t/*\n \t * If HW has bug working with tunnel packet decapsulation and scatter\n \t * FCS, and decapsulation is needed, clear the hw_fcs_strip bit.\n@@ -2392,10 +2401,7 @@ mlx5_port_args_config(struct mlx5_priv *priv, struct mlx5_kvargs_ctrl *mkvlist,\n \t\tconfig->mps == MLX5_MPW_ENHANCED ? \"enhanced \" :\n \t\tconfig->mps == MLX5_MPW ? \"legacy \" : \"\",\n \t\tconfig->mps != MLX5_MPW_DISABLED ? \"enabled\" : \"disabled\");\n-\t/* LRO is supported only when DV flow enabled. */\n-\tif (dev_cap->lro_supported && !priv->sh->config.dv_flow_en)\n-\t\tdev_cap->lro_supported = 0;\n-\tif (dev_cap->lro_supported) {\n+\tif (priv->sh->config.lro_allowed) {\n \t\t/*\n \t\t * If LRO timeout is not configured by application,\n \t\t * use the minimal supported value.\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 8af84aef50..a56ee83d99 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -151,7 +151,6 @@ struct mlx5_dev_cap {\n \t/* HW has bug working with tunnel packet decap and scatter FCS. */\n \tuint32_t hw_fcs_strip:1; /* FCS stripping is supported. */\n \tuint32_t rt_timestamp:1; /* Realtime timestamp format. */\n-\tuint32_t lro_supported:1; /* Whether LRO is supported. */\n \tuint32_t rq_delay_drop_en:1; /* Enable RxQ delay drop. */\n \tuint32_t tunnel_en:3;\n \t/* Whether tunnel stateless offloads are supported. */\n@@ -308,6 +307,7 @@ struct mlx5_sh_config {\n \tuint32_t decap_en:1; /* Whether decap will be used or not. */\n \tuint32_t hw_fcs_strip:1; /* FCS stripping is supported. */\n \tuint32_t allow_duplicate_pattern:1;\n+\tuint32_t lro_allowed:1; /* Whether LRO is allowed. */\n \t/* Allow/Prevent the duplicate rules pattern. */\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 6886ae1f22..943aa8ef57 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -835,7 +835,7 @@ mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key,\n \tif (dev->data->dev_conf.lpbk_mode)\n \t\ttir_attr->self_lb_block = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;\n \tif (lro) {\n-\t\tMLX5_ASSERT(priv->sh->dev_cap.lro_supported);\n+\t\tMLX5_ASSERT(priv->sh->config.lro_allowed);\n \t\ttir_attr->lro_timeout_period_usecs = priv->config.lro_timeout;\n \t\ttir_attr->lro_max_msg_sz = priv->max_lro_msg_size;\n \t\ttir_attr->lro_enable_mask =\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex eaf23d0df4..b1543b480e 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -374,7 +374,7 @@ mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)\n \t\t\t RTE_ETH_RX_OFFLOAD_TCP_CKSUM);\n \tif (priv->sh->dev_cap.hw_vlan_strip)\n \t\toffloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;\n-\tif (priv->sh->dev_cap.lro_supported)\n+\tif (priv->sh->config.lro_allowed)\n \t\toffloads |= RTE_ETH_RX_OFFLOAD_TCP_LRO;\n \treturn offloads;\n }\n@@ -843,9 +843,9 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \tbool is_extmem = false;\n \n \tif ((offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) &&\n-\t !priv->sh->dev_cap.lro_supported) {\n+\t !priv->sh->config.lro_allowed) {\n \t\tDRV_LOG(ERR,\n-\t\t\t\"Port %u queue %u LRO is configured but not supported.\",\n+\t\t\t\"Port %u queue %u LRO is configured but not allowed.\",\n \t\t\tdev->data->port_id, idx);\n \t\trte_errno = EINVAL;\n \t\treturn -rte_errno;\n", "prefixes": [] }