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GET /api/patches/113834/?format=api
{ "id": 113834, "url": "https://patches.dpdk.org/api/patches/113834/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220708131431.148279-1-marcinx.danilewicz@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220708131431.148279-1-marcinx.danilewicz@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220708131431.148279-1-marcinx.danilewicz@intel.com", "date": "2022-07-08T13:14:31", "name": "[v9] sched: enable CMAN at runtime", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "201e172e5233c1614a6526dc604f2fe60dd782ea", "submitter": { "id": 1988, "url": "https://patches.dpdk.org/api/people/1988/?format=api", "name": "Danilewicz, MarcinX", "email": "marcinx.danilewicz@intel.com" }, "delegate": { "id": 3961, "url": "https://patches.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220708131431.148279-1-marcinx.danilewicz@intel.com/mbox/", "series": [ { "id": 23944, "url": "https://patches.dpdk.org/api/series/23944/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=23944", "date": "2022-07-08T13:14:31", "name": "[v9] sched: enable CMAN at runtime", "version": 9, "mbox": "https://patches.dpdk.org/series/23944/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/113834/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/113834/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7A5F8A00C5;\n\tFri, 8 Jul 2022 15:14:40 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0FE39406B4;\n\tFri, 8 Jul 2022 15:14:40 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id B34374021E\n for <dev@dpdk.org>; Fri, 8 Jul 2022 15:14:38 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Jul 2022 06:14:37 -0700", "from silpixa00400629.ir.intel.com ([10.237.213.88])\n by orsmga003.jf.intel.com with ESMTP; 08 Jul 2022 06:14:35 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1657286079; x=1688822079;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=9oN6E0/Ky7reluhrfQRe0tO4O5ZgW0whKH0oFm6yYU0=;\n b=OFLR6XXGC5RgA11HdhxyhF9ZPH6WSwG7v45iwE08PVluDTLiZrhYGTUV\n akrMsypiX/RBBapP1fdH4WVonYxebQoPvqXPpYFirjJWpg9e5kQgpWZcE\n pDEaoz47nxCFtQ0xGHGdBryR13Wq3KfaTPBRolby6PbVh2sZ0dlFy8wNz\n ioYtTSeFghbY2Y+aPMCRW5o2cPtXVs5kfaMXVwyg0lOKltYZuJg04coyc\n 2Rrh9GH6m4PtU2ctDzO0Vserc8ox8gnwnTKTvWXyVn8PTW5wqKajrV0k8\n J8hV3PKcvMdFGBoSuYoCGcK/KAf5v3P3VQF2GugWtNnifJUrT9ap4mGg+ A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10401\"; a=\"281826356\"", "E=Sophos;i=\"5.92,255,1650956400\"; d=\"scan'208\";a=\"281826356\"", "E=Sophos;i=\"5.92,255,1650956400\"; d=\"scan'208\";a=\"544204796\"" ], "X-ExtLoop1": "1", "From": "Marcin Danilewicz <marcinx.danilewicz@intel.com>", "To": "dev@dpdk.org,\n\tjasvinder.singh@intel.com,\n\tcristian.dumitrescu@intel.com", "Cc": "megha.ajmera@intel.com", "Subject": "[PATCH v9] sched: enable CMAN at runtime", "Date": "Fri, 8 Jul 2022 13:14:31 +0000", "Message-Id": "<20220708131431.148279-1-marcinx.danilewicz@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220705170533.709971-1-marcinx.danilewicz@intel.com>", "References": "<20220705170533.709971-1-marcinx.danilewicz@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added changes to enable CMAN (RED or PIE) at init\nfrom profile configuration file.\n\nBy default CMAN code is enable but not in use, when\nthere is no RED or PIE profile configured.\n\nSigned-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>\n---\nLog: v2 change in rte_sched.h to avoid ABI breakage.\n v3 changes from comments\n v4 rebase to 22.07-rc1\n v5 rebase to main latest\n v6 commit message fixed\n v7 changes from comments\n v8 with changes from comments\n v9 changes from comments\n tmgr.c\n cman_params set to null\n qos_sched/cfg_file.c\n removed redundant cman_params to NULL assignement\n subport_params[].cman_params assigned\n only when CMAN enabled\n---\n config/rte_config.h | 3 -\n drivers/net/softnic/rte_eth_softnic_tm.c | 12 --\n examples/ip_pipeline/tmgr.c | 6 +-\n examples/qos_sched/cfg_file.c | 49 +-------\n examples/qos_sched/cfg_file.h | 5 -\n examples/qos_sched/init.c | 76 +-----------\n examples/qos_sched/main.h | 2 -\n examples/qos_sched/profile.cfg | 135 +--------------------\n examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++\n examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++\n lib/sched/rte_sched.c | 47 +-------\n 11 files changed, 298 insertions(+), 322 deletions(-)\n create mode 100644 examples/qos_sched/profile_pie.cfg\n create mode 100644 examples/qos_sched/profile_red.cfg", "diff": "diff --git a/config/rte_config.h b/config/rte_config.h\nindex 46549cb062..ae56a86394 100644\n--- a/config/rte_config.h\n+++ b/config/rte_config.h\n@@ -88,9 +88,6 @@\n /* rte_power defines */\n #define RTE_MAX_LCORE_FREQS 64\n \n-/* rte_sched defines */\n-// RTE_SCHED_CMAN is not set\n-\n /* rte_graph defines */\n #define RTE_GRAPH_BURST_SIZE 256\n #define RTE_LIBRTE_GRAPH_STATS 1\ndiff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c\nindex 6a7766ba1c..3e4bed81e9 100644\n--- a/drivers/net/softnic/rte_eth_softnic_tm.c\n+++ b/drivers/net/softnic/rte_eth_softnic_tm.c\n@@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n-#ifdef RTE_SCHED_CMAN\n-#define WRED_SUPPORTED\t\t\t\t\t\t1\n-#else\n #define WRED_SUPPORTED\t\t\t\t\t\t0\n-#endif\n \n #define STATS_MASK_DEFAULT\t\t\t\t\t\\\n \t(RTE_TM_STATS_N_PKTS |\t\t\t\t\t\\\n@@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id)\n \treturn NULL;\n }\n \n-#ifdef RTE_SCHED_CMAN\n-\n static void\n wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)\n {\n@@ -2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)\n \t\t}\n }\n \n-#else\n-\n-#define wred_profiles_set(dev, subport_id)\n-\n-#endif\n-\n static struct tm_shared_shaper *\n tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node)\n {\ndiff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c\nindex b138e885cf..18bee1e0fc 100644\n--- a/examples/ip_pipeline/tmgr.c\n+++ b/examples/ip_pipeline/tmgr.c\n@@ -17,7 +17,6 @@ static uint32_t n_subport_profiles;\n static struct rte_sched_pipe_params\n \tpipe_profile[TMGR_PIPE_PROFILE_MAX];\n \n-#ifdef RTE_SCHED_CMAN\n static struct rte_sched_cman_params cman_params = {\n \t.red_params = {\n \t\t/* Traffic Class 0 Colors Green / Yellow / Red */\n@@ -86,7 +85,6 @@ static struct rte_sched_cman_params cman_params = {\n \t\t[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n \t\t},\n };\n-#endif /* RTE_SCHED_CMAN */\n \n static uint32_t n_pipe_profiles;\n \n@@ -96,9 +94,7 @@ static const struct rte_sched_subport_params subport_params_default = {\n \t.pipe_profiles = pipe_profile,\n \t.n_pipe_profiles = 0, /* filled at run time */\n \t.n_max_pipe_profiles = RTE_DIM(pipe_profile),\n-#ifdef RTE_SCHED_CMAN\n-\t.cman_params = &cman_params,\n-#endif /* RTE_SCHED_CMAN */\n+\t.cman_params = NULL,\n };\n \n static struct tmgr_port_list tmgr_port_list;\ndiff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c\nindex 450482f07d..deaa28d391 100644\n--- a/examples/qos_sched/cfg_file.c\n+++ b/examples/qos_sched/cfg_file.c\n@@ -23,6 +23,8 @@\n uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];\n uint32_t n_active_queues;\n \n+struct rte_sched_cman_params cman_params;\n+\n int\n cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port_params)\n {\n@@ -229,40 +231,6 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,\n \treturn 0;\n }\n \n-#ifdef RTE_SCHED_CMAN\n-void set_subport_cman_params(struct rte_sched_subport_params *subport_p,\n-\t\t\t\t\tstruct rte_sched_cman_params cman_p)\n-{\n-\tint j, k;\n-\tsubport_p->cman_params->cman_mode = cman_p.cman_mode;\n-\n-\tfor (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {\n-\t\tif (subport_p->cman_params->cman_mode ==\n-\t\t\t\t\tRTE_SCHED_CMAN_RED) {\n-\t\t\tfor (k = 0; k < RTE_COLORS; k++) {\n-\t\t\t\tsubport_p->cman_params->red_params[j][k].min_th =\n-\t\t\t\t\tcman_p.red_params[j][k].min_th;\n-\t\t\t\tsubport_p->cman_params->red_params[j][k].max_th =\n-\t\t\t\t\tcman_p.red_params[j][k].max_th;\n-\t\t\t\tsubport_p->cman_params->red_params[j][k].maxp_inv =\n-\t\t\t\t\tcman_p.red_params[j][k].maxp_inv;\n-\t\t\t\tsubport_p->cman_params->red_params[j][k].wq_log2 =\n-\t\t\t\t\tcman_p.red_params[j][k].wq_log2;\n-\t\t\t}\n-\t\t} else {\n-\t\t\tsubport_p->cman_params->pie_params[j].qdelay_ref =\n-\t\t\t\tcman_p.pie_params[j].qdelay_ref;\n-\t\t\tsubport_p->cman_params->pie_params[j].dp_update_interval =\n-\t\t\t\tcman_p.pie_params[j].dp_update_interval;\n-\t\t\tsubport_p->cman_params->pie_params[j].max_burst =\n-\t\t\t\tcman_p.pie_params[j].max_burst;\n-\t\t\tsubport_p->cman_params->pie_params[j].tailq_th =\n-\t\t\t\tcman_p.pie_params[j].tailq_th;\n-\t\t}\n-\t}\n-}\n-#endif\n-\n int\n cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)\n {\n@@ -276,12 +244,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \tmemset(active_queues, 0, sizeof(active_queues));\n \tn_active_queues = 0;\n \n-#ifdef RTE_SCHED_CMAN\n-\tstruct rte_sched_cman_params cman_params = {\n-\t\t.cman_mode = RTE_SCHED_CMAN_RED,\n-\t\t.red_params = { },\n-\t};\n-\n \tif (rte_cfgfile_has_section(cfg, \"red\")) {\n \t\tcman_params.cman_mode = RTE_SCHED_CMAN_RED;\n \n@@ -387,7 +349,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \n \t\t}\n \t}\n-#endif /* RTE_SCHED_CMAN */\n \n \tfor (i = 0; i < MAX_SCHED_SUBPORTS; i++) {\n \t\tchar sec_name[CFG_NAME_LEN];\n@@ -465,9 +426,9 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo\n \t\t\t\t\t}\n \t\t\t\t}\n \t\t\t}\n-#ifdef RTE_SCHED_CMAN\n-\t\t\tset_subport_cman_params(subport_params+i, cman_params);\n-#endif\n+\t\t\tif (cman_params.cman_mode == RTE_SCHED_CMAN_PIE ||\n+\t\t\t\tcman_params.cman_mode == RTE_SCHED_CMAN_RED)\n+\t\t\t\tsubport_params[i].cman_params = &cman_params;\n \t\t}\n \t}\n \ndiff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h\nindex 1a9dce9db5..0dc458aa71 100644\n--- a/examples/qos_sched/cfg_file.h\n+++ b/examples/qos_sched/cfg_file.h\n@@ -12,11 +12,6 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);\n \n int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);\n \n-#ifdef RTE_SCHED_CMAN\n-void set_subport_cman_params(struct rte_sched_subport_params *subport_p,\n-\t\t\t\t\tstruct rte_sched_cman_params cman_p);\n-#endif\n-\n int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);\n \n int cfg_load_subport_profile(struct rte_cfgfile *cfg,\ndiff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c\nindex 8a0fb8a374..e8b819ffb9 100644\n--- a/examples/qos_sched/init.c\n+++ b/examples/qos_sched/init.c\n@@ -201,78 +201,6 @@ static struct rte_sched_subport_profile_params\n \t},\n };\n \n-#ifdef RTE_SCHED_CMAN\n-struct rte_sched_cman_params cman_params = {\n-\t.cman_mode = RTE_SCHED_CMAN_RED,\n-\t.red_params = {\n-\t\t/* Traffic Class 0 Colors Green / Yellow / Red */\n-\t\t[0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\n-\t\t/* Traffic Class 1 - Colors Green / Yellow / Red */\n-\t\t[1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\n-\t\t/* Traffic Class 2 - Colors Green / Yellow / Red */\n-\t\t[2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\n-\t\t/* Traffic Class 3 - Colors Green / Yellow / Red */\n-\t\t[3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\n-\t\t/* Traffic Class 4 - Colors Green / Yellow / Red */\n-\t\t[4][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[4][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[4][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\n-\t\t/* Traffic Class 5 - Colors Green / Yellow / Red */\n-\t\t[5][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[5][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[5][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\n-\t\t/* Traffic Class 6 - Colors Green / Yellow / Red */\n-\t\t[6][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[6][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[6][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\n-\t\t/* Traffic Class 7 - Colors Green / Yellow / Red */\n-\t\t[7][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[7][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[7][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\n-\t\t/* Traffic Class 8 - Colors Green / Yellow / Red */\n-\t\t[8][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[8][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[8][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\n-\t\t/* Traffic Class 9 - Colors Green / Yellow / Red */\n-\t\t[9][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[9][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[9][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\n-\t\t/* Traffic Class 10 - Colors Green / Yellow / Red */\n-\t\t[10][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[10][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[10][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\n-\t\t/* Traffic Class 11 - Colors Green / Yellow / Red */\n-\t\t[11][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[11][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[11][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\n-\t\t/* Traffic Class 12 - Colors Green / Yellow / Red */\n-\t\t[12][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t\t[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n-\t},\n-};\n-#endif /* RTE_SCHED_CMAN */\n-\n struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {\n \t{\n \t\t.n_pipes_per_subport_enabled = 4096,\n@@ -281,9 +209,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {\n \t\t.n_pipe_profiles = sizeof(pipe_profiles) /\n \t\t\tsizeof(struct rte_sched_pipe_params),\n \t\t.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,\n-#ifdef RTE_SCHED_CMAN\n-\t\t.cman_params = &cman_params,\n-#endif /* RTE_SCHED_CMAN */\n+\t\t.cman_params = NULL,\n \t},\n };\n \ndiff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h\nindex 915311bac8..76a68f585f 100644\n--- a/examples/qos_sched/main.h\n+++ b/examples/qos_sched/main.h\n@@ -153,9 +153,7 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];\n extern uint32_t n_active_queues;\n \n extern struct rte_sched_port_params port_params;\n-#ifdef RTE_SCHED_CMAN\n extern struct rte_sched_cman_params cman_params;\n-#endif\n extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];\n \n int app_parse_args(int argc, char **argv);\ndiff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg\nindex d4b21c0170..c9ec187c93 100644\n--- a/examples/qos_sched/profile.cfg\n+++ b/examples/qos_sched/profile.cfg\n@@ -73,137 +73,4 @@ tc period = 40 ; Milliseconds\n \n tc 12 oversubscription weight = 1\n \n-tc 12 wrr weights = 1 1 1 1\n-\n-; RED params per traffic class and color (Green / Yellow / Red)\n-;[red]\n-;tc 0 wred min = 48 40 32\n-;tc 0 wred max = 64 64 64\n-;tc 0 wred inv prob = 10 10 10\n-;tc 0 wred weight = 9 9 9\n-\n-;tc 1 wred min = 48 40 32\n-;tc 1 wred max = 64 64 64\n-;tc 1 wred inv prob = 10 10 10\n-;tc 1 wred weight = 9 9 9\n-\n-;tc 2 wred min = 48 40 32\n-;tc 2 wred max = 64 64 64\n-;tc 2 wred inv prob = 10 10 10\n-;tc 2 wred weight = 9 9 9\n-\n-;tc 3 wred min = 48 40 32\n-;tc 3 wred max = 64 64 64\n-;tc 3 wred inv prob = 10 10 10\n-;tc 3 wred weight = 9 9 9\n-\n-;tc 4 wred min = 48 40 32\n-;tc 4 wred max = 64 64 64\n-;tc 4 wred inv prob = 10 10 10\n-;tc 4 wred weight = 9 9 9\n-\n-;tc 5 wred min = 48 40 32\n-;tc 5 wred max = 64 64 64\n-;tc 5 wred inv prob = 10 10 10\n-;tc 5 wred weight = 9 9 9\n-\n-;tc 6 wred min = 48 40 32\n-;tc 6 wred max = 64 64 64\n-;tc 6 wred inv prob = 10 10 10\n-;tc 6 wred weight = 9 9 9\n-\n-;tc 7 wred min = 48 40 32\n-;tc 7 wred max = 64 64 64\n-;tc 7 wred inv prob = 10 10 10\n-;tc 7 wred weight = 9 9 9\n-\n-;tc 8 wred min = 48 40 32\n-;tc 8 wred max = 64 64 64\n-;tc 8 wred inv prob = 10 10 10\n-;tc 8 wred weight = 9 9 9\n-\n-;tc 9 wred min = 48 40 32\n-;tc 9 wred max = 64 64 64\n-;tc 9 wred inv prob = 10 10 10\n-;tc 9 wred weight = 9 9 9\n-\n-;tc 10 wred min = 48 40 32\n-;tc 10 wred max = 64 64 64\n-;tc 10 wred inv prob = 10 10 10\n-;tc 10 wred weight = 9 9 9\n-\n-;tc 11 wred min = 48 40 32\n-;tc 11 wred max = 64 64 64\n-;tc 11 wred inv prob = 10 10 10\n-;tc 11 wred weight = 9 9 9\n-\n-;tc 12 wred min = 48 40 32\n-;tc 12 wred max = 64 64 64\n-;tc 12 wred inv prob = 10 10 10\n-;tc 12 wred weight = 9 9 9\n-\n-[pie]\n-tc 0 qdelay ref = 15\n-tc 0 max burst = 150\n-tc 0 update interval = 15\n-tc 0 tailq th = 64\n-\n-tc 1 qdelay ref = 15\n-tc 1 max burst = 150\n-tc 1 update interval = 15\n-tc 1 tailq th = 64\n-\n-tc 2 qdelay ref = 15\n-tc 2 max burst = 150\n-tc 2 update interval = 15\n-tc 2 tailq th = 64\n-\n-tc 3 qdelay ref = 15\n-tc 3 max burst = 150\n-tc 3 update interval = 15\n-tc 3 tailq th = 64\n-\n-tc 4 qdelay ref = 15\n-tc 4 max burst = 150\n-tc 4 update interval = 15\n-tc 4 tailq th = 64\n-\n-tc 5 qdelay ref = 15\n-tc 5 max burst = 150\n-tc 5 update interval = 15\n-tc 5 tailq th = 64\n-\n-tc 6 qdelay ref = 15\n-tc 6 max burst = 150\n-tc 6 update interval = 15\n-tc 6 tailq th = 64\n-\n-tc 7 qdelay ref = 15\n-tc 7 max burst = 150\n-tc 7 update interval = 15\n-tc 7 tailq th = 64\n-\n-tc 8 qdelay ref = 15\n-tc 8 max burst = 150\n-tc 8 update interval = 15\n-tc 8 tailq th = 64\n-\n-tc 9 qdelay ref = 15\n-tc 9 max burst = 150\n-tc 9 update interval = 15\n-tc 9 tailq th = 64\n-\n-tc 10 qdelay ref = 15\n-tc 10 max burst = 150\n-tc 10 update interval = 15\n-tc 10 tailq th = 64\n-\n-tc 11 qdelay ref = 15\n-tc 11 max burst = 150\n-tc 11 update interval = 15\n-tc 11 tailq th = 64\n-\n-tc 12 qdelay ref = 15\n-tc 12 max burst = 150\n-tc 12 update interval = 15\n-tc 12 tailq th = 64\n+tc 12 wrr weights = 1 1 1 1\n\\ No newline at end of file\ndiff --git a/examples/qos_sched/profile_pie.cfg b/examples/qos_sched/profile_pie.cfg\nnew file mode 100644\nindex 0000000000..241f748b33\n--- /dev/null\n+++ b/examples/qos_sched/profile_pie.cfg\n@@ -0,0 +1,142 @@\n+; SPDX-License-Identifier: BSD-3-Clause\n+; Copyright(c) 2010-2019 Intel Corporation.\n+\n+; This file enables the following hierarchical scheduler configuration for each\n+; 10GbE output port:\n+;\t* Single subport (subport 0):\n+;\t\t- Subport rate set to 100% of port rate\n+;\t\t- Each of the 13 traffic classes has rate set to 100% of port rate\n+;\t* 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:\n+;\t\t- Pipe rate set to 1/4K of port rate\n+;\t\t- Each of the 13 traffic classes has rate set to 100% of pipe rate\n+;\t\t- Within lowest priority traffic class (best-effort), the byte-level\n+;\t\t WRR weights for the 4 queues of best effort traffic class are set\n+;\t\t to 1:1:1:1\n+;\n+; For more details, please refer to chapter \"Quality of Service (QoS) Framework\"\n+; of Data Plane Development Kit (DPDK) Programmer's Guide.\n+\n+; Port configuration\n+[port]\n+frame overhead = 24\n+number of subports per port = 1\n+\n+; Subport configuration\n+[subport 0]\n+number of pipes per subport = 4096\n+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64\n+\n+subport 0-8 = 0 ; These subports are configured with subport profile 0\n+\n+[subport profile 0]\n+tb rate = 1250000000 ; Bytes per second\n+tb size = 1000000 ; Bytes\n+\n+tc 0 rate = 1250000000 ; Bytes per second\n+tc 1 rate = 1250000000 ; Bytes per second\n+tc 2 rate = 1250000000 ; Bytes per second\n+tc 3 rate = 1250000000 ; Bytes per second\n+tc 4 rate = 1250000000 ; Bytes per second\n+tc 5 rate = 1250000000 ; Bytes per second\n+tc 6 rate = 1250000000 ; Bytes per second\n+tc 7 rate = 1250000000 ; Bytes per second\n+tc 8 rate = 1250000000 ; Bytes per second\n+tc 9 rate = 1250000000 ; Bytes per second\n+tc 10 rate = 1250000000 ; Bytes per second\n+tc 11 rate = 1250000000 ; Bytes per second\n+tc 12 rate = 1250000000 ; Bytes per second\n+\n+tc period = 10 ; Milliseconds\n+\n+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0\n+\n+; Pipe configuration\n+[pipe profile 0]\n+tb rate = 305175 ; Bytes per second\n+tb size = 1000000 ; Bytes\n+\n+tc 0 rate = 305175 ; Bytes per second\n+tc 1 rate = 305175 ; Bytes per second\n+tc 2 rate = 305175 ; Bytes per second\n+tc 3 rate = 305175 ; Bytes per second\n+tc 4 rate = 305175 ; Bytes per second\n+tc 5 rate = 305175 ; Bytes per second\n+tc 6 rate = 305175 ; Bytes per second\n+tc 7 rate = 305175 ; Bytes per second\n+tc 8 rate = 305175 ; Bytes per second\n+tc 9 rate = 305175 ; Bytes per second\n+tc 10 rate = 305175 ; Bytes per second\n+tc 11 rate = 305175 ; Bytes per second\n+tc 12 rate = 305175 ; Bytes per second\n+\n+tc period = 40 ; Milliseconds\n+\n+tc 12 oversubscription weight = 1\n+\n+tc 12 wrr weights = 1 1 1 1\n+\n+[pie]\n+tc 0 qdelay ref = 15\n+tc 0 max burst = 150\n+tc 0 update interval = 15\n+tc 0 tailq th = 64\n+\n+tc 1 qdelay ref = 15\n+tc 1 max burst = 150\n+tc 1 update interval = 15\n+tc 1 tailq th = 64\n+\n+tc 2 qdelay ref = 15\n+tc 2 max burst = 150\n+tc 2 update interval = 15\n+tc 2 tailq th = 64\n+\n+tc 3 qdelay ref = 15\n+tc 3 max burst = 150\n+tc 3 update interval = 15\n+tc 3 tailq th = 64\n+\n+tc 4 qdelay ref = 15\n+tc 4 max burst = 150\n+tc 4 update interval = 15\n+tc 4 tailq th = 64\n+\n+tc 5 qdelay ref = 15\n+tc 5 max burst = 150\n+tc 5 update interval = 15\n+tc 5 tailq th = 64\n+\n+tc 6 qdelay ref = 15\n+tc 6 max burst = 150\n+tc 6 update interval = 15\n+tc 6 tailq th = 64\n+\n+tc 7 qdelay ref = 15\n+tc 7 max burst = 150\n+tc 7 update interval = 15\n+tc 7 tailq th = 64\n+\n+tc 8 qdelay ref = 15\n+tc 8 max burst = 150\n+tc 8 update interval = 15\n+tc 8 tailq th = 64\n+\n+tc 9 qdelay ref = 15\n+tc 9 max burst = 150\n+tc 9 update interval = 15\n+tc 9 tailq th = 64\n+\n+tc 10 qdelay ref = 15\n+tc 10 max burst = 150\n+tc 10 update interval = 15\n+tc 10 tailq th = 64\n+\n+tc 11 qdelay ref = 15\n+tc 11 max burst = 150\n+tc 11 update interval = 15\n+tc 11 tailq th = 64\n+\n+tc 12 qdelay ref = 15\n+tc 12 max burst = 150\n+tc 12 update interval = 15\n+tc 12 tailq th = 64\ndiff --git a/examples/qos_sched/profile_red.cfg b/examples/qos_sched/profile_red.cfg\nnew file mode 100644\nindex 0000000000..4486d2799e\n--- /dev/null\n+++ b/examples/qos_sched/profile_red.cfg\n@@ -0,0 +1,143 @@\n+; SPDX-License-Identifier: BSD-3-Clause\n+; Copyright(c) 2010-2019 Intel Corporation.\n+\n+; This file enables the following hierarchical scheduler configuration for each\n+; 10GbE output port:\n+;\t* Single subport (subport 0):\n+;\t\t- Subport rate set to 100% of port rate\n+;\t\t- Each of the 13 traffic classes has rate set to 100% of port rate\n+;\t* 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:\n+;\t\t- Pipe rate set to 1/4K of port rate\n+;\t\t- Each of the 13 traffic classes has rate set to 100% of pipe rate\n+;\t\t- Within lowest priority traffic class (best-effort), the byte-level\n+;\t\t WRR weights for the 4 queues of best effort traffic class are set\n+;\t\t to 1:1:1:1\n+;\n+; For more details, please refer to chapter \"Quality of Service (QoS) Framework\"\n+; of Data Plane Development Kit (DPDK) Programmer's Guide.\n+\n+; Port configuration\n+[port]\n+frame overhead = 24\n+number of subports per port = 1\n+\n+; Subport configuration\n+[subport 0]\n+number of pipes per subport = 4096\n+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64\n+\n+subport 0-8 = 0 ; These subports are configured with subport profile 0\n+\n+[subport profile 0]\n+tb rate = 1250000000 ; Bytes per second\n+tb size = 1000000 ; Bytes\n+\n+tc 0 rate = 1250000000 ; Bytes per second\n+tc 1 rate = 1250000000 ; Bytes per second\n+tc 2 rate = 1250000000 ; Bytes per second\n+tc 3 rate = 1250000000 ; Bytes per second\n+tc 4 rate = 1250000000 ; Bytes per second\n+tc 5 rate = 1250000000 ; Bytes per second\n+tc 6 rate = 1250000000 ; Bytes per second\n+tc 7 rate = 1250000000 ; Bytes per second\n+tc 8 rate = 1250000000 ; Bytes per second\n+tc 9 rate = 1250000000 ; Bytes per second\n+tc 10 rate = 1250000000 ; Bytes per second\n+tc 11 rate = 1250000000 ; Bytes per second\n+tc 12 rate = 1250000000 ; Bytes per second\n+\n+tc period = 10 ; Milliseconds\n+\n+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0\n+\n+; Pipe configuration\n+[pipe profile 0]\n+tb rate = 305175 ; Bytes per second\n+tb size = 1000000 ; Bytes\n+\n+tc 0 rate = 305175 ; Bytes per second\n+tc 1 rate = 305175 ; Bytes per second\n+tc 2 rate = 305175 ; Bytes per second\n+tc 3 rate = 305175 ; Bytes per second\n+tc 4 rate = 305175 ; Bytes per second\n+tc 5 rate = 305175 ; Bytes per second\n+tc 6 rate = 305175 ; Bytes per second\n+tc 7 rate = 305175 ; Bytes per second\n+tc 8 rate = 305175 ; Bytes per second\n+tc 9 rate = 305175 ; Bytes per second\n+tc 10 rate = 305175 ; Bytes per second\n+tc 11 rate = 305175 ; Bytes per second\n+tc 12 rate = 305175 ; Bytes per second\n+\n+tc period = 40 ; Milliseconds\n+\n+tc 12 oversubscription weight = 1\n+\n+tc 12 wrr weights = 1 1 1 1\n+\n+; RED params per traffic class and color (Green / Yellow / Red)\n+[red]\n+tc 0 wred min = 48 40 32\n+tc 0 wred max = 64 64 64\n+tc 0 wred inv prob = 10 10 10\n+tc 0 wred weight = 9 9 9\n+\n+tc 1 wred min = 48 40 32\n+tc 1 wred max = 64 64 64\n+tc 1 wred inv prob = 10 10 10\n+tc 1 wred weight = 9 9 9\n+\n+tc 2 wred min = 48 40 32\n+tc 2 wred max = 64 64 64\n+tc 2 wred inv prob = 10 10 10\n+tc 2 wred weight = 9 9 9\n+\n+tc 3 wred min = 48 40 32\n+tc 3 wred max = 64 64 64\n+tc 3 wred inv prob = 10 10 10\n+tc 3 wred weight = 9 9 9\n+\n+tc 4 wred min = 48 40 32\n+tc 4 wred max = 64 64 64\n+tc 4 wred inv prob = 10 10 10\n+tc 4 wred weight = 9 9 9\n+\n+tc 5 wred min = 48 40 32\n+tc 5 wred max = 64 64 64\n+tc 5 wred inv prob = 10 10 10\n+tc 5 wred weight = 9 9 9\n+\n+tc 6 wred min = 48 40 32\n+tc 6 wred max = 64 64 64\n+tc 6 wred inv prob = 10 10 10\n+tc 6 wred weight = 9 9 9\n+\n+tc 7 wred min = 48 40 32\n+tc 7 wred max = 64 64 64\n+tc 7 wred inv prob = 10 10 10\n+tc 7 wred weight = 9 9 9\n+\n+tc 8 wred min = 48 40 32\n+tc 8 wred max = 64 64 64\n+tc 8 wred inv prob = 10 10 10\n+tc 8 wred weight = 9 9 9\n+\n+tc 9 wred min = 48 40 32\n+tc 9 wred max = 64 64 64\n+tc 9 wred inv prob = 10 10 10\n+tc 9 wred weight = 9 9 9\n+\n+tc 10 wred min = 48 40 32\n+tc 10 wred max = 64 64 64\n+tc 10 wred inv prob = 10 10 10\n+tc 10 wred weight = 9 9 9\n+\n+tc 11 wred min = 48 40 32\n+tc 11 wred max = 64 64 64\n+tc 11 wred inv prob = 10 10 10\n+tc 11 wred weight = 9 9 9\n+\n+tc 12 wred min = 48 40 32\n+tc 12 wred max = 64 64 64\n+tc 12 wred inv prob = 10 10 10\n+tc 12 wred weight = 9 9 9\ndiff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c\nindex 599c7e9536..c5fa9e4582 100644\n--- a/lib/sched/rte_sched.c\n+++ b/lib/sched/rte_sched.c\n@@ -81,13 +81,11 @@ struct rte_sched_queue {\n \n struct rte_sched_queue_extra {\n \tstruct rte_sched_queue_stats stats;\n-#ifdef RTE_SCHED_CMAN\n \tRTE_STD_C11\n \tunion {\n \t\tstruct rte_red red;\n \t\tstruct rte_pie pie;\n \t};\n-#endif\n };\n \n enum grinder_state {\n@@ -179,7 +177,6 @@ struct rte_sched_subport {\n \t/* Pipe queues size */\n \tuint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n \n-#ifdef RTE_SCHED_CMAN\n \tbool cman_enabled;\n \tenum rte_sched_cman_mode cman;\n \n@@ -188,7 +185,6 @@ struct rte_sched_subport {\n \t\tstruct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];\n \t\tstruct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n \t};\n-#endif\n \n \t/* Scheduling loop detection */\n \tuint32_t pipe_loop;\n@@ -1084,7 +1080,6 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)\n \trte_free(port);\n }\n \n-#ifdef RTE_SCHED_CMAN\n static int\n rte_sched_red_config(struct rte_sched_port *port,\n \tstruct rte_sched_subport *s,\n@@ -1166,7 +1161,6 @@ rte_sched_cman_config(struct rte_sched_port *port,\n \n \treturn -EINVAL;\n }\n-#endif\n \n int\n rte_sched_subport_tc_ov_config(struct rte_sched_port *port,\n@@ -1285,7 +1279,6 @@ rte_sched_subport_config(struct rte_sched_port *port,\n \t\t/* TC oversubscription is enabled by default */\n \t\ts->tc_ov_enabled = 1;\n \n-#ifdef RTE_SCHED_CMAN\n \t\tif (params->cman_params != NULL) {\n \t\t\ts->cman_enabled = true;\n \t\t\tstatus = rte_sched_cman_config(port, s, params, n_subports);\n@@ -1297,7 +1290,6 @@ rte_sched_subport_config(struct rte_sched_port *port,\n \t\t} else {\n \t\t\ts->cman_enabled = false;\n \t\t}\n-#endif\n \n \t\t/* Scheduling loop detection */\n \t\ts->pipe_loop = RTE_SCHED_PIPE_INVALID;\n@@ -1823,7 +1815,7 @@ rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port,\n \tstruct rte_sched_subport *subport,\n \tuint32_t qindex,\n \tstruct rte_mbuf *pkt,\n-\t__rte_unused uint32_t n_pkts_cman_dropped)\n+\tuint32_t n_pkts_cman_dropped)\n {\n \tuint32_t tc_index = rte_sched_port_pipe_tc(port, qindex);\n \tuint32_t pkt_len = pkt->pkt_len;\n@@ -1849,21 +1841,17 @@ static inline void\n rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport,\n \tuint32_t qindex,\n \tstruct rte_mbuf *pkt,\n-\t__rte_unused uint32_t n_pkts_cman_dropped)\n+\tuint32_t n_pkts_cman_dropped)\n {\n \tstruct rte_sched_queue_extra *qe = subport->queue_extra + qindex;\n \tuint32_t pkt_len = pkt->pkt_len;\n \n \tqe->stats.n_pkts_dropped += 1;\n \tqe->stats.n_bytes_dropped += pkt_len;\n-#ifdef RTE_SCHED_CMAN\n \tif (subport->cman_enabled)\n \t\tqe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;\n-#endif\n }\n \n-#ifdef RTE_SCHED_CMAN\n-\n static inline int\n rte_sched_port_cman_drop(struct rte_sched_port *port,\n \tstruct rte_sched_subport *subport,\n@@ -1908,13 +1896,11 @@ static inline void\n rte_sched_port_red_set_queue_empty_timestamp(struct rte_sched_port *port,\n \tstruct rte_sched_subport *subport, uint32_t qindex)\n {\n-\tif (subport->cman_enabled) {\n+\tif (subport->cman_enabled && subport->cman == RTE_SCHED_CMAN_RED) {\n \t\tstruct rte_sched_queue_extra *qe = subport->queue_extra + qindex;\n-\t\tif (subport->cman == RTE_SCHED_CMAN_RED) {\n-\t\t\tstruct rte_red *red = &qe->red;\n+\t\tstruct rte_red *red = &qe->red;\n \n-\t\t\trte_red_mark_queue_empty(red, port->time);\n-\t\t}\n+\t\trte_red_mark_queue_empty(red, port->time);\n \t}\n }\n \n@@ -1933,29 +1919,6 @@ uint32_t qindex, uint32_t pkt_len, uint64_t time) {\n \t}\n }\n \n-#else\n-\n-static inline int rte_sched_port_cman_drop(struct rte_sched_port *port __rte_unused,\n-\tstruct rte_sched_subport *subport __rte_unused,\n-\tstruct rte_mbuf *pkt __rte_unused,\n-\tuint32_t qindex __rte_unused,\n-\tuint16_t qlen __rte_unused)\n-{\n-\treturn 0;\n-}\n-\n-#define rte_sched_port_red_set_queue_empty_timestamp(port, subport, qindex)\n-\n-static inline void\n-rte_sched_port_pie_dequeue(struct rte_sched_subport *subport __rte_unused,\n-\tuint32_t qindex __rte_unused,\n-\tuint32_t pkt_len __rte_unused,\n-\tuint64_t time __rte_unused) {\n-\t/* do-nothing when RTE_SCHED_CMAN not defined */\n-}\n-\n-#endif /* RTE_SCHED_CMAN */\n-\n #ifdef RTE_SCHED_DEBUG\n \n static inline void\n", "prefixes": [ "v9" ] }