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GET /api/patches/113640/?format=api
{ "id": 113640, "url": "https://patches.dpdk.org/api/patches/113640/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220702160340.1591058-5-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220702160340.1591058-5-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220702160340.1591058-5-timothy.mcdaniel@intel.com", "date": "2022-07-02T16:03:39", "name": "[v2,4/5] event/dlb2: fix cq depth override credit deadlock", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "aa6defd05dbbb704153f4832a5481169a48a5e8f", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220702160340.1591058-5-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 23866, "url": "https://patches.dpdk.org/api/series/23866/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=23866", "date": "2022-07-02T16:03:35", "name": "DLB2 Bug Fixes", "version": 2, "mbox": "https://patches.dpdk.org/series/23866/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/113640/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/113640/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 24DFBA0093;\n\tSat, 2 Jul 2022 18:04:11 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CBEFB42B71;\n\tSat, 2 Jul 2022 18:03:50 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 5A57540E50\n for <dev@dpdk.org>; Sat, 2 Jul 2022 18:03:46 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 02 Jul 2022 09:03:44 -0700", "from txanpdk03.an.intel.com ([10.123.117.78])\n by fmsmga008.fm.intel.com with ESMTP; 02 Jul 2022 09:03:44 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1656777826; x=1688313826;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=iPgi5J2UBlJ7Taa4Usg5YEAsg77772/o3ji4TnWZ49k=;\n b=Nfi8PZR4dvSv5y3GNjGjESD1ZOmp7XZxIKOpGKAGf/cfZtwERtIajbm7\n fWRk50/oEEN2NNdFphkZwZ2pq6FSrvgDXIAwcnQZxEHYVzrqfcQ7MR6QO\n SDXfRM0GDL9jMrrXuCLw/wch3mW3sRArX5CSLr7d62k2pP2IfPxr7Bh/V\n Igpw4YjbZDZG0ozm1wE0JJgMVWOQuaA5kbx4v0dnehqN1cIi/a8ilKN/G\n 3fi+7iN1q3X1WNCDa3kzqGmhaAL1Id3U7dL53WK9P5wzkgWe266moA/LO\n IG38dbonCPVszYgGKsBdmZEPFrFHMahzHOAWTDIEQIvr1iQZG5zQhphpd A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10396\"; a=\"271616952\"", "E=Sophos;i=\"5.92,240,1650956400\"; d=\"scan'208\";a=\"271616952\"", "E=Sophos;i=\"5.92,240,1650956400\"; d=\"scan'208\";a=\"648776830\"" ], "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "jerinj@marvell.com", "Cc": "dev@dpdk.org,\n\ttimothy.mcdaniel@intel.com", "Subject": "[PATCH v2 4/5] event/dlb2: fix cq depth override credit deadlock", "Date": "Sat, 2 Jul 2022 11:03:39 -0500", "Message-Id": "<20220702160340.1591058-5-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 2.23.0", "In-Reply-To": "<20220702160340.1591058-1-timothy.mcdaniel@intel.com>", "References": "<20220629153638.1269743-1-timothy.mcdaniel@intel.com>\n <20220702160340.1591058-1-timothy.mcdaniel@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This commit fixes a bug, where we could encounter a credit\ndeadlock due to changing the CQ depth. To remedy this situation,\nthe commit reduces the maximum CQ depth from 1024 to 128,\nand also allows configuring the maximum enqueue depth. Maximum\nenqueue depth must be tuned to the CQ depth, if the CQ depth\nis increased.\n\nFixes: 86fe66d45667 (\"event/dlb2: allow CQ depths up to 1024\")\nCc: timothy.mcdaniel@intel.com\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/dlb2.c | 51 +++++++++++++++++++++++++++++++++\n drivers/event/dlb2/dlb2_priv.h | 8 +++++-\n drivers/event/dlb2/pf/dlb2_pf.c | 3 +-\n 3 files changed, 60 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex b50cd8e5ce..8a68c25c93 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -326,6 +326,36 @@ set_max_cq_depth(const char *key __rte_unused,\n \treturn 0;\n }\n \n+static int\n+set_max_enq_depth(const char *key __rte_unused,\n+\t\t const char *value,\n+\t\t void *opaque)\n+{\n+\tint *max_enq_depth = opaque;\n+\tint ret;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = dlb2_string_to_int(max_enq_depth, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif (*max_enq_depth < DLB2_MIN_ENQ_DEPTH_OVERRIDE ||\n+\t *max_enq_depth > DLB2_MAX_ENQ_DEPTH_OVERRIDE ||\n+\t !rte_is_power_of_2(*max_enq_depth)) {\n+\t\tDLB2_LOG_ERR(\"dlb2: max_enq_depth %d and %d and a power of 2\\n\",\n+\t\tDLB2_MIN_ENQ_DEPTH_OVERRIDE,\n+\t\tDLB2_MAX_ENQ_DEPTH_OVERRIDE);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+\n static int\n set_max_num_events(const char *key __rte_unused,\n \t\t const char *value,\n@@ -4514,6 +4544,15 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev,\n \n \tevdev_dlb2_default_info.max_event_port_dequeue_depth = dlb2->max_cq_depth;\n \n+\tif (dlb2_args->max_enq_depth != 0)\n+\t\tdlb2->max_enq_depth = dlb2_args->max_enq_depth;\n+\telse\n+\t\tdlb2->max_enq_depth = DLB2_DEFAULT_CQ_DEPTH;\n+\n+\tevdev_dlb2_default_info.max_event_port_enqueue_depth =\n+\t\tdlb2->max_enq_depth;\n+\n+\n \terr = dlb2_iface_open(&dlb2->qm_instance, name);\n \tif (err < 0) {\n \t\tDLB2_LOG_ERR(\"could not open event hardware device, err=%d\\n\",\n@@ -4650,6 +4689,7 @@ dlb2_parse_params(const char *params,\n \t\t\t\t\t DLB2_DEPTH_THRESH_ARG,\n \t\t\t\t\t DLB2_VECTOR_OPTS_ENAB_ARG,\n \t\t\t\t\t DLB2_MAX_CQ_DEPTH,\n+\t\t\t\t\t DLB2_MAX_ENQ_DEPTH,\n \t\t\t\t\t DLB2_CQ_WEIGHT,\n \t\t\t\t\t DLB2_PORT_COS,\n \t\t\t\t\t DLB2_COS_BW,\n@@ -4789,6 +4829,17 @@ dlb2_parse_params(const char *params,\n \t\t\t\treturn ret;\n \t\t\t}\n \n+\t\t\tret = rte_kvargs_process(kvlist,\n+\t\t\t\t\t\t DLB2_MAX_ENQ_DEPTH,\n+\t\t\t\t\t\t set_max_enq_depth,\n+\t\t\t\t\t\t &dlb2_args->max_enq_depth);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing vector opts enabled\",\n+\t\t\t\t\t name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n \t\t\tret = rte_kvargs_process(kvlist,\n \t\t\t\t\tDLB2_CQ_WEIGHT,\n \t\t\t\t\tset_cq_weight,\ndiff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h\nindex 8744efa79d..1edea83a5b 100644\n--- a/drivers/event/dlb2/dlb2_priv.h\n+++ b/drivers/event/dlb2/dlb2_priv.h\n@@ -29,7 +29,10 @@\n #define DLB2_SW_CREDIT_C_QUANTA_DEFAULT 256 /* Consumer */\n #define DLB2_DEPTH_THRESH_DEFAULT 256\n #define DLB2_MIN_CQ_DEPTH_OVERRIDE 32\n-#define DLB2_MAX_CQ_DEPTH_OVERRIDE 1024\n+#define DLB2_MAX_CQ_DEPTH_OVERRIDE 128\n+#define DLB2_MIN_ENQ_DEPTH_OVERRIDE 32\n+#define DLB2_MAX_ENQ_DEPTH_OVERRIDE 1024\n+\n \n /* command line arg strings */\n #define NUMA_NODE_ARG \"numa_node\"\n@@ -44,6 +47,7 @@\n #define DLB2_DEPTH_THRESH_ARG \"default_depth_thresh\"\n #define DLB2_VECTOR_OPTS_ENAB_ARG \"vector_opts_enable\"\n #define DLB2_MAX_CQ_DEPTH \"max_cq_depth\"\n+#define DLB2_MAX_ENQ_DEPTH \"max_enqueue_depth\"\n #define DLB2_CQ_WEIGHT \"cq_weight\"\n #define DLB2_PORT_COS \"port_cos\"\n #define DLB2_COS_BW \"cos_bw\"\n@@ -585,6 +589,7 @@ struct dlb2_eventdev {\n \tint num_dir_credits_override;\n \tbool vector_opts_enabled;\n \tint max_cq_depth;\n+\tint max_enq_depth;\n \tvolatile enum dlb2_run_state run_state;\n \tuint16_t num_dir_queues; /* total num of evdev dir queues requested */\n \tunion {\n@@ -660,6 +665,7 @@ struct dlb2_devargs {\n \tint default_depth_thresh;\n \tbool vector_opts_enabled;\n \tint max_cq_depth;\n+\tint max_enq_depth;\n \tstruct dlb2_cq_weight cq_weight;\n \tstruct dlb2_port_cos port_cos;\n \tstruct dlb2_cos_bw cos_bw;\ndiff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c\nindex 0627f06a6e..086d4a1cc7 100644\n--- a/drivers/event/dlb2/pf/dlb2_pf.c\n+++ b/drivers/event/dlb2/pf/dlb2_pf.c\n@@ -708,7 +708,8 @@ dlb2_eventdev_pci_init(struct rte_eventdev *eventdev)\n \t\t.sw_credit_quanta = DLB2_SW_CREDIT_QUANTA_DEFAULT,\n \t\t.hw_credit_quanta = DLB2_SW_CREDIT_BATCH_SZ,\n \t\t.default_depth_thresh = DLB2_DEPTH_THRESH_DEFAULT,\n-\t\t.max_cq_depth = DLB2_DEFAULT_CQ_DEPTH\n+\t\t.max_cq_depth = DLB2_DEFAULT_CQ_DEPTH,\n+\t\t.max_enq_depth = DLB2_MAX_ENQUEUE_DEPTH\n \t};\n \tstruct dlb2_eventdev *dlb2;\n \n", "prefixes": [ "v2", "4/5" ] }