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GET /api/patches/113060/?format=api
{ "id": 113060, "url": "https://patches.dpdk.org/api/patches/113060/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220618090258.91157-4-lizh@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220618090258.91157-4-lizh@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220618090258.91157-4-lizh@nvidia.com", "date": "2022-06-18T09:02:46", "name": "[v4,03/15] common/mlx5: add DevX API to move QP to reset state", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7d16a75ab8b2e712d59ae1da0b946682e272f114", "submitter": { "id": 1967, "url": "https://patches.dpdk.org/api/people/1967/?format=api", "name": "Li Zhang", "email": "lizh@nvidia.com" }, "delegate": { "id": 2642, "url": "https://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220618090258.91157-4-lizh@nvidia.com/mbox/", "series": [ { "id": 23622, "url": "https://patches.dpdk.org/api/series/23622/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=23622", "date": "2022-06-18T09:02:43", "name": "mlx5/vdpa: optimize live migration time", "version": 4, "mbox": "https://patches.dpdk.org/series/23622/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/113060/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/113060/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 586D6A0032;\n\tSat, 18 Jun 2022 11:03:42 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D95124282C;\n\tSat, 18 Jun 2022 11:03:29 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2066.outbound.protection.outlook.com [40.107.92.66])\n by mails.dpdk.org (Postfix) with ESMTP id 7D7F84282C\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Li Zhang <lizh@nvidia.com>", "To": "<orika@nvidia.com>, <viacheslavo@nvidia.com>, <matan@nvidia.com>,\n <shahafs@nvidia.com>", "CC": "<dev@dpdk.org>, <thomas@monjalon.net>, <rasland@nvidia.com>,\n <roniba@nvidia.com>, <maxime.coquelin@redhat.com>, Yajun Wu\n <yajunw@nvidia.com>", "Subject": "[PATCH v4 03/15] common/mlx5: add DevX API to move QP to reset state", "Date": "Sat, 18 Jun 2022 12:02:46 +0300", "Message-ID": "<20220618090258.91157-4-lizh@nvidia.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20220618090258.91157-1-lizh@nvidia.com>", "References": "<20220408075606.33056-1-lizh@nvidia.com>\n <20220618090258.91157-1-lizh@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "a81f132a-db5b-455f-3735-08da510967a1", "X-MS-TrafficTypeDiagnostic": "MN0PR12MB5713:EE_", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <MN0PR12MB57134BCBC61B9F7EA9433CA7BFAE9@MN0PR12MB5713.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Xw8ZvZCY5rcYXtZWjknJxD0+axtwaJb1loFJcvFe6ykcP3IzIWJvgskBjCg9uS5hDfULbRWU/qKWFKz4xLF31f1FNorgf/lceqiXOrglok+M3KlGIDpl6Q4NGvqZCTRTKd2NfKjl4+X+390p0K+sa8NvDaMtkKT0TMoI/5KqmVNOMa2zdCfA/NFc+M+/nWAtgmMYYqkYywzaKrXXUXyGg7jc/ux5dUXhUjYopPD55NqUxOS+61aJM7vd2veZk2ytme6qgqlUw2Q4FICRO5BQb+FK1c4swWxCilf8xRVkXvs6h/eocAg3DKfHkn+/4jyco/VxKLJfTYKAHPXU+XFY1ZNfIv/HL5Qf1AyOAe4rx4Jk/Q6wguqyTM1wEGuXCAkleNKIYvW8vjogMJ/wZ1IyUV3RgeHz6LofevyqSTe6b0GYSr4a3ah9A2/dUdmay5EwWsJ7y9oOqr69bA2mMLYztVDBj1xIkgKGv79cjYp9QXHivF7nXQZcWf5ERd2gvX4/ZYm8cKpzeSJcZZROhOlR2eMI99q7Wju3vtwumpuV5MLnRr/7EgXvgQ1g+AbvIt4+koCpBwkAV9xkAwY4mwuS8jvXVsTelb0sSIvN2rxZEPsqf83Zkgrcxja3PMJvG2IROGgsXZ3svRbUUtXe6GthqwhSPGE0ou8kOis4PjI4/PHPQc+5L492zktXMWZtemKsOgzcIrwrZ5j50wCEqRiVQA==", "X-Forefront-Antispam-Report": "CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230016)(4636009)(40470700004)(46966006)(36840700001)(107886003)(81166007)(16526019)(186003)(336012)(47076005)(426003)(1076003)(356005)(2616005)(82310400005)(86362001)(55016003)(36860700001)(8676002)(70206006)(5660300002)(8936002)(40460700003)(7696005)(2906002)(316002)(4326008)(6286002)(498600001)(26005)(70586007)(36756003)(6636002)(54906003)(110136005)(6666004)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Jun 2022 09:03:26.0270 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a81f132a-db5b-455f-3735-08da510967a1", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT004.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN0PR12MB5713", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Yajun Wu <yajunw@nvidia.com>\n\nSupport set QP to RESET state.\n\nSigned-off-by: Yajun Wu <yajunw@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 7 +++++++\n drivers/common/mlx5/mlx5_prm.h | 17 +++++++++++++++++\n 2 files changed, 24 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex c6bdbc12bb..1d6d6578d6 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -2264,11 +2264,13 @@ mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,\n \t\tuint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];\n \t\tuint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];\n \t\tuint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];\n+\t\tuint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)];\n \t} in;\n \tunion {\n \t\tuint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];\n \t\tuint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];\n \t\tuint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];\n+\t\tuint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)];\n \t} out;\n \tvoid *qpc;\n \tint ret;\n@@ -2311,6 +2313,11 @@ mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,\n \t\tinlen = sizeof(in.rtr2rts);\n \t\toutlen = sizeof(out.rtr2rts);\n \t\tbreak;\n+\tcase MLX5_CMD_OP_QP_2RST:\n+\t\tMLX5_SET(2rst_qp_in, &in, qpn, qp->id);\n+\t\tinlen = sizeof(in.qp2rst);\n+\t\toutlen = sizeof(out.qp2rst);\n+\t\tbreak;\n \tdefault:\n \t\tDRV_LOG(ERR, \"Invalid or unsupported QP modify op %u.\",\n \t\t\tqp_st_mod_op);\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex bc3e70a1d1..8a2f55c33e 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -3657,6 +3657,23 @@ struct mlx5_ifc_init2init_qp_in_bits {\n \tu8 reserved_at_800[0x80];\n };\n \n+struct mlx5_ifc_2rst_qp_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n+struct mlx5_ifc_2rst_qp_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 vhca_tunnel_id[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_80[0x8];\n+\tu8 qpn[0x18];\n+\tu8 reserved_at_a0[0x20];\n+};\n+\n struct mlx5_ifc_dealloc_pd_out_bits {\n \tu8 status[0x8];\n \tu8 reserved_0[0x18];\n", "prefixes": [ "v4", "03/15" ] }