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GET /api/patches/112768/?format=api
{ "id": 112768, "url": "https://patches.dpdk.org/api/patches/112768/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220615125836.391771-4-spiked@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220615125836.391771-4-spiked@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220615125836.391771-4-spiked@nvidia.com", "date": "2022-06-15T12:58:33", "name": "[v8,3/6] net/mlx5: add LWM event handling support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "02b494cbe7b9801ae228d028e247380f4eaaa2c8", "submitter": { "id": 2637, "url": "https://patches.dpdk.org/api/people/2637/?format=api", "name": "Spike Du", "email": "spiked@nvidia.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220615125836.391771-4-spiked@nvidia.com/mbox/", "series": [ { "id": 23538, "url": "https://patches.dpdk.org/api/series/23538/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=23538", "date": "2022-06-15T12:58:30", "name": "introduce per-queue available descriptor threshold and host shaper", "version": 8, "mbox": "https://patches.dpdk.org/series/23538/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/112768/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/112768/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A6C91A0548;\n\tWed, 15 Jun 2022 15:09:37 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0C34942B82;\n\tWed, 15 Jun 2022 15:09:19 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2045.outbound.protection.outlook.com [40.107.236.45])\n by mails.dpdk.org (Postfix) with ESMTP id EF08642B82\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Spike Du <spiked@nvidia.com>", "To": "<matan@nvidia.com>, <viacheslavo@nvidia.com>, <orika@nvidia.com>,\n <thomas@monjalon.net>, Shahaf Shuler <shahafs@nvidia.com>", "CC": "<andrew.rybchenko@oktetlabs.ru>, <stephen@networkplumber.org>,\n <mb@smartsharesystems.com>, <dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[PATCH v8 3/6] net/mlx5: add LWM event handling support", "Date": "Wed, 15 Jun 2022 15:58:33 +0300", "Message-ID": "<20220615125836.391771-4-spiked@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20220615125836.391771-1-spiked@nvidia.com>", "References": "<20220614120134.1828188-2-spiked@nvidia.com>\n <20220615125836.391771-1-spiked@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "62e412a7-7e1e-4c2f-b3d6-08da4eced3c5", "X-MS-TrafficTypeDiagnostic": "CH2PR12MB5547:EE_", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <CH2PR12MB5547635C84BB7276C2AFE066A8AD9@CH2PR12MB5547.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n yn4aiJ+RAFWAnzFw5WUPzzvy5AXuOG+H6DFBScr4yYQGyL7IJqFEKAXSJvspPP5haMkCpuAsCag1t6BdYezZCiXbdlpnt8sDmyASUkzYqEc9oyVF9yE/q1YDxURleEzaX/JQ1DhxSI/XRIcE6PQ3YxiR05UwsrYnDotSi+AlwmlDXXzYgcfQv/eNisL8vglKRToPzyQXn8RWcimP6S+4pN7ogSb9rhcekAcmMz0iL5bhKFr8S0KLxCk/OXsXe2KUCj4j7OT4Tl/aL/pFLnBjU3+AAyYa0ZGzmWCEAPXkT66qczltepHdYjJ84uqkWqAZ6I5/esHnkCsnQGxEfWDlhUy3skYOLlruhJFApeMnrR5fKV+TtDYlcMrQVR+LOpDs0v8A53nX2PAlgrBYL6oCWJ4sjK7U/CeZjApbVR/uUB0lfVUHatFEZuR6EDDhK+Xz1YlibDEs0LykR0kdj6NJt6ir2lUKAycnBs1taOzDSwoLdBNtuZE/JKRF7mLmyQemcutAUHrkxon6EzBAOGMP/VSIwc42jZJfCsG0hjiS0JomAwtDKxeROtTo1qB+Y/3+q61TpqX0vP/gSTl5V1/ogCOHSst92gQspkxS6IHD13VPuXBgHWQGexCLUnnEm12xXBZU4SyR+0awbWqU6bZlCtpCBK502KwE3witQLMNA14zeQb7z7TMYyEIBU4nSoMEACZ52HW0Go6v1nbLq+LY/A==", "X-Forefront-Antispam-Report": "CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230016)(4636009)(40470700004)(36840700001)(46966006)(81166007)(40460700003)(36860700001)(356005)(6636002)(36756003)(5660300002)(2906002)(26005)(110136005)(54906003)(86362001)(2616005)(6286002)(16526019)(107886003)(83380400001)(7696005)(82310400005)(4326008)(6666004)(8936002)(55016003)(70586007)(70206006)(186003)(1076003)(8676002)(508600001)(336012)(426003)(47076005)(316002)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Jun 2022 12:59:04.7181 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 62e412a7-7e1e-4c2f-b3d6-08da4eced3c5", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT019.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB5547", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "When LWM meets RQ WQE, the kernel driver raises an event to SW.\nUse devx event_channel to catch this and to notify the user.\nAllocate this channel per shared device.\nThe channel has a cookie that informs the specific event port and queue.\n\nSigned-off-by: Spike Du <spiked@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 66 ++++++++++++++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5.h | 7 +++++\n drivers/net/mlx5/mlx5_devx.c | 47 +++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_rx.c | 33 ++++++++++++++++++++++\n drivers/net/mlx5/mlx5_rx.h | 7 +++++\n 5 files changed, 160 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex f098871..e04a666 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -9,6 +9,7 @@\n #include <stdint.h>\n #include <stdlib.h>\n #include <errno.h>\n+#include <fcntl.h>\n \n #include <rte_malloc.h>\n #include <ethdev_driver.h>\n@@ -22,6 +23,7 @@\n #include <rte_eal_paging.h>\n #include <rte_alarm.h>\n #include <rte_cycles.h>\n+#include <rte_interrupts.h>\n \n #include <mlx5_glue.h>\n #include <mlx5_devx_cmds.h>\n@@ -1525,6 +1527,69 @@ struct mlx5_dev_ctx_shared *\n }\n \n /**\n+ * Create LWM event_channel and interrupt handle for shared device\n+ * context. All rxqs sharing the device context share the event_channel.\n+ * A callback is registered in interrupt thread to receive the LWM event.\n+ *\n+ * @param[in] priv\n+ * Pointer to mlx5_priv instance.\n+ *\n+ * @return\n+ * 0 on success, negative with rte_errno set.\n+ */\n+int\n+mlx5_lwm_setup(struct mlx5_priv *priv)\n+{\n+\tint fd_lwm;\n+\n+\tpthread_mutex_init(&priv->sh->lwm_config_lock, NULL);\n+\tpriv->sh->devx_channel_lwm = mlx5_os_devx_create_event_channel\n+\t\t\t(priv->sh->cdev->ctx,\n+\t\t\t MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);\n+\tif (!priv->sh->devx_channel_lwm)\n+\t\tgoto err;\n+\tfd_lwm = mlx5_os_get_devx_channel_fd(priv->sh->devx_channel_lwm);\n+\tpriv->sh->intr_handle_lwm = mlx5_os_interrupt_handler_create\n+\t\t(RTE_INTR_INSTANCE_F_SHARED, true,\n+\t\t fd_lwm, mlx5_dev_interrupt_handler_lwm, priv);\n+\tif (!priv->sh->intr_handle_lwm)\n+\t\tgoto err;\n+\treturn 0;\n+err:\n+\tif (priv->sh->devx_channel_lwm) {\n+\t\tmlx5_os_devx_destroy_event_channel\n+\t\t\t(priv->sh->devx_channel_lwm);\n+\t\tpriv->sh->devx_channel_lwm = NULL;\n+\t}\n+\tpthread_mutex_destroy(&priv->sh->lwm_config_lock);\n+\treturn -rte_errno;\n+}\n+\n+/**\n+ * Destroy LWM event_channel and interrupt handle for shared device\n+ * context before free this context. The interrupt handler is also\n+ * unregistered.\n+ *\n+ * @param[in] sh\n+ * Pointer to shared device context.\n+ */\n+void\n+mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh)\n+{\n+\tif (sh->intr_handle_lwm) {\n+\t\tmlx5_os_interrupt_handler_destroy(sh->intr_handle_lwm,\n+\t\t\tmlx5_dev_interrupt_handler_lwm, (void *)-1);\n+\t\tsh->intr_handle_lwm = NULL;\n+\t}\n+\tif (sh->devx_channel_lwm) {\n+\t\tmlx5_os_devx_destroy_event_channel\n+\t\t\t(sh->devx_channel_lwm);\n+\t\tsh->devx_channel_lwm = NULL;\n+\t}\n+\tpthread_mutex_destroy(&sh->lwm_config_lock);\n+}\n+\n+/**\n * Free shared IB device context. Decrement counter and if zero free\n * all allocated resources and close handles.\n *\n@@ -1601,6 +1666,7 @@ struct mlx5_dev_ctx_shared *\n \t\tclaim_zero(mlx5_devx_cmd_destroy(sh->td));\n \tMLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);\n \tpthread_mutex_destroy(&sh->txpp.mutex);\n+\tmlx5_lwm_unset(sh);\n \tmlx5_free(sh);\n \treturn;\n exit:\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 7ebb2cc..a76f2fe 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1268,6 +1268,9 @@ struct mlx5_dev_ctx_shared {\n \tstruct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */\n \tunsigned int flow_max_priority;\n \tenum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];\n+\tvoid *devx_channel_lwm;\n+\tstruct rte_intr_handle *intr_handle_lwm;\n+\tpthread_mutex_t lwm_config_lock;\n \t/* Availability of mreg_c's. */\n \tstruct mlx5_dev_shared_port port[]; /* per device port data array. */\n };\n@@ -1405,6 +1408,7 @@ enum mlx5_txq_modify_type {\n };\n \n struct mlx5_rxq_priv;\n+struct mlx5_priv;\n \n /* HW objects operations structure. */\n struct mlx5_obj_ops {\n@@ -1413,6 +1417,7 @@ struct mlx5_obj_ops {\n \tint (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj);\n \tint (*rxq_obj_modify)(struct mlx5_rxq_priv *rxq, uint8_t type);\n \tvoid (*rxq_obj_release)(struct mlx5_rxq_priv *rxq);\n+\tint (*rxq_event_get_lwm)(struct mlx5_priv *priv, int *rxq_idx, int *port_id);\n \tint (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n,\n \t\t\t struct mlx5_ind_table_obj *ind_tbl);\n \tint (*ind_table_modify)(struct rte_eth_dev *dev,\n@@ -1603,6 +1608,8 @@ int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,\n bool mlx5_is_hpf(struct rte_eth_dev *dev);\n bool mlx5_is_sf_repr(struct rte_eth_dev *dev);\n void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh);\n+int mlx5_lwm_setup(struct mlx5_priv *priv);\n+void mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh);\n \n /* Macro to iterate over all valid ports for mlx5 driver. */\n #define MLX5_ETH_FOREACH_DEV(port_id, dev) \\\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex c918a50..6886ae1 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -233,6 +233,52 @@\n }\n \n /**\n+ * Get LWM event for shared context, return the correct port/rxq for this event.\n+ *\n+ * @param priv\n+ * Mlx5_priv object.\n+ * @param rxq_idx [out]\n+ * Which rxq gets this event.\n+ * @param port_id [out]\n+ * Which port gets this event.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_rx_devx_get_event_lwm(struct mlx5_priv *priv, int *rxq_idx, int *port_id)\n+{\n+#ifdef HAVE_IBV_DEVX_EVENT\n+\tunion {\n+\t\tstruct mlx5dv_devx_async_event_hdr event_resp;\n+\t\tuint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];\n+\t} out;\n+\tint ret;\n+\n+\tmemset(&out, 0, sizeof(out));\n+\tret = mlx5_glue->devx_get_event(priv->sh->devx_channel_lwm,\n+\t\t\t\t\t&out.event_resp,\n+\t\t\t\t\tsizeof(out.buf));\n+\tif (ret < 0) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(WARNING, \"%s err\\n\", __func__);\n+\t\treturn -rte_errno;\n+\t}\n+\t*port_id = (((uint32_t)out.event_resp.cookie) >>\n+\t\t LWM_COOKIE_PORTID_OFFSET) & LWM_COOKIE_PORTID_MASK;\n+\t*rxq_idx = (((uint32_t)out.event_resp.cookie) >>\n+\t\t LWM_COOKIE_RXQID_OFFSET) & LWM_COOKIE_RXQID_MASK;\n+\treturn 0;\n+#else\n+\t(void)priv;\n+\t(void)rxq_idx;\n+\t(void)port_id;\n+\trte_errno = ENOTSUP;\n+\treturn -rte_errno;\n+#endif /* HAVE_IBV_DEVX_EVENT */\n+}\n+\n+/**\n * Create a RQ object using DevX.\n *\n * @param rxq\n@@ -1421,6 +1467,7 @@ struct mlx5_obj_ops devx_obj_ops = {\n \t.rxq_event_get = mlx5_rx_devx_get_event,\n \t.rxq_obj_modify = mlx5_devx_modify_rq,\n \t.rxq_obj_release = mlx5_rxq_devx_obj_release,\n+\t.rxq_event_get_lwm = mlx5_rx_devx_get_event_lwm,\n \t.ind_table_new = mlx5_devx_ind_table_new,\n \t.ind_table_modify = mlx5_devx_ind_table_modify,\n \t.ind_table_destroy = mlx5_devx_ind_table_destroy,\ndiff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c\nindex e5eea0a..197d708 100644\n--- a/drivers/net/mlx5/mlx5_rx.c\n+++ b/drivers/net/mlx5/mlx5_rx.c\n@@ -1187,3 +1187,36 @@ int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)\n {\n \treturn -ENOTSUP;\n }\n+\n+/**\n+ * Rte interrupt handler for LWM event.\n+ * It first checks if the event arrives, if so process the callback for\n+ * RTE_ETH_EVENT_RX_LWM.\n+ *\n+ * @param args\n+ * Generic pointer to mlx5_priv.\n+ */\n+void\n+mlx5_dev_interrupt_handler_lwm(void *args)\n+{\n+\tstruct mlx5_priv *priv = args;\n+\tstruct mlx5_rxq_priv *rxq;\n+\tstruct rte_eth_dev *dev;\n+\tint ret, rxq_idx = 0, port_id = 0;\n+\n+\tret = priv->obj_ops.rxq_event_get_lwm(priv, &rxq_idx, &port_id);\n+\tif (unlikely(ret < 0)) {\n+\t\tDRV_LOG(WARNING, \"Cannot get LWM event context.\");\n+\t\treturn;\n+\t}\n+\tDRV_LOG(INFO, \"%s get LWM event, port_id:%d rxq_id:%d.\", __func__,\n+\t\tport_id, rxq_idx);\n+\tdev = &rte_eth_devices[port_id];\n+\trxq = mlx5_rxq_get(dev, rxq_idx);\n+\tif (rxq) {\n+\t\tpthread_mutex_lock(&priv->sh->lwm_config_lock);\n+\t\trxq->lwm_event_pending = 1;\n+\t\tpthread_mutex_unlock(&priv->sh->lwm_config_lock);\n+\t}\n+\trte_eth_dev_callback_process(dev, RTE_ETH_EVENT_RX_AVAIL_THRESH, NULL);\n+}\ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex 25a5f2c..068dff5 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -176,6 +176,7 @@ struct mlx5_rxq_priv {\n \tstruct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */\n \tuint32_t hairpin_status; /* Hairpin binding status. */\n \tuint32_t lwm:16;\n+\tuint32_t lwm_event_pending:1;\n };\n \n /* External RX queue descriptor. */\n@@ -295,6 +296,7 @@ void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,\n int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n \t\t\t struct rte_eth_burst_mode *mode);\n int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);\n+void mlx5_dev_interrupt_handler_lwm(void *args);\n \n /* Vectorized version of mlx5_rx.c */\n int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);\n@@ -675,4 +677,9 @@ uint16_t mlx5_rx_burst_mprq_vec(void *dpdk_rxq, struct rte_mbuf **pkts,\n \treturn !!__atomic_load_n(&rxq->refcnt, __ATOMIC_RELAXED);\n }\n \n+#define LWM_COOKIE_RXQID_OFFSET 0\n+#define LWM_COOKIE_RXQID_MASK 0xffff\n+#define LWM_COOKIE_PORTID_OFFSET 16\n+#define LWM_COOKIE_PORTID_MASK 0xffff\n+\n #endif /* RTE_PMD_MLX5_RX_H_ */\n", "prefixes": [ "v8", "3/6" ] }