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{
    "id": 112767,
    "url": "https://patches.dpdk.org/api/patches/112767/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220615125836.391771-2-spiked@nvidia.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220615125836.391771-2-spiked@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220615125836.391771-2-spiked@nvidia.com",
    "date": "2022-06-15T12:58:31",
    "name": "[v8,1/6] net/mlx5: add LWM support for Rxq",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "25526add26c35ee5eb9c77ced2a320cef2d33d64",
    "submitter": {
        "id": 2637,
        "url": "https://patches.dpdk.org/api/people/2637/?format=api",
        "name": "Spike Du",
        "email": "spiked@nvidia.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220615125836.391771-2-spiked@nvidia.com/mbox/",
    "series": [
        {
            "id": 23538,
            "url": "https://patches.dpdk.org/api/series/23538/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=23538",
            "date": "2022-06-15T12:58:30",
            "name": "introduce per-queue available descriptor threshold and host shaper",
            "version": 8,
            "mbox": "https://patches.dpdk.org/series/23538/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/112767/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/112767/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Spike Du <spiked@nvidia.com>",
        "To": "<matan@nvidia.com>, <viacheslavo@nvidia.com>, <orika@nvidia.com>,\n <thomas@monjalon.net>, Shahaf Shuler <shahafs@nvidia.com>",
        "CC": "<andrew.rybchenko@oktetlabs.ru>, <stephen@networkplumber.org>,\n <mb@smartsharesystems.com>, <dev@dpdk.org>, <rasland@nvidia.com>",
        "Subject": "[PATCH v8 1/6] net/mlx5: add LWM support for Rxq",
        "Date": "Wed, 15 Jun 2022 15:58:31 +0300",
        "Message-ID": "<20220615125836.391771-2-spiked@nvidia.com>",
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        "References": "<20220614120134.1828188-2-spiked@nvidia.com>\n <20220615125836.391771-1-spiked@nvidia.com>",
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    },
    "content": "Add lwm(Limit WaterMark) field to Rxq object which indicates the percentage\nof RX queue size used by HW to raise LWM event to the user.\nAllow LWM setting in modify_rq command.\nAllow the LWM configuration dynamically by adding RDY2RDY state change.\n\nSigned-off-by: Spike Du <spiked@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h      |  1 +\n drivers/net/mlx5/mlx5_devx.c | 13 ++++++++++++-\n drivers/net/mlx5/mlx5_devx.h |  1 +\n drivers/net/mlx5/mlx5_rx.h   |  1 +\n 4 files changed, 15 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex ef755ee..305edff 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1395,6 +1395,7 @@ enum mlx5_rxq_modify_type {\n \tMLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */\n \tMLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */\n \tMLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */\n+\tMLX5_RXQ_MOD_RDY2RDY, /* modify state from ready to ready. */\n };\n \n enum mlx5_txq_modify_type {\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 4b48f94..c918a50 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -62,7 +62,7 @@\n  * @return\n  *   0 on success, a negative errno value otherwise and rte_errno is set.\n  */\n-static int\n+int\n mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type)\n {\n \tstruct mlx5_devx_modify_rq_attr rq_attr;\n@@ -76,6 +76,11 @@\n \tcase MLX5_RXQ_MOD_RST2RDY:\n \t\trq_attr.rq_state = MLX5_RQC_STATE_RST;\n \t\trq_attr.state = MLX5_RQC_STATE_RDY;\n+\t\tif (rxq->lwm) {\n+\t\t\trq_attr.modify_bitmask |=\n+\t\t\t\tMLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM;\n+\t\t\trq_attr.lwm = rxq->lwm;\n+\t\t}\n \t\tbreak;\n \tcase MLX5_RXQ_MOD_RDY2ERR:\n \t\trq_attr.rq_state = MLX5_RQC_STATE_RDY;\n@@ -85,6 +90,12 @@\n \t\trq_attr.rq_state = MLX5_RQC_STATE_RDY;\n \t\trq_attr.state = MLX5_RQC_STATE_RST;\n \t\tbreak;\n+\tcase MLX5_RXQ_MOD_RDY2RDY:\n+\t\trq_attr.rq_state = MLX5_RQC_STATE_RDY;\n+\t\trq_attr.state = MLX5_RQC_STATE_RDY;\n+\t\trq_attr.modify_bitmask |= MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM;\n+\t\trq_attr.lwm = rxq->lwm;\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5_devx.h b/drivers/net/mlx5/mlx5_devx.h\nindex a95207a..ebd1da4 100644\n--- a/drivers/net/mlx5/mlx5_devx.h\n+++ b/drivers/net/mlx5/mlx5_devx.h\n@@ -11,6 +11,7 @@\n int mlx5_txq_devx_modify(struct mlx5_txq_obj *obj,\n \t\t\t enum mlx5_txq_modify_type type, uint8_t dev_port);\n void mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj);\n+int mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type);\n \n extern struct mlx5_obj_ops devx_obj_ops;\n \ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex e715ed6..25a5f2c 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -175,6 +175,7 @@ struct mlx5_rxq_priv {\n \tstruct mlx5_devx_rq devx_rq;\n \tstruct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */\n \tuint32_t hairpin_status; /* Hairpin binding status. */\n+\tuint32_t lwm:16;\n };\n \n /* External RX queue descriptor. */\n",
    "prefixes": [
        "v8",
        "1/6"
    ]
}