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GET /api/patches/112759/?format=api
{ "id": 112759, "url": "https://patches.dpdk.org/api/patches/112759/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220615100227.358768-1-yajunw@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220615100227.358768-1-yajunw@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220615100227.358768-1-yajunw@nvidia.com", "date": "2022-06-15T10:02:27", "name": "[v3] vdpa/mlx5: workaround var offset within page", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "570f425f4d7e9b696a90a7843fa033ba43501927", "submitter": { "id": 2517, "url": "https://patches.dpdk.org/api/people/2517/?format=api", "name": "Yajun Wu", "email": "yajunw@nvidia.com" }, "delegate": { "id": 2642, "url": "https://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220615100227.358768-1-yajunw@nvidia.com/mbox/", "series": [ { "id": 23534, "url": "https://patches.dpdk.org/api/series/23534/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=23534", "date": "2022-06-15T10:02:27", "name": "[v3] vdpa/mlx5: workaround var offset within page", "version": 3, "mbox": "https://patches.dpdk.org/series/23534/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/112759/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/112759/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0C00DA0548;\n\tWed, 15 Jun 2022 12:02:51 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EC0EF40220;\n\tWed, 15 Jun 2022 12:02:50 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2085.outbound.protection.outlook.com [40.107.236.85])\n by mails.dpdk.org (Postfix) with ESMTP id BC51740040;\n Wed, 15 Jun 2022 12:02:49 +0200 (CEST)", "from MW4PR04CA0309.namprd04.prod.outlook.com (2603:10b6:303:82::14)\n by MN2PR12MB3087.namprd12.prod.outlook.com (2603:10b6:208:d2::32)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5332.13; 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helo=mail.nvidia.com; pr=C", "From": "Yajun Wu <yajunw@nvidia.com>", "To": "<maxime.coquelin@redhat.com>, <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <thomas@monjalon.net>, <rasland@nvidia.com>,\n <roniba@nvidia.com>, <stable@dpdk.org>", "Subject": "[PATCH v3] vdpa/mlx5: workaround var offset within page", "Date": "Wed, 15 Jun 2022 13:02:27 +0300", "Message-ID": "<20220615100227.358768-1-yajunw@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20220314014414.251869-1-yajunw@nvidia.com>", "References": "<20220314014414.251869-1-yajunw@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "9cf9ee38-761d-45b9-d323-08da4eb63323", "X-MS-TrafficTypeDiagnostic": "MN2PR12MB3087:EE_", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <MN2PR12MB3087173F3DE7253F8C35DB5CB6AD9@MN2PR12MB3087.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n koksnGAgr8sYy8Ay9HvKXkuS2C1nm3+T+tSeLF70xmMxk/Df6dqypTvvCWXo82C0EGJEog06fYYIWPGDMYOBK+N6kdXO1kCoe5AYa5HBtvAhYw3phIYSNfcOSqAw/S+7prIWz+eQuESkaRA44VHxB3G0XO8oVK2G1U7fXomHOf5WmA/DNRt3h1YPIldaIY/MHpysw/gVDu3ymDtrEwKgvKwyvV1/FlWfwdliQKozqs/gLe2ea0mUvbCKu0G0xQUKxzV/UJhtuhbME1g3EOce90948vWgAZyNS3by4vFYiz44e1F1U38HO27JEwiAIxQDxS6b2uV+3cQ/Tpukog+tVQpft0QnKwGBAKUEnYsCuSXRcRAvPxkzs8db5pbey8u0QWD3x2CQNEOpN2n61byxIr3jkI+9UNje0PvxkRlFn4hqQ4wJgLkkR4jyyAQFfqP9mpbkL2k9bUNOhqunWr5OuDJsWELFLzwwNqGQQhQK1LdQR2RBa06OLyW8sdyDIHJLnuN6FOzWFUXcKR0rbnkCx/lBZi46D8f+weraKhJwrdmp/b8Uf27PBxuwPkjEipL6iAYYomqzR02RJpKrApuqA84UyX9KfEls7CHGsaNzCZ2f0e8SPyrHe/YWAVpZdz58MLpuGcZ5NokJ+4RkiIAdL9sX5WafyRRDCp5qyr0ECPmex8qpi4amyRpTzt7Aa/6IIpGE0BIIHyadXCyfOkEWJ7PFCIz2XfxpeHmCh3qYsvQ=", "X-Forefront-Antispam-Report": "CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230016)(4636009)(36840700001)(40470700004)(46966006)(70586007)(54906003)(6286002)(356005)(26005)(82310400005)(5660300002)(186003)(2906002)(86362001)(1076003)(36860700001)(2616005)(110136005)(70206006)(8936002)(81166007)(8676002)(508600001)(316002)(6636002)(83380400001)(47076005)(55016003)(40460700003)(426003)(6666004)(16526019)(336012)(7696005)(4326008)(36756003)(2101003)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Jun 2022 10:02:47.4409 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9cf9ee38-761d-45b9-d323-08da4eb63323", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT036.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB3087", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "vDPA driver first uses kernel driver to allocate doorbell(VAR) area for\neach device. Then uses var->mmap_off and var->length to mmap uverbs device\nfile as doorbell userspace virtual address.\n\nCurrent kernel driver provides var->mmap_off equal to page start of VAR.\nIt's fine with x86 4K page server, because VAR physical address is only 4K\naligned thus locate in 4K page start.\n\nBut with aarch64 64K page server, the actual VAR physical address has\noffset within page(not locate in 64K page start). So vDPA driver need add\nthis within page offset(caps.doorbell_bar_offset) to get right VAR virtual\naddress.\n\nFixes: 62c813706e4 (\"vdpa/mlx5: map doorbell\")\nCc: stable@dpdk.org\n\nSigned-off-by: Yajun Wu <yajunw@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n drivers/vdpa/mlx5/mlx5_vdpa.c | 8 +++++++-\n 1 file changed, 7 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c\nindex 76fa5d4299..8a33a0c9a1 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.c\n@@ -14,6 +14,7 @@\n #include <rte_errno.h>\n #include <rte_string_fns.h>\n #include <rte_bus_pci.h>\n+#include <rte_eal_paging.h>\n \n #include <mlx5_glue.h>\n #include <mlx5_common.h>\n@@ -560,6 +561,9 @@ mlx5_vdpa_create_dev_resources(struct mlx5_vdpa_priv *priv)\n \t\trte_errno = errno;\n \t\treturn -rte_errno;\n \t}\n+\t/* Add within page offset for 64K page system. */\n+\tpriv->virtq_db_addr = (char *)priv->virtq_db_addr +\n+\t\t((rte_mem_page_size() - 1) & priv->caps.doorbell_bar_offset);\n \tDRV_LOG(DEBUG, \"VAR address of doorbell mapping is %p.\",\n \t\tpriv->virtq_db_addr);\n \tpriv->td = mlx5_devx_cmd_create_td(ctx);\n@@ -705,7 +709,9 @@ mlx5_vdpa_release_dev_resources(struct mlx5_vdpa_priv *priv)\n \tif (priv->td)\n \t\tclaim_zero(mlx5_devx_cmd_destroy(priv->td));\n \tif (priv->virtq_db_addr)\n-\t\tclaim_zero(munmap(priv->virtq_db_addr, priv->var->length));\n+\t\t/* Mask out the within page offset for munmap. */\n+\t\tclaim_zero(munmap((void *)((uintptr_t)priv->virtq_db_addr &\n+\t\t\t~(rte_mem_page_size() - 1)), priv->var->length));\n \tif (priv->var)\n \t\tmlx5_glue->dv_free_var(priv->var);\n }\n", "prefixes": [ "v3" ] }