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GET /api/patches/112585/?format=api
{ "id": 112585, "url": "https://patches.dpdk.org/api/patches/112585/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1654742650-7214-6-git-send-email-wei.huang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1654742650-7214-6-git-send-email-wei.huang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1654742650-7214-6-git-send-email-wei.huang@intel.com", "date": "2022-06-09T02:44:10", "name": "[v6,5/5] raw/ifpga: add HE-HSSI AFU driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f827171f2cc2d3b948944278a625bcc0b954d96b", "submitter": { "id": 2033, "url": "https://patches.dpdk.org/api/people/2033/?format=api", "name": "Wei Huang", "email": "wei.huang@intel.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1654742650-7214-6-git-send-email-wei.huang@intel.com/mbox/", "series": [ { "id": 23427, "url": "https://patches.dpdk.org/api/series/23427/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=23427", "date": "2022-06-09T02:44:05", "name": "introduce AFU PMD driver of FPGA", "version": 6, "mbox": "https://patches.dpdk.org/series/23427/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/112585/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/112585/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9B312A0547;\n\tThu, 9 Jun 2022 04:37:16 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 54913427F9;\n\tThu, 9 Jun 2022 04:37:11 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by mails.dpdk.org (Postfix) with ESMTP id 7602C40220;\n Thu, 9 Jun 2022 04:37:08 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Jun 2022 19:36:47 -0700", "from unknown (HELO zj-fpga-amt.sh.intel.com) ([10.238.175.102])\n by fmsmga006.fm.intel.com with ESMTP; 08 Jun 2022 19:36:45 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1654742228; x=1686278228;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=bPi7NwJgsM2Z91u0nzVzSjOIufSoqKeke8e2JFMGpNg=;\n b=cfKJE2QwH/H2Uv+VU6DsQVNUJizNUr/GrCA6DSfowpEa/wGDVSx4xtbX\n dnMAiY9Et++nh1+K80ohDiLdM7a/7509kURoeP6uASkFkL4LvZ45bflJn\n CjWKdzsVHF7X0k70BktQGxWhTCwaHSI90Yvyum5AzNWN3CmyD8JvfTE8c\n ZVPvLKPUnYZUabqQ2hbqUEjR+BcaYQexh+EO8NADK5wBwH+b719ha7oGZ\n +zqEnyr8BwDrzsrslv2aH3jNCoLYYKUKq3nxj5oNu26RkkpRo/GnShFsP\n bYbYEC+x/Fd+KtyEuKpjT0iZkAAd53w43i7MpqNbjT/1ZnOdsqODpx9oi A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10372\"; a=\"277146325\"", "E=Sophos;i=\"5.91,287,1647327600\"; d=\"scan'208\";a=\"277146325\"", "E=Sophos;i=\"5.91,287,1647327600\"; d=\"scan'208\";a=\"827300439\"" ], "X-ExtLoop1": "1", "From": "Wei Huang <wei.huang@intel.com>", "To": "dev@dpdk.org, thomas@monjalon.net, nipun.gupta@nxp.com,\n hemant.agrawal@nxp.com", "Cc": "stable@dpdk.org, rosen.xu@intel.com, tianfei.zhang@intel.com,\n qi.z.zhang@intel.com, Wei Huang <wei.huang@intel.com>", "Subject": "[PATCH v6 5/5] raw/ifpga: add HE-HSSI AFU driver", "Date": "Wed, 8 Jun 2022 22:44:10 -0400", "Message-Id": "<1654742650-7214-6-git-send-email-wei.huang@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1654742650-7214-1-git-send-email-wei.huang@intel.com>", "References": "<1653629824-4535-1-git-send-email-wei.huang@intel.com>\n <1654742650-7214-1-git-send-email-wei.huang@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "HE-HSSI is one of the host exerciser modules in OFS FPGA,\nwhich is used to test HSSI (High Speed Serial Interface).\nThis driver initialize the module and report test result.\n\nSigned-off-by: Wei Huang <wei.huang@intel.com>\n---\n drivers/raw/ifpga/afu_pmd_he_hssi.c | 371 ++++++++++++++++++++++++++++++++++++\n drivers/raw/ifpga/afu_pmd_he_hssi.h | 108 +++++++++++\n drivers/raw/ifpga/meson.build | 3 +-\n drivers/raw/ifpga/rte_pmd_afu.h | 16 ++\n 4 files changed, 497 insertions(+), 1 deletion(-)\n create mode 100644 drivers/raw/ifpga/afu_pmd_he_hssi.c\n create mode 100644 drivers/raw/ifpga/afu_pmd_he_hssi.h", "diff": "diff --git a/drivers/raw/ifpga/afu_pmd_he_hssi.c b/drivers/raw/ifpga/afu_pmd_he_hssi.c\nnew file mode 100644\nindex 0000000..395c2ca\n--- /dev/null\n+++ b/drivers/raw/ifpga/afu_pmd_he_hssi.c\n@@ -0,0 +1,371 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Intel Corporation\n+ */\n+\n+#include <errno.h>\n+#include <stdio.h>\n+#include <stdint.h>\n+#include <stdlib.h>\n+#include <inttypes.h>\n+#include <unistd.h>\n+#include <fcntl.h>\n+#include <poll.h>\n+#include <sys/eventfd.h>\n+#include <sys/ioctl.h>\n+\n+#include <rte_eal.h>\n+#include <rte_malloc.h>\n+#include <rte_memcpy.h>\n+#include <rte_io.h>\n+#include <rte_vfio.h>\n+#include <rte_bus_pci.h>\n+#include <rte_bus_ifpga.h>\n+#include <rte_rawdev.h>\n+\n+#include \"afu_pmd_core.h\"\n+#include \"afu_pmd_he_hssi.h\"\n+\n+static int he_hssi_indirect_write(struct he_hssi_ctx *ctx, uint32_t addr,\n+\tuint32_t value)\n+{\n+\tstruct traffic_ctrl_cmd cmd;\n+\tstruct traffic_ctrl_data data;\n+\tuint32_t i = 0;\n+\n+\tIFPGA_RAWDEV_PMD_DEBUG(\"Indirect write 0x%x, value 0x%08x\", addr, value);\n+\n+\tif (!ctx)\n+\t\treturn -EINVAL;\n+\n+\tdata.write_data = value;\n+\trte_write64(data.csr, ctx->addr + TRAFFIC_CTRL_DATA);\n+\n+\tcmd.csr = 0;\n+\tcmd.write_cmd = 1;\n+\tcmd.afu_cmd_addr = addr;\n+\trte_write64(cmd.csr, ctx->addr + TRAFFIC_CTRL_CMD);\n+\n+\twhile (i < MAILBOX_TIMEOUT_MS) {\n+\t\trte_delay_ms(MAILBOX_POLL_INTERVAL_MS);\n+\t\tcmd.csr = rte_read64(ctx->addr + TRAFFIC_CTRL_CMD);\n+\t\tif (cmd.ack_trans)\n+\t\t\tbreak;\n+\t\ti += MAILBOX_POLL_INTERVAL_MS;\n+\t}\n+\tif (i >= MAILBOX_TIMEOUT_MS)\n+\t\treturn -ETIMEDOUT;\n+\n+\ti = 0;\n+\tcmd.csr = 0;\n+\twhile (i < MAILBOX_TIMEOUT_MS) {\n+\t\tcmd.ack_trans = 1;\n+\t\trte_write64(cmd.csr, ctx->addr + TRAFFIC_CTRL_CMD);\n+\t\trte_delay_ms(MAILBOX_POLL_INTERVAL_MS);\n+\t\tcmd.csr = rte_read64(ctx->addr + TRAFFIC_CTRL_CMD);\n+\t\tif (!cmd.ack_trans)\n+\t\t\tbreak;\n+\t\ti += MAILBOX_POLL_INTERVAL_MS;\n+\t}\n+\tif (i >= MAILBOX_TIMEOUT_MS)\n+\t\treturn -ETIMEDOUT;\n+\n+\treturn 0;\n+}\n+\n+static int he_hssi_indirect_read(struct he_hssi_ctx *ctx, uint32_t addr,\n+\tuint32_t *value)\n+{\n+\tstruct traffic_ctrl_cmd cmd;\n+\tstruct traffic_ctrl_data data;\n+\tuint32_t i = 0;\n+\n+\tif (!ctx)\n+\t\treturn -EINVAL;\n+\n+\tcmd.csr = 0;\n+\tcmd.read_cmd = 1;\n+\tcmd.afu_cmd_addr = addr;\n+\trte_write64(cmd.csr, ctx->addr + TRAFFIC_CTRL_CMD);\n+\n+\twhile (i < MAILBOX_TIMEOUT_MS) {\n+\t\trte_delay_ms(MAILBOX_POLL_INTERVAL_MS);\n+\t\tcmd.csr = rte_read64(ctx->addr + TRAFFIC_CTRL_CMD);\n+\t\tif (cmd.ack_trans) {\n+\t\t\tdata.csr = rte_read64(ctx->addr + TRAFFIC_CTRL_DATA);\n+\t\t\t*value = data.read_data;\n+\t\t\tbreak;\n+\t\t}\n+\t\ti += MAILBOX_POLL_INTERVAL_MS;\n+\t}\n+\tif (i >= MAILBOX_TIMEOUT_MS)\n+\t\treturn -ETIMEDOUT;\n+\n+\ti = 0;\n+\tcmd.csr = 0;\n+\twhile (i < MAILBOX_TIMEOUT_MS) {\n+\t\tcmd.ack_trans = 1;\n+\t\trte_write64(cmd.csr, ctx->addr + TRAFFIC_CTRL_CMD);\n+\t\trte_delay_ms(MAILBOX_POLL_INTERVAL_MS);\n+\t\tcmd.csr = rte_read64(ctx->addr + TRAFFIC_CTRL_CMD);\n+\t\tif (!cmd.ack_trans)\n+\t\t\tbreak;\n+\t\ti += MAILBOX_POLL_INTERVAL_MS;\n+\t}\n+\tif (i >= MAILBOX_TIMEOUT_MS)\n+\t\treturn -ETIMEDOUT;\n+\n+\tIFPGA_RAWDEV_PMD_DEBUG(\"Indirect read 0x%x, value 0x%08x\", addr, *value);\n+\treturn 0;\n+}\n+\n+static void he_hssi_report(struct he_hssi_ctx *ctx)\n+{\n+\tuint32_t val = 0;\n+\tuint64_t v64 = 0;\n+\tint ret = 0;\n+\n+\tret = he_hssi_indirect_read(ctx, TM_PKT_GOOD, &val);\n+\tif (ret)\n+\t\treturn;\n+\tprintf(\"Number of good packets received: %u\\n\", val);\n+\n+\tret = he_hssi_indirect_read(ctx, TM_PKT_BAD, &val);\n+\tif (ret)\n+\t\treturn;\n+\tprintf(\"Number of bad packets received: %u\\n\", val);\n+\n+\tret = he_hssi_indirect_read(ctx, TM_BYTE_CNT1, &val);\n+\tif (ret)\n+\t\treturn;\n+\tv64 = val;\n+\tret = he_hssi_indirect_read(ctx, TM_BYTE_CNT0, &val);\n+\tif (ret)\n+\t\treturn;\n+\tv64 = (v64 << 32) | val;\n+\tprintf(\"Number of bytes received: %\"PRIu64\"\\n\", v64);\n+\n+\tret = he_hssi_indirect_read(ctx, TM_AVST_RX_ERR, &val);\n+\tif (ret)\n+\t\treturn;\n+\tif (val & ERR_VALID) {\n+\t\tprintf(\"AVST rx error:\");\n+\t\tif (val & OVERFLOW_ERR)\n+\t\t\tprintf(\" overflow\");\n+\t\tif (val & LENGTH_ERR)\n+\t\t\tprintf(\" length\");\n+\t\tif (val & OVERSIZE_ERR)\n+\t\t\tprintf(\" oversize\");\n+\t\tif (val & UNDERSIZE_ERR)\n+\t\t\tprintf(\" undersize\");\n+\t\tif (val & MAC_CRC_ERR)\n+\t\t\tprintf(\" crc\");\n+\t\tif (val & PHY_ERR)\n+\t\t\tprintf(\" phy\");\n+\t\tprintf(\"\\n\");\n+\t}\n+\n+\tret = he_hssi_indirect_read(ctx, LOOPBACK_FIFO_STATUS, &val);\n+\tif (ret)\n+\t\treturn;\n+\tif (val & (ALMOST_EMPTY | ALMOST_FULL)) {\n+\t\tprintf(\"FIFO status:\");\n+\t\tif (val & ALMOST_EMPTY)\n+\t\t\tprintf(\" almost empty\");\n+\t\tif (val & ALMOST_FULL)\n+\t\t\tprintf(\" almost full\");\n+\t\tprintf(\"\\n\");\n+\t}\n+}\n+\n+static int he_hssi_test(struct afu_rawdev *dev)\n+{\n+\tstruct he_hssi_priv *priv = NULL;\n+\tstruct rte_pmd_afu_he_hssi_cfg *cfg = NULL;\n+\tstruct he_hssi_ctx *ctx = NULL;\n+\tstruct traffic_ctrl_ch_sel sel;\n+\tuint32_t val = 0;\n+\tuint32_t i = 0;\n+\tint ret = 0;\n+\n+\tif (!dev)\n+\t\treturn -EINVAL;\n+\n+\tpriv = (struct he_hssi_priv *)dev->priv;\n+\tif (!priv)\n+\t\treturn -ENOENT;\n+\n+\tcfg = &priv->he_hssi_cfg;\n+\tctx = &priv->he_hssi_ctx;\n+\n+\tret = he_hssi_indirect_write(ctx, TG_STOP_XFR, 0);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tsel.channel_sel = cfg->port;\n+\trte_write64(sel.csr, ctx->addr + TRAFFIC_CTRL_CH_SEL);\n+\n+\tif (cfg->he_loopback >= 0) {\n+\t\tval = cfg->he_loopback ? 1 : 0;\n+\t\tIFPGA_RAWDEV_PMD_INFO(\"%s HE loopback on port %u\",\n+\t\t\tval ? \"Enable\" : \"Disable\", cfg->port);\n+\t\treturn he_hssi_indirect_write(ctx, LOOPBACK_EN, val);\n+\t}\n+\n+\tret = he_hssi_indirect_write(ctx, TG_NUM_PKT, cfg->num_packets);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = he_hssi_indirect_write(ctx, TG_PKT_LEN, cfg->packet_length);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tval = cfg->src_addr & 0xffffffff;\n+\tret = he_hssi_indirect_write(ctx, TG_SRC_MAC_L, val);\n+\tif (ret)\n+\t\treturn ret;\n+\tval = (cfg->src_addr >> 32) & 0xffff;\n+\tret = he_hssi_indirect_write(ctx, TG_SRC_MAC_H, val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tval = cfg->dest_addr & 0xffffffff;\n+\tret = he_hssi_indirect_write(ctx, TG_DST_MAC_L, val);\n+\tif (ret)\n+\t\treturn ret;\n+\tval = (cfg->dest_addr >> 32) & 0xffff;\n+\tret = he_hssi_indirect_write(ctx, TG_DST_MAC_H, val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tval = cfg->random_length ? 1 : 0;\n+\tret = he_hssi_indirect_write(ctx, TG_PKT_LEN_TYPE, val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tval = cfg->random_payload ? 1 : 0;\n+\tret = he_hssi_indirect_write(ctx, TG_DATA_PATTERN, val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfor (i = 0; i < 3; i++) {\n+\t\tret = he_hssi_indirect_write(ctx, TG_RANDOM_SEED(i),\n+\t\t\tcfg->rnd_seed[i]);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tret = he_hssi_indirect_write(ctx, TG_START_XFR, 1);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\twhile (i++ < cfg->timeout) {\n+\t\tret = he_hssi_indirect_read(ctx, TG_PKT_XFRD, &val);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\t\tif (val == cfg->num_packets)\n+\t\t\tbreak;\n+\t\tsleep(1);\n+\t}\n+\n+\the_hssi_report(ctx);\n+\n+\treturn ret;\n+}\n+\n+static int he_hssi_init(struct afu_rawdev *dev)\n+{\n+\tstruct he_hssi_priv *priv = NULL;\n+\tstruct he_hssi_ctx *ctx = NULL;\n+\n+\tif (!dev)\n+\t\treturn -EINVAL;\n+\n+\tpriv = (struct he_hssi_priv *)dev->priv;\n+\tif (!priv) {\n+\t\tpriv = rte_zmalloc(NULL, sizeof(struct he_hssi_priv), 0);\n+\t\tif (!priv)\n+\t\t\treturn -ENOMEM;\n+\t\tdev->priv = priv;\n+\t}\n+\n+\tctx = &priv->he_hssi_ctx;\n+\tctx->addr = (uint8_t *)dev->addr;\n+\n+\treturn 0;\n+}\n+\n+static int he_hssi_config(struct afu_rawdev *dev, void *config,\n+\tsize_t config_size)\n+{\n+\tstruct he_hssi_priv *priv = NULL;\n+\tstruct rte_pmd_afu_he_hssi_cfg *cfg = NULL;\n+\n+\tif (!dev || !config || !config_size)\n+\t\treturn -EINVAL;\n+\n+\tpriv = (struct he_hssi_priv *)dev->priv;\n+\tif (!priv)\n+\t\treturn -ENOENT;\n+\n+\tif (config_size != sizeof(struct rte_pmd_afu_he_hssi_cfg))\n+\t\treturn -EINVAL;\n+\n+\tcfg = (struct rte_pmd_afu_he_hssi_cfg *)config;\n+\tif (cfg->port >= NUM_HE_HSSI_PORTS)\n+\t\treturn -EINVAL;\n+\n+\trte_memcpy(&priv->he_hssi_cfg, cfg, sizeof(priv->he_hssi_cfg));\n+\n+\treturn 0;\n+}\n+\n+static int he_hssi_close(struct afu_rawdev *dev)\n+{\n+\tif (!dev)\n+\t\treturn -EINVAL;\n+\n+\trte_free(dev->priv);\n+\tdev->priv = NULL;\n+\n+\treturn 0;\n+}\n+\n+static int he_hssi_dump(struct afu_rawdev *dev, FILE *f)\n+{\n+\tstruct he_hssi_priv *priv = NULL;\n+\tstruct he_hssi_ctx *ctx = NULL;\n+\n+\tif (!dev)\n+\t\treturn -EINVAL;\n+\n+\tpriv = (struct he_hssi_priv *)dev->priv;\n+\tif (!priv)\n+\t\treturn -ENOENT;\n+\n+\tif (!f)\n+\t\tf = stdout;\n+\n+\tctx = &priv->he_hssi_ctx;\n+\n+\tfprintf(f, \"addr:\\t\\t%p\\n\", (void *)ctx->addr);\n+\n+\treturn 0;\n+}\n+\n+static struct afu_ops he_hssi_ops = {\n+\t.init = he_hssi_init,\n+\t.config = he_hssi_config,\n+\t.start = NULL,\n+\t.stop = NULL,\n+\t.test = he_hssi_test,\n+\t.close = he_hssi_close,\n+\t.dump = he_hssi_dump,\n+\t.reset = NULL\n+};\n+\n+struct afu_rawdev_drv he_hssi_drv = {\n+\t.uuid = { HE_HSSI_UUID_L, HE_HSSI_UUID_H },\n+\t.ops = &he_hssi_ops\n+};\n+\n+AFU_PMD_REGISTER(he_hssi_drv);\ndiff --git a/drivers/raw/ifpga/afu_pmd_he_hssi.h b/drivers/raw/ifpga/afu_pmd_he_hssi.h\nnew file mode 100644\nindex 0000000..3974670\n--- /dev/null\n+++ b/drivers/raw/ifpga/afu_pmd_he_hssi.h\n@@ -0,0 +1,108 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Intel Corporation\n+ */\n+\n+#ifndef _AFU_PMD_HE_HSSI_H_\n+#define _AFU_PMD_HE_HSSI_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"afu_pmd_core.h\"\n+#include \"rte_pmd_afu.h\"\n+\n+#define HE_HSSI_UUID_L 0xbb370242ac130002\n+#define HE_HSSI_UUID_H 0x823c334c98bf11ea\n+#define NUM_HE_HSSI_PORTS 8\n+\n+/* HE-HSSI registers definition */\n+#define TRAFFIC_CTRL_CMD 0x30\n+#define TRAFFIC_CTRL_DATA 0x38\n+#define TRAFFIC_CTRL_CH_SEL 0x40\n+#define AFU_SCRATCHPAD 0x48\n+\n+#define TG_NUM_PKT 0x3c00\n+#define TG_PKT_LEN_TYPE 0x3c01\n+#define TG_DATA_PATTERN 0x3c02\n+#define TG_START_XFR 0x3c03\n+#define TG_STOP_XFR 0x3c04\n+#define TG_SRC_MAC_L 0x3c05\n+#define TG_SRC_MAC_H 0x3c06\n+#define TG_DST_MAC_L 0x3c07\n+#define TG_DST_MAC_H 0x3c08\n+#define TG_PKT_XFRD 0x3c09\n+#define TG_RANDOM_SEED(n) (0x3c0a + (n))\n+#define TG_PKT_LEN 0x3c0d\n+\n+#define TM_NUM_PKT 0x3d00\n+#define TM_PKT_GOOD 0x3d01\n+#define TM_PKT_BAD 0x3d02\n+#define TM_BYTE_CNT0 0x3d03\n+#define TM_BYTE_CNT1 0x3d04\n+#define TM_AVST_RX_ERR 0x3d07\n+#define OVERFLOW_ERR (1 << 9)\n+#define LENGTH_ERR (1 << 8)\n+#define OVERSIZE_ERR (1 << 7)\n+#define UNDERSIZE_ERR (1 << 6)\n+#define MAC_CRC_ERR (1 << 5)\n+#define PHY_ERR (1 << 4)\n+#define ERR_VALID (1 << 3)\n+\n+#define LOOPBACK_EN 0x3e00\n+#define LOOPBACK_FIFO_STATUS 0x3e01\n+#define ALMOST_EMPTY (1 << 1)\n+#define ALMOST_FULL (1 << 0)\n+\n+#define MAILBOX_TIMEOUT_MS 100\n+#define MAILBOX_POLL_INTERVAL_MS 10\n+\n+struct traffic_ctrl_cmd {\n+\tunion {\n+\t\tuint64_t csr;\n+\t\tstruct {\n+\t\t\tuint32_t read_cmd:1;\n+\t\t\tuint32_t write_cmd:1;\n+\t\t\tuint32_t ack_trans:1;\n+\t\t\tuint32_t rsvd1:29;\n+\t\t\tuint32_t afu_cmd_addr:16;\n+\t\t\tuint32_t rsvd2:16;\n+\t\t};\n+\t};\n+};\n+\n+struct traffic_ctrl_data {\n+\tunion {\n+\t\tuint64_t csr;\n+\t\tstruct {\n+\t\t\tuint32_t read_data;\n+\t\t\tuint32_t write_data;\n+\t\t};\n+\t};\n+};\n+\n+struct traffic_ctrl_ch_sel {\n+\tunion {\n+\t\tuint64_t csr;\n+\t\tstruct {\n+\t\t\tuint32_t channel_sel:3;\n+\t\t\tuint32_t rsvd1:29;\n+\t\t\tuint32_t rsvd2;\n+\t\t};\n+\t};\n+};\n+\n+struct he_hssi_ctx {\n+\tuint8_t *addr;\n+};\n+\n+struct he_hssi_priv {\n+\tstruct rte_pmd_afu_he_hssi_cfg he_hssi_cfg;\n+\tstruct he_hssi_ctx he_hssi_ctx;\n+};\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _AFU_PMD_HE_HSSI_H_ */\ndiff --git a/drivers/raw/ifpga/meson.build b/drivers/raw/ifpga/meson.build\nindex dc6941d..cc30dc8 100644\n--- a/drivers/raw/ifpga/meson.build\n+++ b/drivers/raw/ifpga/meson.build\n@@ -14,7 +14,8 @@ deps += ['ethdev', 'rawdev', 'pci', 'bus_pci', 'kvargs',\n 'bus_vdev', 'bus_ifpga', 'net', 'net_i40e', 'net_ipn3ke']\n \n sources = files('ifpga_rawdev.c', 'rte_pmd_ifpga.c', 'afu_pmd_core.c',\n- 'afu_pmd_n3000.c', 'afu_pmd_he_lpbk.c', 'afu_pmd_he_mem.c')\n+ 'afu_pmd_n3000.c', 'afu_pmd_he_lpbk.c', 'afu_pmd_he_mem.c',\n+ 'afu_pmd_he_hssi.c')\n \n includes += include_directories('base')\n includes += include_directories('../../net/ipn3ke')\ndiff --git a/drivers/raw/ifpga/rte_pmd_afu.h b/drivers/raw/ifpga/rte_pmd_afu.h\nindex 213e854..cea1ea3 100644\n--- a/drivers/raw/ifpga/rte_pmd_afu.h\n+++ b/drivers/raw/ifpga/rte_pmd_afu.h\n@@ -111,6 +111,22 @@ struct rte_pmd_afu_he_mem_tg_cfg {\n \tuint32_t channel_mask; /* mask of traffic generator channel */\n };\n \n+/**\n+ * HE-HSSI AFU configuration data structure.\n+ */\n+struct rte_pmd_afu_he_hssi_cfg {\n+\tuint32_t port;\n+\tuint32_t timeout;\n+\tuint32_t num_packets;\n+\tuint32_t random_length;\n+\tuint32_t packet_length;\n+\tuint32_t random_payload;\n+\tuint32_t rnd_seed[3];\n+\tuint64_t src_addr;\n+\tuint64_t dest_addr;\n+\tint he_loopback;\n+};\n+\n #ifdef __cplusplus\n }\n #endif\n", "prefixes": [ "v6", "5/5" ] }