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GET /api/patches/112324/?format=api
{ "id": 112324, "url": "https://patches.dpdk.org/api/patches/112324/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220604162651.3503338-8-tduszynski@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220604162651.3503338-8-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220604162651.3503338-8-tduszynski@marvell.com", "date": "2022-06-04T16:26:48", "name": "[07/10] raw/cnxk_bphy: support changing CPRI misc settings", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6cde6a56c6260161accb360792c00de1493ceb9a", "submitter": { "id": 2215, "url": "https://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220604162651.3503338-8-tduszynski@marvell.com/mbox/", "series": [ { "id": 23325, "url": "https://patches.dpdk.org/api/series/23325/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=23325", "date": "2022-06-04T16:26:41", "name": "Sync BPHY changes", "version": 1, "mbox": "https://patches.dpdk.org/series/23325/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/112324/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/112324/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 03040A034C;\n\tSat, 4 Jun 2022 18:29:40 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3BECF427F3;\n\tSat, 4 Jun 2022 18:29:39 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 40701427F2\n for <dev@dpdk.org>; Sat, 4 Jun 2022 18:29:37 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 254GFNCM005477;\n Sat, 4 Jun 2022 09:27:34 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gg6wq0dhc-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Sat, 04 Jun 2022 09:27:34 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 4 Jun 2022 09:27:32 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sat, 4 Jun 2022 09:27:32 -0700", "from localhost.localdomain (unknown [10.28.34.39])\n by maili.marvell.com (Postfix) with ESMTP id 3DE793F70AB;\n Sat, 4 Jun 2022 09:27:29 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=dWhmKrCjobjsF7q6naehW9rbPivSCIGdzGKFNChJWqk=;\n b=iET1OTr4O/gAk432YqWC9nEd7n+gl39Rcd7IqvzWOTlr6x0HE+QccZ1FxGgidDaGQinS\n IZvKuhDcnfMtW8H/YfBWN6aTrVtgyEI9gZhe6nG2dFB209xZumLOynX/G9XSId6FtHwW\n b4tq8dUjcxjCx6XEvm2HtlJVvXguMn/px3cuTdUW3oKQRGwm9IzGBZ52M0Y/ctWVwJK8\n gVYFnNqCMFL8otRhGSLb+9FgcTVZgk5MOzaPta0Ekwe2i25yw/R2Fc/04J2EUSy+xTdg\n +5UtHT2OPZcOoByegBC7JttWoUwfKTSkFvlf0OUMBtf7CVSiO/yGH1LkhaxYL8frwSxs jw==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "<dev@dpdk.org>, Jakub Palider <jpalider@marvell.com>, Tomasz Duszynski\n <tduszynski@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>,\n \"Kiran Kumar K\" <kirankumark@marvell.com>,\n Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<thomas@monjalon.net>, <jerinj@marvell.com>", "Subject": "[PATCH 07/10] raw/cnxk_bphy: support changing CPRI misc settings", "Date": "Sat, 4 Jun 2022 18:26:48 +0200", "Message-ID": "<20220604162651.3503338-8-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220604162651.3503338-1-tduszynski@marvell.com>", "References": "<20220604162651.3503338-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "gS2DYty29RYNYpyn-GvrkU78JGzcjwI2", "X-Proofpoint-GUID": "gS2DYty29RYNYpyn-GvrkU78JGzcjwI2", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514\n definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for changing miscellaneous CPRI settings.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\nReviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>\n---\n doc/guides/rawdevs/cnxk_bphy.rst | 11 ++++++++\n drivers/common/cnxk/roc_bphy_cgx.c | 30 +++++++++++++++++++++\n drivers/common/cnxk/roc_bphy_cgx.h | 8 ++++++\n drivers/common/cnxk/roc_bphy_cgx_priv.h | 6 +++++\n drivers/common/cnxk/version.map | 1 +\n drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 10 +++++++\n drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 36 +++++++++++++++++++++++++\n 7 files changed, 102 insertions(+)", "diff": "diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst\nindex 50ee9bdaa6..2490912534 100644\n--- a/doc/guides/rawdevs/cnxk_bphy.rst\n+++ b/doc/guides/rawdevs/cnxk_bphy.rst\n@@ -121,6 +121,17 @@ Prior to sending actual message payload i.e\n ``struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl`` needs to be filled with relevant\n information.\n \n+Change CPRI misc settings\n+~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+Message is used to change misc CPRI settings, for example to reset RX state\n+machine on CPRI SERDES.\n+\n+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC``.\n+Prior to sending actual message payload i.e\n+``struct cnxk_bphy_cgx_msg_cpri_mode_misc`` needs to be filled with relevant\n+information.\n+\n BPHY PMD\n --------\n \ndiff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c\nindex ee0198924e..4b62905164 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx.c\n+++ b/drivers/common/cnxk/roc_bphy_cgx.c\n@@ -519,3 +519,33 @@ roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx,\n \n \treturn roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);\n }\n+\n+int\n+roc_bphy_cgx_cpri_mode_misc(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n+\t\t\t struct roc_bphy_cgx_cpri_mode_misc *mode)\n+{\n+\tuint64_t scr1, scr0;\n+\n+\tif (!(roc_model_is_cnf95xxn_a0() ||\n+\t roc_model_is_cnf95xxn_a1() ||\n+\t roc_model_is_cnf95xxn_b0()))\n+\t\treturn -ENOTSUP;\n+\n+\tif (!roc_cgx)\n+\t\treturn -EINVAL;\n+\n+\tif (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))\n+\t\treturn -ENODEV;\n+\n+\tif (!mode)\n+\t\treturn -EINVAL;\n+\n+\tscr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_CPRI_MISC) |\n+\t FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_GSERC_IDX,\n+\t\t\t mode->gserc_idx) |\n+\t FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_LANE_IDX,\n+\t\t\t mode->lane_idx) |\n+\t FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_FLAGS, mode->flags);\n+\n+\treturn roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);\n+}\ndiff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h\nindex b8023cce88..3b645eb130 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx.h\n+++ b/drivers/common/cnxk/roc_bphy_cgx.h\n@@ -106,6 +106,12 @@ struct roc_bphy_cgx_cpri_mode_tx_ctrl {\n \tbool enable;\n };\n \n+struct roc_bphy_cgx_cpri_mode_misc {\n+\tint gserc_idx;\n+\tint lane_idx;\n+\tint flags;\n+};\n+\n __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);\n __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);\n \n@@ -138,5 +144,7 @@ __roc_api int roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsign\n \t\t\t\t\t struct roc_bphy_cgx_cpri_mode_change *mode);\n __roc_api int roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n \t\t\t\t\t\tstruct roc_bphy_cgx_cpri_mode_tx_ctrl *mode);\n+__roc_api int roc_bphy_cgx_cpri_mode_misc(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n+\t\t\t\t\t struct roc_bphy_cgx_cpri_mode_misc *mode);\n \n #endif /* _ROC_BPHY_CGX_H_ */\ndiff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h\nindex 96db34f6a1..a1a4239cbe 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h\n+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h\n@@ -71,6 +71,7 @@ enum eth_cmd_id {\n \tETH_CMD_SET_PTP_MODE = 34,\n \tETH_CMD_CPRI_MODE_CHANGE = 35,\n \tETH_CMD_CPRI_TX_CONTROL = 36,\n+\tETH_CMD_CPRI_MISC = 42,\n };\n \n /* event types - cause of interrupt */\n@@ -147,6 +148,11 @@ enum eth_cmd_own {\n #define SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX GENMASK_ULL(15, 12)\n #define SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE BIT_ULL(16)\n \n+/* struct cpri_mode_misc_args */\n+#define SCR1_CPRI_MODE_MISC_ARGS_GSERC_IDX GENMASK_ULL(11, 8)\n+#define SCR1_CPRI_MODE_MISC_ARGS_LANE_IDX GENMASK_ULL(15, 12)\n+#define SCR1_CPRI_MODE_MISC_ARGS_FLAGS GENMASK_ULL(17, 16)\n+\n #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)\n \n #endif /* _ROC_BPHY_CGX_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex a6183799a9..d5fd1f41c2 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -29,6 +29,7 @@ INTERNAL {\n \troc_ae_fpm_put;\n \troc_aes_xcbc_key_derive;\n \troc_bphy_cgx_cpri_mode_change;\n+\troc_bphy_cgx_cpri_mode_misc;\n \troc_bphy_cgx_cpri_mode_tx_control;\n \troc_bphy_cgx_dev_fini;\n \troc_bphy_cgx_dev_init;\ndiff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\nindex bdc65a7f2a..de1c372334 100644\n--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\n+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\n@@ -59,10 +59,12 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,\n \tstruct cnxk_bphy_cgx_msg_cpri_mode_change *cpri_mode;\n \tstruct cnxk_bphy_cgx_msg_set_link_state *link_state;\n \tstruct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl *tx_ctrl;\n+\tstruct cnxk_bphy_cgx_msg_cpri_mode_misc *mode_misc;\n \tstruct cnxk_bphy_cgx_msg *msg = buf->buf_addr;\n \tstruct cnxk_bphy_cgx_msg_link_mode *link_mode;\n \tstruct cnxk_bphy_cgx_msg_link_info *link_info;\n \tstruct roc_bphy_cgx_cpri_mode_change rcpri_mode;\n+\tstruct roc_bphy_cgx_cpri_mode_misc rmode_misc;\n \tstruct roc_bphy_cgx_cpri_mode_tx_ctrl rtx_ctrl;\n \tstruct roc_bphy_cgx_link_info rlink_info;\n \tstruct roc_bphy_cgx_link_mode rlink_mode;\n@@ -159,6 +161,14 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,\n \t\tret = roc_bphy_cgx_cpri_mode_tx_control(cgx->rcgx, lmac,\n \t\t\t\t\t\t\t&rtx_ctrl);\n \t\tbreak;\n+\tcase CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC:\n+\t\tmode_misc = msg->data;\n+\t\tmemset(&rmode_misc, 0, sizeof(rmode_misc));\n+\t\trmode_misc.gserc_idx = mode_misc->gserc_idx;\n+\t\trmode_misc.lane_idx = mode_misc->lane_idx;\n+\t\trmode_misc.flags = mode_misc->flags;\n+\t\tret = roc_bphy_cgx_cpri_mode_misc(cgx->rcgx, lmac, &rmode_misc);\n+\t\tbreak;\n \tdefault:\n \t\treturn -EINVAL;\n \t}\ndiff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h\nindex 79bb2233bc..86e58e4756 100644\n--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h\n+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h\n@@ -54,6 +54,8 @@ enum cnxk_bphy_cgx_msg_type {\n \tCNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE,\n \t/** Type used to enable TX for CPRI SERDES */\n \tCNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL,\n+\t/** Type use to change misc CPRI SERDES settings */\n+\tCNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC,\n };\n \n /** Available link speeds */\n@@ -197,6 +199,15 @@ struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl {\n \tbool enable;\n };\n \n+struct cnxk_bphy_cgx_msg_cpri_mode_misc {\n+\t/** SERDES index (0 - 4) */\n+\tint gserc_idx;\n+\t/** Lane index (0 - 1) */\n+\tint lane_idx;\n+\t/** Misc flags (0 - RX Eq, 1 - RX state machine reset) */\n+\tint flags;\n+};\n+\n struct cnxk_bphy_cgx_msg {\n \t/** Message type */\n \tenum cnxk_bphy_cgx_msg_type type;\n@@ -770,6 +781,31 @@ rte_pmd_bphy_cgx_cpri_tx_control(uint16_t dev_id, uint16_t lmac,\n \treturn __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);\n }\n \n+/**\n+ * CPRI misc settings\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param lmac\n+ * LMAC number for operation\n+ * @param mode\n+ * CPRI settings holding misc control data\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n+static __rte_always_inline int\n+rte_pmd_bphy_cgx_cpri_mode_misc(uint16_t dev_id, uint16_t lmac,\n+\t\t\t\tstruct cnxk_bphy_cgx_msg_cpri_mode_misc *mode)\n+{\n+\tstruct cnxk_bphy_cgx_msg msg = {\n+\t\t.type = CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC,\n+\t\t.data = mode,\n+\t};\n+\n+\treturn __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);\n+}\n+\n #ifdef __cplusplus\n }\n #endif\n", "prefixes": [ "07/10" ] }