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GET /api/patches/110768/?format=api
{ "id": 110768, "url": "https://patches.dpdk.org/api/patches/110768/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220506035645.4101714-7-spiked@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220506035645.4101714-7-spiked@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220506035645.4101714-7-spiked@nvidia.com", "date": "2022-05-06T03:56:44", "name": "[RFC,v1,6/7] net/mlx5: add private API to config host port shaper", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "cf337e381529217466184595f76628e724172011", "submitter": { "id": 2637, "url": "https://patches.dpdk.org/api/people/2637/?format=api", "name": "Spike Du", "email": "spiked@nvidia.com" }, "delegate": { "id": 3961, "url": "https://patches.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220506035645.4101714-7-spiked@nvidia.com/mbox/", "series": [ { "id": 22804, "url": "https://patches.dpdk.org/api/series/22804/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=22804", "date": "2022-05-06T03:56:38", "name": "net/mlx5: introduce limit watermark and host shaper", "version": 1, "mbox": "https://patches.dpdk.org/series/22804/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/110768/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/110768/checks/", "tags": {}, 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port shaper", "Date": "Fri, 6 May 2022 06:56:44 +0300", "Message-ID": "<20220506035645.4101714-7-spiked@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20220506035645.4101714-1-spiked@nvidia.com>", "References": "<20220401032232.1267376-2-spiked@nvidia.com>\n <20220506035645.4101714-1-spiked@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "33f55f53-8778-4171-f647-08da2f148200", "X-MS-TrafficTypeDiagnostic": "DM5PR1201MB2552:EE_", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <DM5PR1201MB2552A6443BB922AED5B7FF3CA8C59@DM5PR1201MB2552.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n EgiRNr7166pfH+qOBfW8TSDCn6lcZon7/b+IzoahcjylVkIXXnGT7ZzV3x6UBI3HWXDMGJg2OVa884AstrwcS0pfRVHVzIkj2fZUO9MM/dkUUnU661YHqcHE81r8XRVSeJwr6zVG/9LWBKhFR9CqZjBXIVQc4I+g/N5/UHRH9z7TOGysl1nwOK0oTzR6lwVmBlSHCDjZp7iimOlwZA/JTImDvuZG4LdMV+PP5F26FDmxVR63ZMfgRPLvLSlV4lXpdO9i06tt5pgyvhNyGvsfS1piWqX7L3B+R8RslqYzKH1UT99fFZhcYHdlS+Xs5xOJE2J/GW2Y1rAKHBvMl8mEZpNi+ydkWmb/dlOZ6Ku2DcC9PvKfjYnBw2MNj1zN5O/ap1dwKylwYSS46NbO/BdnY3jvwHVl4Mr+hIrb8tQUZUYHg7ECOVixX2X7H2mj63ommTjYIrmb7NJY0g19reMhKFm1/eAj9avgOYMIWS0AhDPdOaP/nuF0duNGnHOSho8ADP2HTtcEBLtNRdChvloAnME45V96CORNxv/HHfjLCe7FFZrXucbZ4z7AUAc5XUXPXSS74rEjnrjSsZlLiG46noiVBBxlSFuTJdfekyNzdJ6GcZuVqzXDEktp85hSL/cGfsESF0OxazgOdgyXPH6QmhKb0/RdBY1TGLNam/0tLZ27QplnTeAPmMlSMOwAz+72nqKuODlk36tHf001XYDZGw==", "X-Forefront-Antispam-Report": "CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(6286002)(86362001)(6666004)(7696005)(26005)(36860700001)(426003)(356005)(16526019)(81166007)(186003)(336012)(1076003)(107886003)(40460700003)(47076005)(2616005)(83380400001)(5660300002)(316002)(8676002)(70206006)(4326008)(70586007)(55016003)(82310400005)(36756003)(30864003)(2906002)(54906003)(8936002)(110136005)(508600001)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 May 2022 03:57:15.1111 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 33f55f53-8778-4171-f647-08da2f148200", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT068.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR1201MB2552", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Host port shaper can be configured with QSHR(QoS Shaper Host Register).\nAdd check in build files to enable this function or not.\n\nThe host shaper configuration affects all the ethdev ports belonging to the\nsame host port.\n\nHost shaper can configure shaper rate and lwm-triggered for a host port.\nThe shaper limits the rate of traffic from host port to wire port.\nIf lwm-triggered is enabled, a 100Mbps shaper is enabled automatically\nwhen one of the host port's Rx queues receives LWM(Limit Watermark) event.\n\nSigned-off-by: Spike Du <spiked@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 7 +++\n doc/guides/rel_notes/release_22_07.rst | 1 +\n drivers/common/mlx5/linux/meson.build | 44 +++++++++-----\n drivers/common/mlx5/mlx5_prm.h | 25 ++++++++\n drivers/net/mlx5/mlx5.h | 2 +\n drivers/net/mlx5/mlx5_rx.c | 103 +++++++++++++++++++++++++++++++++\n drivers/net/mlx5/rte_pmd_mlx5.h | 30 ++++++++++\n drivers/net/mlx5/version.map | 2 +\n 8 files changed, 199 insertions(+), 15 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex a7698c9..4e2ebff 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -93,6 +93,7 @@ Features\n - Sub-Function representors.\n - Sub-Function.\n - Rx queue LWM (Limit WaterMark) configuration.\n+- Host shaper support.\n \n \n Limitations\n@@ -522,6 +523,12 @@ Limitations\n - LWM:\n - Doesn't support shared Rx queue and Hairpin Rx queue.\n \n+- Host shaper:\n+\n+ - Support BlueField series NIC from BlueField 2.\n+ - When configure host shaper with MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED flag set,\n+ only rate 0 and 100Mbps are supported.\n+\n Statistics\n ----------\n \ndiff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst\nindex f3cf2f1..96083eb 100644\n--- a/doc/guides/rel_notes/release_22_07.rst\n+++ b/doc/guides/rel_notes/release_22_07.rst\n@@ -65,6 +65,7 @@ New Features\n * Added support for promiscuous mode on Windows.\n * Added support for MTU on Windows.\n * Added Rx queue LWM(Limit WaterMark) support.\n+ * Added host shaper support.\n \n \n Removed Items\ndiff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build\nindex ed48245..e332261 100644\n--- a/drivers/common/mlx5/linux/meson.build\n+++ b/drivers/common/mlx5/linux/meson.build\n@@ -16,23 +16,24 @@ if dlopen_ibverbs\n ]\n endif\n \n-libnames = [ 'mlx5', 'ibverbs' ]\n+libnames = [ 'mlx5', 'ibverbs']\n libs = []\n foreach libname:libnames\n- lib = dependency('lib' + libname, static:static_ibverbs, required:false, method: 'pkg-config')\n- if not lib.found() and not static_ibverbs\n- lib = cc.find_library(libname, required:false)\n- endif\n- if lib.found()\n- libs += lib\n- if not static_ibverbs and not dlopen_ibverbs\n- ext_deps += lib\n- endif\n- else\n- build = false\n- reason = 'missing dependency, \"' + libname + '\"'\n- subdir_done()\n- endif\n+\tlib = dependency('lib' + libname, static:static_ibverbs,\n+\t\t\trequired:false, method: 'pkg-config')\n+\tif not lib.found() and not static_ibverbs\n+\t\tlib = cc.find_library(libname, required:false)\n+\tendif\n+\tif lib.found()\n+\t\tlibs += lib\n+\t\tif not static_ibverbs and not dlopen_ibverbs\n+\t\t\text_deps += lib\n+\t\tendif\n+\telse\n+\t\tbuild = false\n+\t\treason = 'missing dependency, \"' + libname + '\"'\n+\t\tsubdir_done()\n+\tendif\n endforeach\n if static_ibverbs or dlopen_ibverbs\n # Build without adding shared libs to Requires.private\n@@ -45,6 +46,13 @@ if static_ibverbs\n ext_deps += declare_dependency(link_args:ibv_ldflags.split())\n endif\n \n+libmtcr_ul_found = false\n+lib = cc.find_library('mtcr_ul', required:false)\n+if lib.found() and run_command('meson', '--version').stdout().version_compare('>= 0.49.2')\n+\tlibmtcr_ul_found = true\n+\text_deps += lib\n+endif\n+\n sources += files('mlx5_nl.c')\n sources += files('mlx5_common_auxiliary.c')\n sources += files('mlx5_common_os.c')\n@@ -205,6 +213,12 @@ has_sym_args = [\n [ 'HAVE_MLX5_IBV_IMPORT_CTX_PD_AND_MR', 'infiniband/verbs.h',\n 'ibv_import_device' ],\n ]\n+if libmtcr_ul_found\n+ has_sym_args += [\n+ [ 'HAVE_MLX5_MSTFLINT', 'mstflint/mtcr.h',\n+ 'mopen'],\n+ ]\n+endif\n config = configuration_data()\n foreach arg:has_sym_args\n config.set(arg[0], cc.has_header_symbol(arg[1], arg[2], dependencies: libs))\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 23b13e3..3559927 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -3768,6 +3768,7 @@ enum {\n \tMLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003,\n \tMLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004,\n \tMLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005,\n+\tMLX5_QSHR_REGISTER_ID = 0x4030,\n };\n \n struct mlx5_ifc_register_mtutc_bits {\n@@ -3782,6 +3783,30 @@ struct mlx5_ifc_register_mtutc_bits {\n \tu8 time_adjustment[0x20];\n };\n \n+struct mlx5_ifc_ets_global_config_register_bits {\n+\tu8 reserved_at_0[0x2];\n+\tu8 rate_limit_update[0x1];\n+\tu8 reserved_at_3[0x29];\n+\tu8 max_bw_units[0x4];\n+\tu8 reserved_at_48[0x8];\n+\tu8 max_bw_value[0x8];\n+};\n+\n+#define ETS_GLOBAL_CONFIG_BW_UNIT_DISABLED 0x0\n+#define ETS_GLOBAL_CONFIG_BW_UNIT_HUNDREDS_MBPS 0x3\n+#define ETS_GLOBAL_CONFIG_BW_UNIT_GBPS 0x4\n+\n+struct mlx5_ifc_register_qshr_bits {\n+\tu8 reserved_at_0[0x4];\n+\tu8 connected_host[0x1];\n+\tu8 vqos[0x1];\n+\tu8 fast_response[0x1];\n+\tu8 reserved_at_7[0x1];\n+\tu8 local_port[0x8];\n+\tu8 reserved_at_16[0x230];\n+\tstruct mlx5_ifc_ets_global_config_register_bits global_config;\n+};\n+\n #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0\n #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1\n \ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 515ff33..5dfd375 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1267,6 +1267,8 @@ struct mlx5_dev_ctx_shared {\n \tvoid *devx_channel_lwm;\n \tstruct rte_intr_handle *intr_handle_lwm;\n \tpthread_mutex_t lwm_config_lock;\n+\tuint32_t host_shaper_rate:8;\n+\tuint32_t lwm_triggered:1;\n \t/* Availability of mreg_c's. */\n \tstruct mlx5_dev_shared_port port[]; /* per device port data array. */\n };\ndiff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c\nindex 68564ea..cc68a91 100644\n--- a/drivers/net/mlx5/mlx5_rx.c\n+++ b/drivers/net/mlx5/mlx5_rx.c\n@@ -28,6 +28,9 @@\n #include \"mlx5_rxtx.h\"\n #include \"mlx5_devx.h\"\n #include \"mlx5_rx.h\"\n+#ifdef HAVE_MLX5_MSTFLINT\n+#include <mstflint/mtcr.h>\n+#endif\n \n \n static __rte_always_inline uint32_t\n@@ -1337,3 +1340,103 @@ int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)\n \treturn ret;\n }\n \n+/**\n+ * Mlx5 access register function to configure host shaper.\n+ * It calls API in libmtcr_ul to access QSHR(Qos Shaper Host Register)\n+ * in firmware.\n+ *\n+ * @param dev\n+ * Pointer to rte_eth_dev.\n+ * @param lwm_triggered\n+ * Flag to enable/disable lwm_triggered bit in QSHR.\n+ * @param rate\n+ * Host shaper rate, unit is 100Mbps, set to 0 means disable the shaper.\n+ * @return\n+ * 0 : operation success.\n+ * Otherwise:\n+ * - ENOENT - no ibdev interface.\n+ * - EBUSY - the register access unit is busy.\n+ * - EIO - the register access command meets IO error.\n+ */\n+static int\n+mlxreg_config_host_shaper(struct rte_eth_dev *dev,\n+\t\t\t bool lwm_triggered, uint8_t rate)\n+{\n+#ifdef HAVE_MLX5_MSTFLINT\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tuint32_t data[MLX5_ST_SZ_DW(register_qshr)] = {0};\n+\tint rc, retry_count = 3;\n+\tmfile *mf = NULL;\n+\tint status;\n+\tvoid *ptr;\n+\n+\tmf = mopen(priv->sh->ibdev_name);\n+\tif (!mf) {\n+\t\tDRV_LOG(WARNING, \"mopen failed\\n\");\n+\t\trte_errno = ENOENT;\n+\t\treturn -rte_errno;\n+\t}\n+\tMLX5_SET(register_qshr, data, connected_host, 1);\n+\tMLX5_SET(register_qshr, data, fast_response, lwm_triggered ? 1 : 0);\n+\tMLX5_SET(register_qshr, data, local_port, 1);\n+\tptr = MLX5_ADDR_OF(register_qshr, data, global_config);\n+\tMLX5_SET(ets_global_config_register, ptr, rate_limit_update, 1);\n+\tMLX5_SET(ets_global_config_register, ptr, max_bw_units,\n+\t\t rate ? ETS_GLOBAL_CONFIG_BW_UNIT_HUNDREDS_MBPS :\n+\t\t ETS_GLOBAL_CONFIG_BW_UNIT_DISABLED);\n+\tMLX5_SET(ets_global_config_register, ptr, max_bw_value, rate);\n+\tdo {\n+\t\trc = maccess_reg(mf,\n+\t\t\t\t MLX5_QSHR_REGISTER_ID,\n+\t\t\t\t MACCESS_REG_METHOD_SET,\n+\t\t\t\t (u_int32_t *)&data[0],\n+\t\t\t\t sizeof(data),\n+\t\t\t\t sizeof(data),\n+\t\t\t\t sizeof(data),\n+\t\t\t\t &status);\n+\t\tif ((rc != ME_ICMD_STATUS_IFC_BUSY &&\n+\t\t status != ME_REG_ACCESS_BAD_PARAM) ||\n+\t\t !(mf->flags & MDEVS_REM)) {\n+\t\t\tbreak;\n+\t\t}\n+\t\tDRV_LOG(WARNING, \"%s retry.\", __func__);\n+\t\tusleep(10000);\n+\t} while (retry_count-- > 0);\n+\tmclose(mf);\n+\trte_errno = (rc == ME_REG_ACCESS_DEV_BUSY) ? EBUSY : EIO;\n+\treturn rc ? -rte_errno : 0;\n+#else\n+\t(void)dev;\n+\t(void)lwm_triggered;\n+\t(void)rate;\n+\treturn -1;\n+#endif\n+}\n+\n+int rte_pmd_mlx5_config_host_shaper(int port_id, uint8_t rate,\n+\t\t\t\t uint32_t flags)\n+{\n+\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tbool lwm_triggered =\n+\t\t!!(flags & RTE_BIT32(MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED));\n+\n+\tif (!lwm_triggered) {\n+\t\tpriv->sh->host_shaper_rate = rate;\n+\t} else {\n+\t\tswitch (rate) {\n+\t\tcase 0:\n+\t\t/* Rate 0 means disable lwm_triggered. */\n+\t\t\tpriv->sh->lwm_triggered = 0;\n+\t\t\tbreak;\n+\t\tcase 1:\n+\t\t/* Rate 1 means enable lwm_triggered. */\n+\t\t\tpriv->sh->lwm_triggered = 1;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -ENOTSUP;\n+\t\t}\n+\t}\n+\treturn mlxreg_config_host_shaper(dev, priv->sh->lwm_triggered,\n+\t\t\t\t\t priv->sh->host_shaper_rate);\n+}\ndiff --git a/drivers/net/mlx5/rte_pmd_mlx5.h b/drivers/net/mlx5/rte_pmd_mlx5.h\nindex 6e7907e..d0e8cae 100644\n--- a/drivers/net/mlx5/rte_pmd_mlx5.h\n+++ b/drivers/net/mlx5/rte_pmd_mlx5.h\n@@ -109,6 +109,36 @@ int rte_pmd_mlx5_external_rx_queue_id_map(uint16_t port_id, uint16_t dpdk_idx,\n int rte_pmd_mlx5_external_rx_queue_id_unmap(uint16_t port_id,\n \t\t\t\t\t uint16_t dpdk_idx);\n \n+/**\n+ * The rate of the host port shaper will be updated directly at the next\n+ * LWM event to the rate that comes with this flag set; set rate 0\n+ * to disable this rate update.\n+ * Unset this flag to update the rate of the host port shaper directly in\n+ * the API call; use rate 0 to disable the current shaper.\n+ */\n+#define MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED 0\n+\n+/**\n+ * Configure an HW shaper to limit Rx rate for a host port.\n+ * The configuration will affect all the ethdev ports belonging to\n+ * the same rte_device.\n+ *\n+ * @param[in] port_id\n+ * The port identifier of the Ethernet device.\n+ * @param[in] rate\n+ * Unit is 100Mbps, setting the rate to 0 disables the shaper.\n+ * @param[in] flags\n+ * Host shaper flags.\n+ * @return\n+ * 0 : operation success.\n+ * Otherwise:\n+ * - ENOENT - no ibdev interface.\n+ * - EBUSY - the register access unit is busy.\n+ * - EIO - the register access command meets IO error.\n+ */\n+__rte_experimental\n+int rte_pmd_mlx5_config_host_shaper(int port_id, uint8_t rate, uint32_t flags);\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/drivers/net/mlx5/version.map b/drivers/net/mlx5/version.map\nindex 79cb79a..905ab30 100644\n--- a/drivers/net/mlx5/version.map\n+++ b/drivers/net/mlx5/version.map\n@@ -12,4 +12,6 @@ EXPERIMENTAL {\n \t# added in 22.03\n \trte_pmd_mlx5_external_rx_queue_id_map;\n \trte_pmd_mlx5_external_rx_queue_id_unmap;\n+\t# added in 22.07\n+\trte_pmd_mlx5_config_host_shaper;\n };\n", "prefixes": [ "RFC", "v1", "6/7" ] }