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GET /api/patches/110297/?format=api
{ "id": 110297, "url": "https://patches.dpdk.org/api/patches/110297/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220427070624.9258-1-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220427070624.9258-1-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220427070624.9258-1-pbhagavatula@marvell.com", "date": "2022-04-27T07:06:24", "name": "event/cnxk: add SLMTST support to Tx adapter", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7f76d412e4f221bedf9d7749a3187bcd314253f2", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220427070624.9258-1-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 22681, "url": "https://patches.dpdk.org/api/series/22681/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=22681", "date": "2022-04-27T07:06:24", "name": "event/cnxk: add SLMTST support to Tx adapter", "version": 1, "mbox": "https://patches.dpdk.org/series/22681/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/110297/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/110297/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 92720A0510;\n\tWed, 27 Apr 2022 09:06:37 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2B2A740E78;\n\tWed, 27 Apr 2022 09:06:37 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 2C4DD40691\n for <dev@dpdk.org>; Wed, 27 Apr 2022 09:06:35 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 23QLapYS015982;\n Wed, 27 Apr 2022 00:06:31 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3fprt4hnuj-20\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Wed, 27 Apr 2022 00:06:31 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 27 Apr 2022 00:06:29 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Wed, 27 Apr 2022 00:06:29 -0700", "from MININT-80QBFE8.corp.innovium.com (unknown [10.193.69.50])\n by maili.marvell.com (Postfix) with ESMTP id 4B2F05B6947;\n Wed, 27 Apr 2022 00:06:26 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=5+BXyLwWJEgaasAdcyxwESQ/gNFqY7aVWtb26CN37Os=;\n b=jmgEPR3oZAC/gVutiwetYzpyFlmylwTihUBaRjOAygnMm2UgWwx9GKRWsfgbtE6MP4Zi\n kAjktN/6NqZ6IzMXRBza/8bh/bosnzAQzSvDDKdWJoapZ7Y3CJ68t2DiTp1smG6Oq/i+\n FlIc/LiPQMYjAUstu0UPIuzd1r+IgLuvvdElLd8ZNr35VCUYsCshTM8089gPV5mOBK+b\n 0yVwM912vHBbGYCAws8fN2AT6f8y6ePT3gZpRMnFGPenu1s0J+0MIkLL/MzjC5yNQXw5\n LR6M+PW0WZKxk3WWUY+GkhI4XFhy49wQQy6Q0pIkbcT33IpU8beVVX/S7R43GPwmfHf2 GQ==", "From": "Pavan Nikhilesh <pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>, \"Pavan\n Nikhilesh\" <pbhagavatula@marvell.com>,\n Shijith Thotton <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH] event/cnxk: add SLMTST support to Tx adapter", "Date": "Wed, 27 Apr 2022 12:36:24 +0530", "Message-ID": "<20220427070624.9258-1-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "SpsykiSCfN6ZCT6VXj-g7iOLsQKhQRTV", "X-Proofpoint-GUID": "SpsykiSCfN6ZCT6VXj-g7iOLsQKhQRTV", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514\n definitions=2022-04-27_02,2022-04-26_02,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Scheduled LMTST uses in-core LSW (LMTST scheduling widget) to\ncoordinate with SSO and send a LMTST to the destination\ncoprocessor without the need for the core to be the head of\nthe scheduling context it is currently holding.\n\nUse SLMTST to send mbuf to NIX-TX for transmit. SLMTST only\nsupports transmitting a single WQE.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n Depends-on: Series-22634\n\n drivers/common/cnxk/hw/ssow.h | 7 +++++++\n drivers/common/cnxk/roc_dev_priv.h | 6 ++++++\n drivers/common/cnxk/roc_io.h | 8 ++++++++\n drivers/common/cnxk/roc_io_generic.h | 7 +++++++\n drivers/common/cnxk/roc_nix.c | 19 +++++++++++++++++++\n drivers/common/cnxk/roc_nix.h | 4 ++++\n drivers/common/cnxk/roc_sso.c | 23 +++++++++++++++++++++++\n drivers/common/cnxk/roc_sso.h | 2 ++\n drivers/common/cnxk/version.map | 2 ++\n drivers/event/cnxk/cn10k_eventdev.c | 11 +++++++++++\n drivers/event/cnxk/cn10k_worker.h | 19 +++++++++++++------\n drivers/event/cnxk/cnxk_eventdev.h | 2 +-\n 12 files changed, 103 insertions(+), 7 deletions(-)\n\n--\n2.25.1", "diff": "diff --git a/drivers/common/cnxk/hw/ssow.h b/drivers/common/cnxk/hw/ssow.h\nindex 618ab7973b..b40238bc6c 100644\n--- a/drivers/common/cnxk/hw/ssow.h\n+++ b/drivers/common/cnxk/hw/ssow.h\n@@ -62,6 +62,13 @@\n #define SSOW_GW_RESULT_GW_NO_WORK (0x1ull) /* [CN10K, .) */\n #define SSOW_GW_RESULT_GW_ERROR\t (0x2ull) /* [CN10K, .) */\n\n+#define SSOW_LSW_MODE_NO_LSW (0x0)\n+#define SSOW_LSW_MODE_WAIT (0x1)\n+#define SSOW_LSW_MODE_IMMED (0x2)\n+\n+#define SSOW_LSW_WQE_RELEASE_WAIT_ACK (0x0)\n+#define SSOW_LSW_WQE_RELEASE_IMMED (0x1)\n+\n #define SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT 63\n #define SSOW_LF_GWS_TAG_PEND_SWITCH_BIT\t 62\n #define SSOW_LF_GWS_TAG_PEND_DESCHED_BIT 58\ndiff --git a/drivers/common/cnxk/roc_dev_priv.h b/drivers/common/cnxk/roc_dev_priv.h\nindex 302dc0feb0..e301487f4c 100644\n--- a/drivers/common/cnxk/roc_dev_priv.h\n+++ b/drivers/common/cnxk/roc_dev_priv.h\n@@ -54,6 +54,12 @@ dev_get_pf(uint16_t pf_func)\n \treturn (pf_func >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;\n }\n\n+static inline int\n+dev_get_func(uint16_t pf_func)\n+{\n+\treturn (pf_func >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK;\n+}\n+\n static inline int\n dev_pf_func(int pf, int vf)\n {\ndiff --git a/drivers/common/cnxk/roc_io.h b/drivers/common/cnxk/roc_io.h\nindex 62e98d9d00..6a76e3fa71 100644\n--- a/drivers/common/cnxk/roc_io.h\n+++ b/drivers/common/cnxk/roc_io.h\n@@ -154,6 +154,14 @@ roc_lmt_submit_steorl(uint64_t data, plt_iova_t io_address)\n \t\t [rs] \"r\"(io_address));\n }\n\n+static __plt_always_inline void\n+roc_lmt_submit_stsmaxl(uint64_t data, plt_iova_t io_address)\n+{\n+\tasm volatile(\".cpu generic+lse\\n\"\n+\t\t \"stsmaxl %x[d], [%[rs]]\" ::[d] \"r\"(data),\n+\t\t [rs] \"r\"(io_address));\n+}\n+\n static __plt_always_inline void\n roc_lmt_mov(void *out, const void *in, const uint32_t lmtext)\n {\ndiff --git a/drivers/common/cnxk/roc_io_generic.h b/drivers/common/cnxk/roc_io_generic.h\nindex 42764455cc..097ed8af09 100644\n--- a/drivers/common/cnxk/roc_io_generic.h\n+++ b/drivers/common/cnxk/roc_io_generic.h\n@@ -98,6 +98,13 @@ roc_lmt_submit_steorl(uint64_t data, plt_iova_t io_address)\n \tPLT_SET_USED(io_address);\n }\n\n+static __plt_always_inline void\n+roc_lmt_submit_stsmaxl(uint64_t data, plt_iova_t io_address)\n+{\n+\tPLT_SET_USED(data);\n+\tPLT_SET_USED(io_address);\n+}\n+\n static __plt_always_inline void\n roc_lmt_mov(void *out, const void *in, const uint32_t lmtext)\n {\ndiff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c\nindex 151d8c3426..16d707b5ff 100644\n--- a/drivers/common/cnxk/roc_nix.c\n+++ b/drivers/common/cnxk/roc_nix.c\n@@ -139,6 +139,25 @@ roc_nix_max_pkt_len(struct roc_nix *roc_nix)\n \treturn NIX_RPM_MAX_HW_FRS;\n }\n\n+int\n+roc_nix_sched_lmt_enable(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct lmtst_tbl_setup_req *req;\n+\n+\treq = mbox_alloc_msg_lmtst_tbl_setup(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\treq->pcifunc = 0;\n+\treq->ssow_pf_func = dev_get_pf(idev_sso_pffunc_get()) << 8;\n+\treq->ssow_pf_func |=\n+\t\t(uint64_t)(dev_get_func(idev_sso_pffunc_get()) & 0xFF);\n+\treq->sched_ena = 1;\n+\n+\treturn mbox_process(mbox);\n+}\n+\n int\n roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq,\n \t\t uint64_t rx_cfg)\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex dbb816d961..b985fb5df4 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -904,4 +904,8 @@ int __roc_api roc_nix_mcast_mcam_entry_write(struct roc_nix *roc_nix,\n \t\t\t\t\t uint64_t action);\n int __roc_api roc_nix_mcast_mcam_entry_ena_dis(struct roc_nix *roc_nix,\n \t\t\t\t\t uint32_t index, bool enable);\n+\n+/* SSO */\n+int __roc_api roc_nix_sched_lmt_enable(struct roc_nix *roc_nix);\n+\n #endif /* _ROC_NIX_H_ */\ndiff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c\nindex f8a0a96533..1b76b439d0 100644\n--- a/drivers/common/cnxk/roc_sso.c\n+++ b/drivers/common/cnxk/roc_sso.c\n@@ -344,6 +344,29 @@ roc_sso_hwgrp_stats_get(struct roc_sso *roc_sso, uint8_t hwgrp,\n \treturn 0;\n }\n\n+int\n+roc_sso_hws_config_lsw(struct roc_sso *roc_sso, uint8_t lsw_mode,\n+\t\t uint8_t wqe_release_mode)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct ssow_config_lsw *req;\n+\n+\tif (lsw_mode > SSOW_LSW_MODE_IMMED ||\n+\t wqe_release_mode > SSOW_LSW_WQE_RELEASE_IMMED)\n+\t\treturn -EINVAL;\n+\n+\treq = mbox_alloc_msg_ssow_config_lsw(dev->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\n+\treq->lsw_mode = lsw_mode;\n+\treq->wqe_release = wqe_release_mode;\n+\tif (mbox_process(dev->mbox) < 0)\n+\t\treturn -EIO;\n+\n+\treturn 0;\n+}\n+\n int\n roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso, uint8_t hws,\n \t\t\t uint16_t hwgrp)\ndiff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h\nindex ab7cee1c60..4548f78602 100644\n--- a/drivers/common/cnxk/roc_sso.h\n+++ b/drivers/common/cnxk/roc_sso.h\n@@ -102,6 +102,8 @@ int __roc_api roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws,\n \t\t\t uint16_t hwgrp[], uint16_t nb_hwgrp);\n int __roc_api roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws,\n \t\t\t\t uint16_t hwgrp[], uint16_t nb_hwgrp);\n+int __roc_api roc_sso_hws_config_lsw(struct roc_sso *roc_sso, uint8_t lsw_mode,\n+\t\t\t\t uint8_t wqe_release_mode);\n int __roc_api roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso,\n \t\t\t\t\t uint8_t hws, uint16_t hwgrp);\n uintptr_t __roc_api roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws);\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 2a122e544d..9c3fe1d31a 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -230,6 +230,7 @@ INTERNAL {\n \troc_nix_rx_drop_re_set;\n \troc_nix_rx_queue_intr_disable;\n \troc_nix_rx_queue_intr_enable;\n+\troc_nix_sched_lmt_enable;\n \troc_nix_sq_dump;\n \troc_nix_sq_fini;\n \troc_nix_sq_head_tail_get;\n@@ -348,6 +349,7 @@ INTERNAL {\n \troc_sso_hwgrp_set_priority;\n \troc_sso_hwgrp_stats_get;\n \troc_sso_hws_base_get;\n+\troc_sso_hws_config_lsw;\n \troc_sso_hws_link;\n \troc_sso_hws_stats_get;\n \troc_sso_hws_unlink;\ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex 9b4d2895ec..31dca54ccc 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -57,6 +57,7 @@ cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)\n \tws->swtag_req = 0;\n \tws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);\n \tws->lmt_base = dev->sso.lmt_base;\n+\tws->gw_rdata = (SSO_TT_EMPTY << 32) | BIT_ULL(35);\n\n \treturn ws;\n }\n@@ -567,12 +568,18 @@ cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,\n static int\n cn10k_sso_start(struct rte_eventdev *event_dev)\n {\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n \tint rc;\n\n \trc = cn10k_sso_updt_tx_adptr_data(event_dev);\n \tif (rc < 0)\n \t\treturn rc;\n\n+\trc = roc_sso_hws_config_lsw(&dev->sso, SSO_LSW_MODE_WAITW,\n+\t\t\t\t SSOW_LSW_WQE_RELEASE_IMMED);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n \trc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,\n \t\t\t cn10k_sso_hws_flush_events);\n \tif (rc < 0)\n@@ -756,6 +763,10 @@ cn10k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,\n \tuint64_t tx_offloads;\n \tint rc;\n\n+\trc = roc_nix_sched_lmt_enable(&cnxk_eth_dev->nix);\n+\tif (rc < 0)\n+\t\treturn -EINVAL;\n+\n \tRTE_SET_USED(id);\n \trc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);\n \tif (rc < 0)\ndiff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex c96048f47d..7f36b0020e 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -580,11 +580,18 @@ cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd,\n \telse\n \t\tpa = txq->io_addr | ((segdw - 1) << 4);\n\n-\tif (!CNXK_TAG_IS_HEAD(ws->gw_rdata) && !sched_type)\n-\t\tws->gw_rdata = roc_sso_hws_head_wait(ws->base);\n+\tif (flags & NIX_TX_VWQE_F ||\n+\t CNXK_TT_FROM_TAG(ws->gw_rdata) == SSO_TT_EMPTY) {\n+\t\tif (!CNXK_TAG_IS_HEAD(ws->gw_rdata) && !sched_type)\n+\t\t\tws->gw_rdata = roc_sso_hws_head_wait(ws->base);\n\n-\tcn10k_sso_txq_fc_wait(txq);\n-\troc_lmt_submit_steorl(lmt_id, pa);\n+\t\tcn10k_sso_txq_fc_wait(txq);\n+\t\troc_lmt_submit_steorl(lmt_id, pa);\n+\t} else {\n+\t\tcn10k_sso_txq_fc_wait(txq);\n+\t\troc_lmt_submit_stsmaxl(\n+\t\t\t(uint64_t)lmt_id | (uint64_t)ws->hws_id << 16, pa);\n+\t}\n }\n\n static __rte_always_inline void\n@@ -616,7 +623,7 @@ cn10k_sso_vwqe_split_tx(struct cn10k_sso_hws *ws, struct rte_mbuf **mbufs,\n \t\t\tfor (j = 0; j < 4; j++)\n \t\t\t\tcn10k_sso_tx_one(ws, mbufs[i + j], cmd, lmt_id,\n \t\t\t\t\t\t lmt_addr, sched_type, txq_data,\n-\t\t\t\t\t\t flags);\n+\t\t\t\t\t\t flags | NIX_TX_VWQE_F);\n \t\t} else {\n \t\t\ttxq = (struct cn10k_eth_txq\n \t\t\t\t *)(txq_data[(txq_data[port[0]] >> 48) +\n@@ -632,7 +639,7 @@ cn10k_sso_vwqe_split_tx(struct cn10k_sso_hws *ws, struct rte_mbuf **mbufs,\n\n \tfor (i = 0; i < scalar; i++) {\n \t\tcn10k_sso_tx_one(ws, mbufs[i], cmd, lmt_id, lmt_addr,\n-\t\t\t\t sched_type, txq_data, flags);\n+\t\t\t\t sched_type, txq_data, flags | NIX_TX_VWQE_F);\n \t}\n }\n\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex 5564746e6d..1cf6517e73 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -129,13 +129,13 @@ struct cn10k_sso_hws {\n \tvoid *lookup_mem;\n \tuint32_t gw_wdata;\n \tuint8_t swtag_req;\n-\tuint8_t hws_id;\n \t/* Add Work Fastpath data */\n \tuint64_t xaq_lmt __rte_cache_aligned;\n \tuint64_t *fc_mem;\n \tuintptr_t grp_base;\n \t/* Tx Fastpath data */\n \tuintptr_t lmt_base __rte_cache_aligned;\n+\tuint8_t hws_id;\n \tuint64_t lso_tun_fmt;\n \tuint8_t tx_adptr_data[];\n } __rte_cache_aligned;\n", "prefixes": [] }