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GET /api/patches/108753/?format=api
{ "id": 108753, "url": "https://patches.dpdk.org/api/patches/108753/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220317035036.2290272-1-psatheesh@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220317035036.2290272-1-psatheesh@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220317035036.2290272-1-psatheesh@marvell.com", "date": "2022-03-17T03:50:35", "name": "[1/2] common/cnxk: fix ROC naming convention issues", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d3245c76960cd2d1fc6227d9aab5e6bd22b81839", "submitter": { "id": 1663, "url": "https://patches.dpdk.org/api/people/1663/?format=api", "name": "Satheesh Paul Antonysamy", "email": "psatheesh@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220317035036.2290272-1-psatheesh@marvell.com/mbox/", "series": [ { "id": 22169, "url": "https://patches.dpdk.org/api/series/22169/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=22169", "date": "2022-03-17T03:50:35", "name": "[1/2] common/cnxk: fix ROC naming convention issues", "version": 1, "mbox": "https://patches.dpdk.org/series/22169/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/108753/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/108753/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 54D35A0093;\n\tThu, 17 Mar 2022 04:50:53 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D0B7A407FF;\n\tThu, 17 Mar 2022 04:50:52 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 077A340151;\n Thu, 17 Mar 2022 04:50:51 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 22H3klHH027579;\n Wed, 16 Mar 2022 20:50:50 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3eue23mnwe-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Wed, 16 Mar 2022 20:50:49 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Wed, 16 Mar 2022 20:50:47 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Wed, 16 Mar 2022 20:50:47 -0700", "from localhost.localdomain (unknown [10.28.34.33])\n by maili.marvell.com (Postfix) with ESMTP id B09263F705C;\n Wed, 16 Mar 2022 20:50:45 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=FqVy72DAP0b915GYIQEcThJVEoxfp8Fxu+Taf8Tkw+o=;\n b=GFEOYRo11mqp/tm/1mLGNEqekwXgWVl9PvF9yxIxxrV7KMx5aEZWa/P7LQiVcL20bXLg\n 7kWlgEi0Wyifnf66ItXZPZioMYjmsjKxIZjN18liDptGg9PPwvSVPT7I3+4D2c154wp7\n RscIosHKYfLXoAcQt3pJpNz3FSX/cY7iEyN/KRvQrcdphStPaOiJzGrg7ghQ3vhmI01R\n 5UpH3Ec7/BGWFuY069XKCV9wMDGoJ9HEzRkCE/1fUTUscD7vKe5SWOOj72wpbgojdqJH\n Rj/0S7qjBMSrW1pxHZ/tMluIDtZmjmtyxwdp6dF5zu8JQYq5VTPJVAFAylu/L9IQ3CY+ cA==", "From": "<psatheesh@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Satheesh Paul <psatheesh@marvell.com>, <stable@dpdk.org>", "Subject": "[dpdk-dev] [PATCH 1/2] common/cnxk: fix ROC naming convention issues", "Date": "Thu, 17 Mar 2022 09:20:35 +0530", "Message-ID": "<20220317035036.2290272-1-psatheesh@marvell.com>", "X-Mailer": "git-send-email 2.25.4", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "ovQ2Ze79cGmipCXSukpthrPtY7qLAy0v", "X-Proofpoint-ORIG-GUID": "ovQ2Ze79cGmipCXSukpthrPtY7qLAy0v", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514\n definitions=2022-03-16_09,2022-03-15_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Satheesh Paul <psatheesh@marvell.com>\n\nFixed some names to follow ROC naming convention in ROC NPC code.\n\nFixes: 4edf1246a40 (\"common/cnxk: support matching VLAN existence in RTE Flow\")\nCc: stable@dpdk.org\n\nSigned-off-by: Satheesh Paul <psatheesh@marvell.com>\n---\n drivers/common/cnxk/roc_npc.h | 6 +++---\n drivers/common/cnxk/roc_npc_mcam.c | 4 ++--\n drivers/common/cnxk/roc_platform.h | 2 +-\n 3 files changed, 6 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h\nindex 6204139396..4c0151e2e7 100644\n--- a/drivers/common/cnxk/roc_npc.h\n+++ b/drivers/common/cnxk/roc_npc.h\n@@ -60,7 +60,7 @@ struct roc_npc_flow_item_raw {\n \n struct roc_ether_addr {\n \tuint8_t addr_bytes[PLT_ETHER_ADDR_LEN]; /**< Addr bytes in tx order */\n-} plt_aligned(2);\n+} __plt_aligned(2);\n \n struct roc_ether_hdr {\n \tstruct roc_ether_addr d_addr; /**< Destination address. */\n@@ -72,7 +72,7 @@ struct roc_ether_hdr {\n \t\t} S_un; /**< Do not use directly; use s_addr instead.*/\n \t};\n \tuint16_t ether_type; /**< Frame type. */\n-} plt_aligned(2);\n+} __plt_aligned(2);\n \n PLT_STD_C11\n struct roc_npc_flow_item_eth {\n@@ -254,7 +254,7 @@ enum roc_npc_rss_hash_function {\n struct roc_npc_action_rss {\n \tenum roc_npc_rss_hash_function func;\n \tuint32_t level;\n-\tuint64_t types;\t /**< Specific RSS hash types (see RTE_ETH_RSS_*). */\n+\tuint64_t types;\t /**< Specific RSS hash types (see ETH_RSS_*). */\n \tuint32_t key_len; /**< Hash key length in bytes. */\n \tuint32_t queue_num; /**< Number of entries in @p queue. */\n \tconst uint8_t *key; /**< Hash key. */\ndiff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c\nindex 9c5ff5e60a..e592310bde 100644\n--- a/drivers/common/cnxk/roc_npc_mcam.c\n+++ b/drivers/common/cnxk/roc_npc_mcam.c\n@@ -283,8 +283,8 @@ npc_get_kex_capability(struct npc *npc)\n \t/* Custom L3 frame: varied offset and lengths */\n \tkex_cap.bit.custom_l3 =\n \t\tnpc_is_kex_enabled(npc, NPC_LID_LC, NPC_LT_LC_CUSTOM0, 0, 0);\n-\tkex_cap.bit.custom_l3 |=\n-\t\tnpc_is_kex_enabled(npc, NPC_LID_LC, NPC_LT_LC_CUSTOM1, 0, 0);\n+\tkex_cap.bit.custom_l3 |= (uint64_t)npc_is_kex_enabled(\n+\t\tnpc, NPC_LID_LC, NPC_LT_LC_CUSTOM1, 0, 0);\n \t/* SCTP sport : offset 0B, len 2B */\n \tkex_cap.bit.sctp_sport = npc_is_kex_enabled(\n \t\tnpc, NPC_LID_LD, NPC_LT_LD_SCTP, 0 * 8, 2 * 8);\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 28004b1743..dd6514eb10 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -98,7 +98,7 @@\n #define plt_cpu_to_be_64 rte_cpu_to_be_64\n #define plt_be_to_cpu_64 rte_be_to_cpu_64\n \n-#define plt_aligned\t __rte_aligned\n+#define __plt_aligned\t __rte_aligned\n #define plt_align32pow2\t rte_align32pow2\n #define plt_align32prevpow2 rte_align32prevpow2\n \n", "prefixes": [ "1/2" ] }