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GET /api/patches/108710/?format=api
{ "id": 108710, "url": "https://patches.dpdk.org/api/patches/108710/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220314095916.53574-1-megha.ajmera@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220314095916.53574-1-megha.ajmera@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220314095916.53574-1-megha.ajmera@intel.com", "date": "2022-03-14T09:59:16", "name": "Revert \"sched: enable traffic class oversubscription unconditionally\"", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "79e5ca2cfe11764a4b209e4c6e6f8696803ca3ba", "submitter": { "id": 2494, "url": "https://patches.dpdk.org/api/people/2494/?format=api", "name": "Ajmera, Megha", "email": "megha.ajmera@intel.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220314095916.53574-1-megha.ajmera@intel.com/mbox/", "series": [ { "id": 22139, "url": "https://patches.dpdk.org/api/series/22139/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=22139", "date": "2022-03-14T09:59:16", "name": "Revert \"sched: enable traffic class oversubscription unconditionally\"", "version": 1, "mbox": "https://patches.dpdk.org/series/22139/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/108710/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/108710/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4BF28A00BE;\n\tMon, 14 Mar 2022 10:59:34 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1FEB240DF4;\n\tMon, 14 Mar 2022 10:59:34 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 46D9440DDD\n for <dev@dpdk.org>; Mon, 14 Mar 2022 10:59:32 +0100 (CET)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Mar 2022 02:59:23 -0700", "from silpixa00397515.ir.intel.com (HELO\n silpixa00397515.ger.corp.intel.com) ([10.237.222.51])\n by FMSMGA003.fm.intel.com with ESMTP; 14 Mar 2022 02:59:21 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1647251972; x=1678787972;\n h=from:to:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=UUTHzvgE57bsV2u9u6597nxZqYurufC962LQjQq0Jv0=;\n b=nOOsVRNeVBaj1zs/rm7FYbrezzeNQzSFJDLnOALFedgZ/1EDDvNVaRVo\n BvlrsNOXhcTJJnodmYf1Vaq6V3hnrY8K8aBuQQ/DIa2MWkArdvTMjiUNc\n wMRmgXeyNT9EB7eYYZIy8LcGKigF+CF3Ezkb9YaXER14YOYiniP/HW1Wx\n mU0YrEnhyHq2vlyzeHHDg6sjz32gc4Hh7y+s79u6c55x3E3C6KBPTZd8a\n 0T3oAvy0mmetkj3PSZKe05RgnWkc97OYgpR9ARfOdJdEF5/rLXMba98Bj\n sho2gpDt9FeWCQq1oLPitTpocGHrlS7SNDBdhR1zyS9CKDe0WmUOUWCLZ Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10285\"; a=\"255711864\"", "E=Sophos;i=\"5.90,180,1643702400\"; d=\"scan'208\";a=\"255711864\"", "E=Sophos;i=\"5.90,180,1643702400\"; d=\"scan'208\";a=\"634137422\"" ], "X-ExtLoop1": "1", "From": "Megha Ajmera <megha.ajmera@intel.com>", "To": "dev@dpdk.org, john.mcnamara@intel.com, jasvinder.singh@intel.com,\n cristian.dumitrescu@intel.com, sham.singh.thakur@intel.com", "Subject": "[PATCH] Revert \"sched: enable traffic class oversubscription\n unconditionally\"", "Date": "Mon, 14 Mar 2022 09:59:16 +0000", "Message-Id": "<20220314095916.53574-1-megha.ajmera@intel.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This reverts commit d91c4b1bb5a938734fe8e66da8f965304919f38e.\n\nWhen enabling TC OV unconditionally, it is observed the performance\ndrops by ~20% hence reverting this commit.\n\nSigned-off-by: Megha Ajmera <megha.ajmera@intel.com>\n---\n config/rte_config.h | 1 +\n drivers/net/softnic/rte_eth_softnic_tm.c | 18 +++++\n examples/qos_sched/init.c | 2 +\n lib/sched/rte_sched.c | 90 ++++++++++++++++++++++++\n 4 files changed, 111 insertions(+)", "diff": "diff --git a/config/rte_config.h b/config/rte_config.h\nindex 8eb29c1525..de6fea5b67 100644\n--- a/config/rte_config.h\n+++ b/config/rte_config.h\n@@ -90,6 +90,7 @@\n \n /* rte_sched defines */\n #undef RTE_SCHED_CMAN\n+#undef RTE_SCHED_SUBPORT_TC_OV\n \n /* rte_graph defines */\n #define RTE_GRAPH_BURST_SIZE 256\ndiff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c\nindex 6a7766ba1c..e74092ce7f 100644\n--- a/drivers/net/softnic/rte_eth_softnic_tm.c\n+++ b/drivers/net/softnic/rte_eth_softnic_tm.c\n@@ -595,9 +595,15 @@ static const struct rte_tm_level_capabilities tm_level_cap[] = {\n \t\t\t.sched_sp_n_priorities_max = 1,\n \t\t\t.sched_wfq_n_children_per_group_max = UINT32_MAX,\n \t\t\t.sched_wfq_n_groups_max = 1,\n+#ifdef RTE_SCHED_SUBPORT_TC_OV\n \t\t\t.sched_wfq_weight_max = UINT32_MAX,\n \t\t\t.sched_wfq_packet_mode_supported = 0,\n \t\t\t.sched_wfq_byte_mode_supported = 1,\n+#else\n+\t\t\t.sched_wfq_weight_max = 1,\n+\t\t\t.sched_wfq_packet_mode_supported = 0,\n+\t\t\t.sched_wfq_byte_mode_supported = 1,\n+#endif\n \n \t\t\t.stats_mask = STATS_MASK_DEFAULT,\n \t\t} },\n@@ -2822,6 +2828,8 @@ pmd_tm_hierarchy_commit(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+#ifdef RTE_SCHED_SUBPORT_TC_OV\n+\n static int\n update_pipe_weight(struct rte_eth_dev *dev, struct tm_node *np, uint32_t weight)\n {\n@@ -2859,6 +2867,8 @@ update_pipe_weight(struct rte_eth_dev *dev, struct tm_node *np, uint32_t weight)\n \treturn 0;\n }\n \n+#endif\n+\n static int\n update_queue_weight(struct rte_eth_dev *dev,\n \tstruct tm_node *nq, uint32_t weight)\n@@ -2973,6 +2983,7 @@ pmd_tm_node_parent_update(struct rte_eth_dev *dev,\n \t\t\trte_strerror(EINVAL));\n \t\t/* fall-through */\n \tcase TM_NODE_LEVEL_PIPE:\n+#ifdef RTE_SCHED_SUBPORT_TC_OV\n \t\tif (update_pipe_weight(dev, n, weight))\n \t\t\treturn -rte_tm_error_set(error,\n \t\t\t\tEINVAL,\n@@ -2980,6 +2991,13 @@ pmd_tm_node_parent_update(struct rte_eth_dev *dev,\n \t\t\t\tNULL,\n \t\t\t\trte_strerror(EINVAL));\n \t\treturn 0;\n+#else\n+\t\treturn -rte_tm_error_set(error,\n+\t\t\tEINVAL,\n+\t\t\tRTE_TM_ERROR_TYPE_NODE_WEIGHT,\n+\t\t\tNULL,\n+\t\t\trte_strerror(EINVAL));\n+#endif\n \t\t/* fall-through */\n \tcase TM_NODE_LEVEL_TC:\n \t\treturn -rte_tm_error_set(error,\ndiff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c\nindex 8a0fb8a374..3c1f0bc680 100644\n--- a/examples/qos_sched/init.c\n+++ b/examples/qos_sched/init.c\n@@ -183,7 +183,9 @@ static struct rte_sched_pipe_params pipe_profiles[MAX_SCHED_PIPE_PROFILES] = {\n \t\t.tc_rate = {305175, 305175, 305175, 305175, 305175, 305175,\n \t\t\t305175, 305175, 305175, 305175, 305175, 305175, 305175},\n \t\t.tc_period = 40,\n+#ifdef RTE_SCHED_SUBPORT_TC_OV\n \t\t.tc_ov_weight = 1,\n+#endif\n \n \t\t.wrr_weights = {1, 1, 1, 1},\n \t},\ndiff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c\nindex ec74bee939..7298df9e90 100644\n--- a/lib/sched/rte_sched.c\n+++ b/lib/sched/rte_sched.c\n@@ -1317,12 +1317,14 @@ rte_sched_subport_config(struct rte_sched_port *port,\n \t\tfor (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i++)\n \t\t\ts->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;\n \n+#ifdef RTE_SCHED_SUBPORT_TC_OV\n \t\t/* TC oversubscription */\n \t\ts->tc_ov_wm_min = port->mtu;\n \t\ts->tc_ov_period_id = 0;\n \t\ts->tc_ov = 0;\n \t\ts->tc_ov_n = 0;\n \t\ts->tc_ov_rate = 0;\n+#endif\n \t}\n \n \t{\n@@ -1342,9 +1344,11 @@ rte_sched_subport_config(struct rte_sched_port *port,\n \t\t\telse\n \t\t\t\tprofile->tc_credits_per_period[i] = 0;\n \n+#ifdef RTE_SCHED_SUBPORT_TC_OV\n \t\ts->tc_ov_wm_max = rte_sched_time_ms_to_bytes(profile->tc_period,\n \t\t\t\t\t\t\ts->pipe_tc_be_rate_max);\n \t\ts->tc_ov_wm = s->tc_ov_wm_max;\n+#endif\n \t\ts->profile = subport_profile_id;\n \n \t}\n@@ -2251,6 +2255,50 @@ rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts,\n \treturn result;\n }\n \n+#ifndef RTE_SCHED_SUBPORT_TC_OV\n+\n+static inline void\n+grinder_credits_update(struct rte_sched_port *port,\n+\tstruct rte_sched_subport *subport, uint32_t pos)\n+{\n+\tstruct rte_sched_grinder *grinder = subport->grinder + pos;\n+\tstruct rte_sched_pipe *pipe = grinder->pipe;\n+\tstruct rte_sched_pipe_profile *params = grinder->pipe_params;\n+\tstruct rte_sched_subport_profile *sp = grinder->subport_params;\n+\tuint64_t n_periods;\n+\tuint32_t i;\n+\n+\t/* Subport TB */\n+\tn_periods = (port->time - subport->tb_time) / sp->tb_period;\n+\tsubport->tb_credits += n_periods * sp->tb_credits_per_period;\n+\tsubport->tb_credits = RTE_MIN(subport->tb_credits, sp->tb_size);\n+\tsubport->tb_time += n_periods * sp->tb_period;\n+\n+\t/* Pipe TB */\n+\tn_periods = (port->time - pipe->tb_time) / params->tb_period;\n+\tpipe->tb_credits += n_periods * params->tb_credits_per_period;\n+\tpipe->tb_credits = RTE_MIN(pipe->tb_credits, params->tb_size);\n+\tpipe->tb_time += n_periods * params->tb_period;\n+\n+\t/* Subport TCs */\n+\tif (unlikely(port->time >= subport->tc_time)) {\n+\t\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n+\t\t\tsubport->tc_credits[i] = sp->tc_credits_per_period[i];\n+\n+\t\tsubport->tc_time = port->time + sp->tc_period;\n+\t}\n+\n+\t/* Pipe TCs */\n+\tif (unlikely(port->time >= pipe->tc_time)) {\n+\t\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n+\t\t\tpipe->tc_credits[i] = params->tc_credits_per_period[i];\n+\n+\t\tpipe->tc_time = port->time + params->tc_period;\n+\t}\n+}\n+\n+#else\n+\n static inline uint64_t\n grinder_tc_ov_credits_update(struct rte_sched_port *port,\n \tstruct rte_sched_subport *subport, uint32_t pos)\n@@ -2345,6 +2393,46 @@ grinder_credits_update(struct rte_sched_port *port,\n \t}\n }\n \n+#endif /* RTE_SCHED_TS_CREDITS_UPDATE, RTE_SCHED_SUBPORT_TC_OV */\n+\n+\n+#ifndef RTE_SCHED_SUBPORT_TC_OV\n+\n+static inline int\n+grinder_credits_check(struct rte_sched_port *port,\n+\tstruct rte_sched_subport *subport, uint32_t pos)\n+{\n+\tstruct rte_sched_grinder *grinder = subport->grinder + pos;\n+\tstruct rte_sched_pipe *pipe = grinder->pipe;\n+\tstruct rte_mbuf *pkt = grinder->pkt;\n+\tuint32_t tc_index = grinder->tc_index;\n+\tuint64_t pkt_len = pkt->pkt_len + port->frame_overhead;\n+\tuint64_t subport_tb_credits = subport->tb_credits;\n+\tuint64_t subport_tc_credits = subport->tc_credits[tc_index];\n+\tuint64_t pipe_tb_credits = pipe->tb_credits;\n+\tuint64_t pipe_tc_credits = pipe->tc_credits[tc_index];\n+\tint enough_credits;\n+\n+\t/* Check queue credits */\n+\tenough_credits = (pkt_len <= subport_tb_credits) &&\n+\t\t(pkt_len <= subport_tc_credits) &&\n+\t\t(pkt_len <= pipe_tb_credits) &&\n+\t\t(pkt_len <= pipe_tc_credits);\n+\n+\tif (!enough_credits)\n+\t\treturn 0;\n+\n+\t/* Update port credits */\n+\tsubport->tb_credits -= pkt_len;\n+\tsubport->tc_credits[tc_index] -= pkt_len;\n+\tpipe->tb_credits -= pkt_len;\n+\tpipe->tc_credits[tc_index] -= pkt_len;\n+\n+\treturn 1;\n+}\n+\n+#else\n+\n static inline int\n grinder_credits_check(struct rte_sched_port *port,\n \tstruct rte_sched_subport *subport, uint32_t pos)\n@@ -2391,6 +2479,8 @@ grinder_credits_check(struct rte_sched_port *port,\n \treturn 1;\n }\n \n+#endif /* RTE_SCHED_SUBPORT_TC_OV */\n+\n \n static inline int\n grinder_schedule(struct rte_sched_port *port,\n", "prefixes": [] }