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GET /api/patches/108387/?format=api
{ "id": 108387, "url": "https://patches.dpdk.org/api/patches/108387/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220228045322.1841812-1-psatheesh@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220228045322.1841812-1-psatheesh@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220228045322.1841812-1-psatheesh@marvell.com", "date": "2022-02-28T04:53:21", "name": "[1/2] common/cnxk: support for CPT second pass flow rules", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b4f6c6238cace7782f91b7c854ba58dbd03f7651", "submitter": { "id": 1663, "url": "https://patches.dpdk.org/api/people/1663/?format=api", "name": "Satheesh Paul Antonysamy", "email": "psatheesh@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220228045322.1841812-1-psatheesh@marvell.com/mbox/", "series": [ { "id": 21915, "url": "https://patches.dpdk.org/api/series/21915/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=21915", "date": "2022-02-28T04:53:21", "name": "[1/2] common/cnxk: support for CPT second pass flow rules", "version": 1, "mbox": "https://patches.dpdk.org/series/21915/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/108387/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/108387/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C7A09A0350;\n\tMon, 28 Feb 2022 05:53:39 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A1F994068C;\n\tMon, 28 Feb 2022 05:53:39 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 2CAF94068A\n for <dev@dpdk.org>; Mon, 28 Feb 2022 05:53:38 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 21S24KGJ006742\n for <dev@dpdk.org>; Sun, 27 Feb 2022 20:53:37 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3egn96rf88-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 27 Feb 2022 20:53:37 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sun, 27 Feb 2022 20:53:35 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Sun, 27 Feb 2022 20:53:35 -0800", "from localhost.localdomain (unknown [10.28.34.33])\n by maili.marvell.com (Postfix) with ESMTP id 32DB33F7118;\n Sun, 27 Feb 2022 20:53:32 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=3sTElVhVIObHGbIfhkdFOsIP6+vOCE0Q6MTeKW17gwM=;\n b=YzMibUbKEgnPROcnugHThx/vQdxj/b8CX/mr4ck5jlk3wMb5jLxQxfqUUAK3vbI+76DM\n YLBRklHEn7jUe2rEMkInVO557cmTj4MfNzfYcKNwiIJJSeoXA9uLroMkLNwJYvO+ARx1\n GYVqBXl4G8FVeMR6kDAEoyrscHpUpqGnTZtP8kmI3aT7QgP4bAkydq/0Sl+Ir1fi/ckV\n lowHht9Qwjqlzu7lTH8yz7h+fhhkbBbSmtHTE716ymmvNQrVefJjb/Y4nWovuiONyyCX\n JQQx+pOXXlC8ejIC3XgWo+t1cE8DWHvLhW/HRNZn/hElnI5URdzggxXupSqIE2tATLAe Ag==", "From": "<psatheesh@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Satheesh Paul <psatheesh@marvell.com>", "Subject": "[dpdk-dev] [PATCH 1/2] common/cnxk: support for CPT second pass flow\n rules", "Date": "Mon, 28 Feb 2022 10:23:21 +0530", "Message-ID": "<20220228045322.1841812-1-psatheesh@marvell.com>", "X-Mailer": "git-send-email 2.25.4", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "DLFTM8t3CogieE95EOPfkZTutDgnk700", "X-Proofpoint-ORIG-GUID": "DLFTM8t3CogieE95EOPfkZTutDgnk700", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514\n definitions=2022-02-28_01,2022-02-26_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Satheesh Paul <psatheesh@marvell.com>\n\nAdded support to create flow rules to match packets\nfrom CPT(second pass packets). With this change, ingress\nrules will be created with bits 10 and 11 of channel field\nin the MCAM ignored by default. For rules specific to\nsecond pass packets, the CPT channel bits will be set\nin the MCAM.\n\nSigned-off-by: Satheesh Paul <psatheesh@marvell.com>\n---\n drivers/common/cnxk/hw/nix.h | 7 +++-\n drivers/common/cnxk/roc_npc.c | 9 +++--\n drivers/common/cnxk/roc_npc.h | 1 +\n drivers/common/cnxk/roc_npc_mcam.c | 60 ++++++++++++++++++++---------\n drivers/common/cnxk/roc_npc_parse.c | 14 +++++++\n drivers/common/cnxk/roc_npc_priv.h | 2 +\n 6 files changed, 69 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h\nindex 1cc0c8dfb8..5863e358e0 100644\n--- a/drivers/common/cnxk/hw/nix.h\n+++ b/drivers/common/cnxk/hw/nix.h\n@@ -830,7 +830,7 @@\n #define NIX_CHAN_LBKX_CHX(a, b) \\\n \t(0x000ull | ((uint64_t)(a) << 8) | (uint64_t)(b))\n #define NIX_CHAN_CPT_CH_END (0x4ffull) /* [CN10K, .) */\n-#define NIX_CHAN_CPT_CH_START (0x400ull) /* [CN10K, .) */\n+#define NIX_CHAN_CPT_CH_START (0x800ull) /* [CN10K, .) */\n #define NIX_CHAN_R4\t (0x400ull) /* [CN9K, CN10K) */\n #define NIX_CHAN_R5\t (0x500ull)\n #define NIX_CHAN_R6\t (0x600ull)\n@@ -843,6 +843,11 @@\n #define NIX_CHAN_RPMX_LMACX_CHX(a, b, c) \\\n \t(0x800ull | ((uint64_t)(a) << 8) | ((uint64_t)(b) << 4) | (uint64_t)(c))\n \n+/* The mask is to extract lower 10-bits of channel number\n+ * which CPT will pass to X2P.\n+ */\n+#define NIX_CHAN_CPT_X2P_MASK (0x3ffull)\n+\n #define NIX_INTF_SDP (0x4ull)\n #define NIX_INTF_CGX0 (0x0ull) /* [CN9K, CN10K) */\n #define NIX_INTF_CGX1 (0x1ull) /* [CN9K, CN10K) */\ndiff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c\nindex fc88fd58bc..51e36f141f 100644\n--- a/drivers/common/cnxk/roc_npc.c\n+++ b/drivers/common/cnxk/roc_npc.c\n@@ -570,10 +570,11 @@ npc_parse_pattern(struct npc *npc, const struct roc_npc_item_info pattern[],\n \t\t struct roc_npc_flow *flow, struct npc_parse_state *pst)\n {\n \tnpc_parse_stage_func_t parse_stage_funcs[] = {\n-\t\tnpc_parse_meta_items, npc_parse_pre_l2, npc_parse_cpt_hdr,\n-\t\tnpc_parse_higig2_hdr, npc_parse_la,\tnpc_parse_lb,\n-\t\tnpc_parse_lc,\t npc_parse_ld,\tnpc_parse_le,\n-\t\tnpc_parse_lf,\t npc_parse_lg,\tnpc_parse_lh,\n+\t\tnpc_parse_meta_items, npc_parse_mark_item, npc_parse_pre_l2,\n+\t\tnpc_parse_cpt_hdr, npc_parse_higig2_hdr, npc_parse_la,\n+\t\tnpc_parse_lb,\t npc_parse_lc,\t npc_parse_ld,\n+\t\tnpc_parse_le,\t npc_parse_lf,\t npc_parse_lg,\n+\t\tnpc_parse_lh,\n \t};\n \tuint8_t layer = 0;\n \tint key_offset;\ndiff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h\nindex 6204139396..aecea37b3d 100644\n--- a/drivers/common/cnxk/roc_npc.h\n+++ b/drivers/common/cnxk/roc_npc.h\n@@ -37,6 +37,7 @@ enum roc_npc_item_type {\n \tROC_NPC_ITEM_TYPE_L3_CUSTOM,\n \tROC_NPC_ITEM_TYPE_QINQ,\n \tROC_NPC_ITEM_TYPE_RAW,\n+\tROC_NPC_ITEM_TYPE_MARK,\n \tROC_NPC_ITEM_TYPE_END,\n };\n \ndiff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c\nindex 9c5ff5e60a..3447b59344 100644\n--- a/drivers/common/cnxk/roc_npc_mcam.c\n+++ b/drivers/common/cnxk/roc_npc_mcam.c\n@@ -497,6 +497,38 @@ npc_mcam_fetch_kex_cfg(struct npc *npc)\n \treturn rc;\n }\n \n+static void\n+npc_mcam_set_channel(struct roc_npc_flow *flow,\n+\t\t struct npc_mcam_write_entry_req *req, uint16_t channel,\n+\t\t uint16_t chan_mask, bool is_second_pass)\n+{\n+\tuint16_t chan = 0, mask = 0;\n+\n+\treq->entry_data.kw[0] &= ~(GENMASK(11, 0));\n+\treq->entry_data.kw_mask[0] &= ~(GENMASK(11, 0));\n+\tflow->mcam_data[0] &= ~(GENMASK(11, 0));\n+\tflow->mcam_mask[0] &= ~(GENMASK(11, 0));\n+\n+\tif (is_second_pass) {\n+\t\tchan = (channel | NIX_CHAN_CPT_CH_START);\n+\t\tmask = (chan_mask | NIX_CHAN_CPT_CH_START);\n+\t} else {\n+\t\t/*\n+\t\t * Clear bits 10 & 11 corresponding to CPT\n+\t\t * channel. By default, rules should match\n+\t\t * both first pass packets and second pass\n+\t\t * packets from CPT.\n+\t\t */\n+\t\tchan = (channel & NIX_CHAN_CPT_X2P_MASK);\n+\t\tmask = (chan_mask & NIX_CHAN_CPT_X2P_MASK);\n+\t}\n+\n+\treq->entry_data.kw[0] |= (uint64_t)chan;\n+\treq->entry_data.kw_mask[0] |= (uint64_t)mask;\n+\tflow->mcam_data[0] |= (uint64_t)chan;\n+\tflow->mcam_mask[0] |= (uint64_t)mask;\n+}\n+\n int\n npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow,\n \t\t\t struct npc_parse_state *pst)\n@@ -564,32 +596,22 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow,\n \tif (flow->nix_intf == NIX_INTF_RX) {\n \t\tif (inl_dev && inl_dev->is_multi_channel &&\n \t\t (flow->npc_action & NIX_RX_ACTIONOP_UCAST_IPSEC)) {\n-\t\t\treq->entry_data.kw[0] |= (uint64_t)inl_dev->channel;\n-\t\t\treq->entry_data.kw_mask[0] |=\n-\t\t\t\t(uint64_t)inl_dev->chan_mask;\n \t\t\tpf_func = nix_inl_dev_pffunc_get();\n \t\t\treq->entry_data.action &= ~(GENMASK(19, 4));\n \t\t\treq->entry_data.action |= (uint64_t)pf_func << 4;\n-\n \t\t\tflow->npc_action &= ~(GENMASK(19, 4));\n \t\t\tflow->npc_action |= (uint64_t)pf_func << 4;\n-\t\t\tflow->mcam_data[0] |= (uint64_t)inl_dev->channel;\n-\t\t\tflow->mcam_mask[0] |= (uint64_t)inl_dev->chan_mask;\n+\n+\t\t\tnpc_mcam_set_channel(flow, req, inl_dev->channel,\n+\t\t\t\t\t inl_dev->chan_mask, false);\n \t\t} else if (npc->is_sdp_link) {\n-\t\t\treq->entry_data.kw[0] &= ~(GENMASK(11, 0));\n-\t\t\treq->entry_data.kw_mask[0] &= ~(GENMASK(11, 0));\n-\t\t\treq->entry_data.kw[0] |= (uint64_t)npc->sdp_channel;\n-\t\t\treq->entry_data.kw_mask[0] |=\n-\t\t\t\t(uint64_t)npc->sdp_channel_mask;\n-\t\t\tflow->mcam_data[0] &= ~(GENMASK(11, 0));\n-\t\t\tflow->mcam_mask[0] &= ~(GENMASK(11, 0));\n-\t\t\tflow->mcam_data[0] |= (uint64_t)npc->sdp_channel;\n-\t\t\tflow->mcam_mask[0] |= (uint64_t)npc->sdp_channel_mask;\n+\t\t\tnpc_mcam_set_channel(flow, req, npc->sdp_channel,\n+\t\t\t\t\t npc->sdp_channel_mask,\n+\t\t\t\t\t pst->is_second_pass_rule);\n \t\t} else {\n-\t\t\treq->entry_data.kw[0] |= (uint64_t)npc->channel;\n-\t\t\treq->entry_data.kw_mask[0] |= (BIT_ULL(12) - 1);\n-\t\t\tflow->mcam_data[0] |= (uint64_t)npc->channel;\n-\t\t\tflow->mcam_mask[0] |= (BIT_ULL(12) - 1);\n+\t\t\tnpc_mcam_set_channel(flow, req, npc->channel,\n+\t\t\t\t\t (BIT_ULL(12) - 1),\n+\t\t\t\t\t pst->is_second_pass_rule);\n \t\t}\n \t} else {\n \t\tuint16_t pf_func = (flow->npc_action >> 4) & 0xffff;\ndiff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c\nindex b849326a19..364a846963 100644\n--- a/drivers/common/cnxk/roc_npc_parse.c\n+++ b/drivers/common/cnxk/roc_npc_parse.c\n@@ -21,6 +21,20 @@ npc_parse_meta_items(struct npc_parse_state *pst)\n \treturn 0;\n }\n \n+int\n+npc_parse_mark_item(struct npc_parse_state *pst)\n+{\n+\tif (pst->pattern->type == ROC_NPC_ITEM_TYPE_MARK) {\n+\t\tif (pst->flow->nix_intf != NIX_INTF_RX)\n+\t\t\treturn -EINVAL;\n+\n+\t\tpst->is_second_pass_rule = true;\n+\t\tpst->pattern++;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n npc_flow_raw_item_prepare(const struct roc_npc_flow_item_raw *raw_spec,\n \t\t\t const struct roc_npc_flow_item_raw *raw_mask,\ndiff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h\nindex e78d96e876..78d6ee844d 100644\n--- a/drivers/common/cnxk/roc_npc_priv.h\n+++ b/drivers/common/cnxk/roc_npc_priv.h\n@@ -189,6 +189,7 @@ struct npc_parse_state {\n \t/* adjust ltype in MCAM to match at least one vlan */\n \tbool set_vlan_ltype_mask;\n \tbool set_ipv6ext_ltype_mask;\n+\tbool is_second_pass_rule;\n };\n \n enum npc_kpu_parser_flag {\n@@ -421,6 +422,7 @@ void npc_get_hw_supp_mask(struct npc_parse_state *pst,\n int npc_parse_item_basic(const struct roc_npc_item_info *item,\n \t\t\t struct npc_parse_item_info *info);\n int npc_parse_meta_items(struct npc_parse_state *pst);\n+int npc_parse_mark_item(struct npc_parse_state *pst);\n int npc_parse_pre_l2(struct npc_parse_state *pst);\n int npc_parse_higig2_hdr(struct npc_parse_state *pst);\n int npc_parse_cpt_hdr(struct npc_parse_state *pst);\n", "prefixes": [ "1/2" ] }