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GET /api/patches/108323/?format=api
{ "id": 108323, "url": "https://patches.dpdk.org/api/patches/108323/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220224184039.786663-1-jerinj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220224184039.786663-1-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220224184039.786663-1-jerinj@marvell.com", "date": "2022-02-24T18:40:38", "name": "[v3,1/2] net/cnxk: optimize Rx packet size extraction", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8ae2b7552268fe0790ad4ffb9080791247487320", "submitter": { "id": 1188, "url": "https://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220224184039.786663-1-jerinj@marvell.com/mbox/", "series": [ { "id": 21877, "url": "https://patches.dpdk.org/api/series/21877/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=21877", "date": "2022-02-24T18:40:38", "name": "[v3,1/2] net/cnxk: optimize Rx packet size extraction", "version": 3, "mbox": "https://patches.dpdk.org/series/21877/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/108323/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/108323/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C4EB5A034C;\n\tThu, 24 Feb 2022 19:39:41 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 95D6441143;\n\tThu, 24 Feb 2022 19:39:41 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 0F4F54113D\n for <dev@dpdk.org>; Thu, 24 Feb 2022 19:39:39 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 21OEtQrC008944\n for <dev@dpdk.org>; Thu, 24 Feb 2022 10:39:39 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3edjerra4x-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 24 Feb 2022 10:39:39 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 24 Feb 2022 10:39:37 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 24 Feb 2022 10:39:37 -0800", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n by maili.marvell.com (Postfix) with ESMTP id 9D1365B6934;\n Thu, 24 Feb 2022 10:39:34 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=4JQweQZ6eE3bAnTzaYZCot0LCOP5uwjHgl00gvYFGDc=;\n b=kHKtrjF8xzpHcnekaa0SJmoKi4eDOPmax6cGhm67yBZcMHC9eTqhUZkeQlkaNDBvHHmq\n /6fYR07dXdG6xGVFdSkv43F07/rzUVN/VzLwRedrLOMNAgYKYlc08WTO3DRflTnNeIJr\n O5rSYIBeFJ4TDS0JDgse+Zk1xgPINkqR7Kk2UoQQ3u4T8DxD1gin7tT009VHFcK5ymmG\n sqnJnXrwW94k7MJBylaua+OI1ZNg6AhcRrSGrtglq/cxe0BsLravfJ+AEE89UsOsyuhj\n uBS15oSggvfl6SXMgiNp3Tt6OXj8M7cxZPSMFdce11DKkdC/Mpx79Hk4EM+DLcIsbL+S +A==", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "Pavan Nikhilesh <pbhagavatula@marvell.com>, Jerin Jacob\n <jerinj@marvell.com>", "Subject": "[dpdk-dev] [PATCH v3 1/2] net/cnxk: optimize Rx packet size\n extraction", "Date": "Fri, 25 Feb 2022 00:10:38 +0530", "Message-ID": "<20220224184039.786663-1-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.35.1", "In-Reply-To": "<20220224161013.4566-1-pbhagavatula@marvell.com>", "References": "<20220224161013.4566-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "jrLpjxQvUHygh-7Xf58eSnE5LKGvzcXr", "X-Proofpoint-GUID": "jrLpjxQvUHygh-7Xf58eSnE5LKGvzcXr", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514\n definitions=2022-02-24_04,2022-02-24_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nIn vWQE mode, the mbuf address is calculated without using the\niova list.\n\nPacket length can also be calculated by using NIX_PARSE_S by\nwhich we can completely eliminate reading 2nd cache line\ndepending on the offloads enabled.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nAcked-by: Jerin Jacob <jerinj@marvell.com>\n---\nv3:\n- Change NIX_MBUF_VALIDATE_NEXT macro to inline function\n- Fixed the relevant checkpatch warning at\nhttp://mails.dpdk.org/archives/test-report/2022-February/264235.html\n\nv2 :\n - Reword commit message.\n\n drivers/net/cnxk/cn10k_rx.h | 73 +++++++++++++++++++++++++++----------\n 1 file changed, 53 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h\nindex abf280102b..236a1dca6e 100644\n--- a/drivers/net/cnxk/cn10k_rx.h\n+++ b/drivers/net/cnxk/cn10k_rx.h\n@@ -590,8 +590,8 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t\t\t\t\t*(uint64_t *)args :\n \t\t\t\t\t\t\trxq->mbuf_initializer;\n \tconst uint64x2_t data_off = flags & NIX_RX_VWQE_F ?\n-\t\t\t\t\t\t vdupq_n_u64(0x80ULL) :\n-\t\t\t\t\t\t vdupq_n_u64(rxq->data_off);\n+\t\t\t\t\tvdupq_n_u64(RTE_PKTMBUF_HEADROOM) :\n+\t\t\t\t\tvdupq_n_u64(rxq->data_off);\n \tconst uint32_t qmask = flags & NIX_RX_VWQE_F ? 0 : rxq->qmask;\n \tconst uint64_t wdata = flags & NIX_RX_VWQE_F ? 0 : rxq->wdata;\n \tconst uintptr_t desc = flags & NIX_RX_VWQE_F ? 0 : rxq->desc;\n@@ -687,6 +687,12 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\tcq3_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 3, 64, flags));\n \n \t\tif (!(flags & NIX_RX_VWQE_F)) {\n+\t\t\t/* Get NIX_RX_SG_S for size and buffer pointer */\n+\t\t\tcq0_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 0, 64, flags));\n+\t\t\tcq1_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 1, 64, flags));\n+\t\t\tcq2_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 2, 64, flags));\n+\t\t\tcq3_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 3, 64, flags));\n+\n \t\t\t/* Extract mbuf from NIX_RX_SG_S */\n \t\t\tmbuf01 = vzip2q_u64(cq0_w8, cq1_w8);\n \t\t\tmbuf23 = vzip2q_u64(cq2_w8, cq3_w8);\n@@ -705,21 +711,22 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\tmbuf2 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 0);\n \t\tmbuf3 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 1);\n \n-\t\t/* Mask to get packet len from NIX_RX_SG_S */\n-\t\tconst uint8x16_t shuf_msk = {\n-\t\t\t0xFF, 0xFF, /* pkt_type set as unknown */\n-\t\t\t0xFF, 0xFF, /* pkt_type set as unknown */\n-\t\t\t0, 1, /* octet 1~0, low 16 bits pkt_len */\n-\t\t\t0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */\n-\t\t\t0, 1, /* octet 1~0, 16 bits data_len */\n-\t\t\t0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};\n-\n-\t\t/* Form the rx_descriptor_fields1 with pkt_len and data_len */\n-\t\tf0 = vqtbl1q_u8(cq0_w8, shuf_msk);\n-\t\tf1 = vqtbl1q_u8(cq1_w8, shuf_msk);\n-\t\tf2 = vqtbl1q_u8(cq2_w8, shuf_msk);\n-\t\tf3 = vqtbl1q_u8(cq3_w8, shuf_msk);\n+\t\tif (!(flags & NIX_RX_VWQE_F)) {\n+\t\t\t/* Mask to get packet len from NIX_RX_SG_S */\n+\t\t\tconst uint8x16_t shuf_msk = {\n+\t\t\t\t0xFF, 0xFF, /* pkt_type set as unknown */\n+\t\t\t\t0xFF, 0xFF, /* pkt_type set as unknown */\n+\t\t\t\t0, 1, /* octet 1~0, low 16 bits pkt_len */\n+\t\t\t\t0xFF, 0xFF, /* skip high 16it pkt_len, zero out */\n+\t\t\t\t0, 1, /* octet 1~0, 16 bits data_len */\n+\t\t\t\t0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};\n \n+\t\t\t/* Form the rx_descriptor_fields1 with pkt_len and data_len */\n+\t\t\tf0 = vqtbl1q_u8(cq0_w8, shuf_msk);\n+\t\t\tf1 = vqtbl1q_u8(cq1_w8, shuf_msk);\n+\t\t\tf2 = vqtbl1q_u8(cq2_w8, shuf_msk);\n+\t\t\tf3 = vqtbl1q_u8(cq3_w8, shuf_msk);\n+\t\t}\n \t\tif (flags & NIX_RX_OFFLOAD_SECURITY_F) {\n \t\t\t/* Prefetch probable CPT parse header area */\n \t\t\trte_prefetch_non_temporal(RTE_PTR_ADD(mbuf0, d_off));\n@@ -731,12 +738,42 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t/* Load CQE word0 and word 1 */\n \t\tconst uint64_t cq0_w0 = *CQE_PTR_OFF(cq0, 0, 0, flags);\n \t\tconst uint64_t cq0_w1 = *CQE_PTR_OFF(cq0, 0, 8, flags);\n+\t\tconst uint64_t cq0_w2 = *CQE_PTR_OFF(cq0, 0, 16, flags);\n \t\tconst uint64_t cq1_w0 = *CQE_PTR_OFF(cq0, 1, 0, flags);\n \t\tconst uint64_t cq1_w1 = *CQE_PTR_OFF(cq0, 1, 8, flags);\n+\t\tconst uint64_t cq1_w2 = *CQE_PTR_OFF(cq0, 1, 16, flags);\n \t\tconst uint64_t cq2_w0 = *CQE_PTR_OFF(cq0, 2, 0, flags);\n \t\tconst uint64_t cq2_w1 = *CQE_PTR_OFF(cq0, 2, 8, flags);\n+\t\tconst uint64_t cq2_w2 = *CQE_PTR_OFF(cq0, 2, 16, flags);\n \t\tconst uint64_t cq3_w0 = *CQE_PTR_OFF(cq0, 3, 0, flags);\n \t\tconst uint64_t cq3_w1 = *CQE_PTR_OFF(cq0, 3, 8, flags);\n+\t\tconst uint64_t cq3_w2 = *CQE_PTR_OFF(cq0, 3, 16, flags);\n+\n+\t\tif (flags & NIX_RX_VWQE_F) {\n+\t\t\tuint16_t psize0, psize1, psize2, psize3;\n+\n+\t\t\tpsize0 = (cq0_w2 & 0xFFFF) + 1;\n+\t\t\tpsize1 = (cq1_w2 & 0xFFFF) + 1;\n+\t\t\tpsize2 = (cq2_w2 & 0xFFFF) + 1;\n+\t\t\tpsize3 = (cq3_w2 & 0xFFFF) + 1;\n+\n+\t\t\tf0 = vdupq_n_u64(0);\n+\t\t\tf1 = vdupq_n_u64(0);\n+\t\t\tf2 = vdupq_n_u64(0);\n+\t\t\tf3 = vdupq_n_u64(0);\n+\n+\t\t\tf0 = vsetq_lane_u16(psize0, f0, 2);\n+\t\t\tf0 = vsetq_lane_u16(psize0, f0, 4);\n+\n+\t\t\tf1 = vsetq_lane_u16(psize1, f1, 2);\n+\t\t\tf1 = vsetq_lane_u16(psize1, f1, 4);\n+\n+\t\t\tf2 = vsetq_lane_u16(psize2, f2, 2);\n+\t\t\tf2 = vsetq_lane_u16(psize2, f2, 4);\n+\n+\t\t\tf3 = vsetq_lane_u16(psize3, f3, 2);\n+\t\t\tf3 = vsetq_lane_u16(psize3, f3, 4);\n+\t\t}\n \n \t\tif (flags & NIX_RX_OFFLOAD_RSS_F) {\n \t\t\t/* Fill rss in the rx_descriptor_fields1 */\n@@ -805,10 +842,6 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t}\n \n \t\tif (flags & NIX_RX_OFFLOAD_VLAN_STRIP_F) {\n-\t\t\tuint64_t cq0_w2 = *(uint64_t *)(cq0 + CQE_SZ(0) + 16);\n-\t\t\tuint64_t cq1_w2 = *(uint64_t *)(cq0 + CQE_SZ(1) + 16);\n-\t\t\tuint64_t cq2_w2 = *(uint64_t *)(cq0 + CQE_SZ(2) + 16);\n-\t\t\tuint64_t cq3_w2 = *(uint64_t *)(cq0 + CQE_SZ(3) + 16);\n \n \t\t\tol_flags0 = nix_vlan_update(cq0_w2, ol_flags0, &f0);\n \t\t\tol_flags1 = nix_vlan_update(cq1_w2, ol_flags1, &f1);\n", "prefixes": [ "v3", "1/2" ] }