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GET /api/patches/108053/?format=api
{ "id": 108053, "url": "https://patches.dpdk.org/api/patches/108053/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220222193512.19292-2-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220222193512.19292-2-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220222193512.19292-2-ndabilpuram@marvell.com", "date": "2022-02-22T19:34:53", "name": "[v2,02/21] common/cnxk: realloc inline device XAQ AURA", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "647b381b70a146ccf8f708d937e368b147e29912", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220222193512.19292-2-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 21801, "url": "https://patches.dpdk.org/api/series/21801/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=21801", "date": "2022-02-22T19:34:52", "name": "[v2,01/21] common/cnxk: increase SMQ resource count", "version": 2, "mbox": "https://patches.dpdk.org/series/21801/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/108053/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/108053/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 847A8A034C;\n\tTue, 22 Feb 2022 20:35:31 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E4F2641148;\n\tTue, 22 Feb 2022 20:35:27 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 0A2AC4114B\n for <dev@dpdk.org>; Tue, 22 Feb 2022 20:35:25 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 21MInr2B019941;\n Tue, 22 Feb 2022 11:35:22 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3ecwaxar0u-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 22 Feb 2022 11:35:22 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Feb 2022 11:35:21 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 22 Feb 2022 11:35:20 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id BE66F3F707B;\n Tue, 22 Feb 2022 11:35:18 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=X/Q+vBU7kJHDTVeQVHzpgfMsrVgP3dTRQqlrrMKM1sI=;\n b=QlAEZTEUG0MdXPWGZwhf02e3iLccfflz/irYqHIoqT5fXo5J76NP5cG+8jrTGNTQee2B\n sVbVZvUaogoCipMa5boqwdfsc1vRyd18rQUOfSi/PujTZqY0Sb77rgq26FqIvQxdmFQn\n 5l2Q/UQL6Jp/8eOZ3tYIbE0cK9RI2gzt0YNwWYcoexYS/2SofoOp5ZqS6EwfLkvd72Pf\n K633YuTxCXswwxtRYV4JXeIcrUYV4AEoet3f1meddlJdy39/A4L1BZbOWHtDAujxTl2c\n JCZe6H79/ySJxLVQVP5uw7IyRImWcfFJXDvrCrgwE2X043JPn+Va7msrd7GJ+x4AqFbn rw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v2 02/21] common/cnxk: realloc inline device XAQ AURA", "Date": "Wed, 23 Feb 2022 01:04:53 +0530", "Message-ID": "<20220222193512.19292-2-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220222193512.19292-1-ndabilpuram@marvell.com>", "References": "<20220207072932.22409-1-ndabilpuram@marvell.com>\n <20220222193512.19292-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "vvajzGWtXs-LDSjHtdeemT4QpyJqITqg", "X-Proofpoint-ORIG-GUID": "vvajzGWtXs-LDSjHtdeemT4QpyJqITqg", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2022-02-22_06,2022-02-21_02,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support to realloc inline device XAQ AURA with more\nbuffers of new packet pool AURA.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_nix_inl.h | 1 +\n drivers/common/cnxk/roc_nix_inl_dev.c | 110 +++++++++++++++++++++++++++++-\n drivers/common/cnxk/roc_nix_inl_dev_irq.c | 2 +-\n drivers/common/cnxk/roc_nix_inl_priv.h | 3 +\n drivers/common/cnxk/roc_platform.h | 1 +\n drivers/common/cnxk/version.map | 3 +-\n 6 files changed, 115 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h\nindex abbeac6..bbdcbc8 100644\n--- a/drivers/common/cnxk/roc_nix_inl.h\n+++ b/drivers/common/cnxk/roc_nix_inl.h\n@@ -124,6 +124,7 @@ void __roc_api roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev);\n bool __roc_api roc_nix_inl_dev_is_probed(void);\n void __roc_api roc_nix_inl_dev_lock(void);\n void __roc_api roc_nix_inl_dev_unlock(void);\n+int __roc_api roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle);\n \n /* NIX Inline Inbound API */\n int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix);\ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c\nindex dd93765..1d14f04 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev.c\n@@ -219,7 +219,6 @@ nix_inl_sso_setup(struct nix_inl_dev *inl_dev)\n \tstruct sso_lf_alloc_rsp *sso_rsp;\n \tstruct dev *dev = &inl_dev->dev;\n \tuint16_t hwgrp[1] = {0};\n-\tuint32_t xae_cnt;\n \tint rc;\n \n \t/* Alloc SSOW LF */\n@@ -240,8 +239,8 @@ nix_inl_sso_setup(struct nix_inl_dev *inl_dev)\n \tinl_dev->xae_waes = sso_rsp->xaq_wq_entries;\n \tinl_dev->iue = sso_rsp->in_unit_entries;\n \n-\txae_cnt = inl_dev->iue;\n-\trc = sso_hwgrp_init_xaq_aura(dev, &inl_dev->xaq, xae_cnt,\n+\tinl_dev->nb_xae = inl_dev->iue;\n+\trc = sso_hwgrp_init_xaq_aura(dev, &inl_dev->xaq, inl_dev->nb_xae,\n \t\t\t\t inl_dev->xae_waes, inl_dev->xaq_buf_size,\n \t\t\t\t 1);\n \tif (rc) {\n@@ -518,6 +517,111 @@ nix_inl_lf_detach(struct nix_inl_dev *inl_dev)\n \treturn mbox_process(dev->mbox);\n }\n \n+static int\n+nix_inl_dev_wait_for_sso_empty(struct nix_inl_dev *inl_dev)\n+{\n+\tuintptr_t sso_base = inl_dev->sso_base;\n+\tint wait_ms = 3000;\n+\n+\twhile (wait_ms > 0) {\n+\t\t/* Break when empty */\n+\t\tif (!plt_read64(sso_base + SSO_LF_GGRP_XAQ_CNT) &&\n+\t\t !plt_read64(sso_base + SSO_LF_GGRP_AQ_CNT))\n+\t\t\treturn 0;\n+\n+\t\tplt_delay_us(1000);\n+\t\twait_ms -= 1;\n+\t}\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+int\n+roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n+\tint rc, i;\n+\n+\tif (idev == NULL)\n+\t\treturn 0;\n+\n+\tinl_dev = idev->nix_inl_dev;\n+\t/* Nothing to do if no inline device */\n+\tif (!inl_dev)\n+\t\treturn 0;\n+\n+\tif (!aura_handle) {\n+\t\tinl_dev->nb_xae = inl_dev->iue;\n+\t\tgoto no_pool;\n+\t}\n+\n+\t/* Check if aura is already considered */\n+\tfor (i = 0; i < inl_dev->pkt_pools_cnt; i++) {\n+\t\tif (inl_dev->pkt_pools[i] == aura_handle)\n+\t\t\treturn 0;\n+\t}\n+\n+no_pool:\n+\t/* Disable RQ if enabled */\n+\tif (inl_dev->rq_refs) {\n+\t\trc = nix_rq_ena_dis(&inl_dev->dev, &inl_dev->rq, false);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to disable inline dev RQ, rc=%d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t}\n+\n+\t/* Wait for events to be removed */\n+\trc = nix_inl_dev_wait_for_sso_empty(inl_dev);\n+\tif (rc) {\n+\t\tplt_err(\"Timeout waiting for inline device event cleanup\");\n+\t\tgoto exit;\n+\t}\n+\n+\t/* Disable HWGRP */\n+\tplt_write64(0, inl_dev->sso_base + SSO_LF_GGRP_QCTL);\n+\n+\tinl_dev->pkt_pools_cnt++;\n+\tinl_dev->pkt_pools =\n+\t\tplt_realloc(inl_dev->pkt_pools,\n+\t\t\t sizeof(uint64_t *) * inl_dev->pkt_pools_cnt, 0);\n+\tif (!inl_dev->pkt_pools)\n+\t\tinl_dev->pkt_pools_cnt = 0;\n+\telse\n+\t\tinl_dev->pkt_pools[inl_dev->pkt_pools_cnt - 1] = aura_handle;\n+\tinl_dev->nb_xae += roc_npa_aura_op_limit_get(aura_handle);\n+\n+\t/* Realloc XAQ aura */\n+\trc = sso_hwgrp_init_xaq_aura(&inl_dev->dev, &inl_dev->xaq,\n+\t\t\t\t inl_dev->nb_xae, inl_dev->xae_waes,\n+\t\t\t\t inl_dev->xaq_buf_size, 1);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to reinitialize xaq aura, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\t/* Setup xaq for hwgrps */\n+\trc = sso_hwgrp_alloc_xaq(&inl_dev->dev, inl_dev->xaq.aura_handle, 1);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to setup hwgrp xaq aura, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\t/* Enable HWGRP */\n+\tplt_write64(0x1, inl_dev->sso_base + SSO_LF_GGRP_QCTL);\n+\n+exit:\n+\t/* Renable RQ */\n+\tif (inl_dev->rq_refs) {\n+\t\trc = nix_rq_ena_dis(&inl_dev->dev, &inl_dev->rq, true);\n+\t\tif (rc)\n+\t\t\tplt_err(\"Failed to enable inline dev RQ, rc=%d\", rc);\n+\t}\n+\n+\treturn rc;\n+}\n+\n int\n roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)\n {\ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c\nindex 848523b..d758e0c 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev_irq.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c\n@@ -72,7 +72,7 @@ nix_inl_sso_hwgrp_irq(void *param)\n \tif (intr & BIT(1))\n \t\tnix_inl_sso_work_cb(inl_dev);\n \n-\tif (!(intr & BIT(1)))\n+\tif (intr & ~BIT(1))\n \t\tplt_err(\"GGRP 0 GGRP_INT=0x%\" PRIx64 \"\", intr);\n \n \t/* Clear interrupt */\ndiff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h\nindex 2cdab6dc..17df23f 100644\n--- a/drivers/common/cnxk/roc_nix_inl_priv.h\n+++ b/drivers/common/cnxk/roc_nix_inl_priv.h\n@@ -27,9 +27,12 @@ struct nix_inl_dev {\n \tuint32_t xaq_buf_size;\n \tuint32_t xae_waes;\n \tuint32_t iue;\n+\tuint32_t nb_xae;\n \tstruct roc_sso_xaq_data xaq;\n \troc_nix_inl_sso_work_cb_t work_cb;\n \tvoid *cb_args;\n+\tuint64_t *pkt_pools;\n+\tuint16_t pkt_pools_cnt;\n \n \t/* NIX data */\n \tuint8_t lf_tx_stats;\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex adfb88c..3b10bfb 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -148,6 +148,7 @@\n #define plt_intr_handle rte_intr_handle\n \n #define plt_zmalloc(sz, align) rte_zmalloc(\"cnxk\", sz, align)\n+#define plt_realloc\t rte_realloc\n #define plt_free\t rte_free\n \n #define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr))\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 75a260f..ff3c1e8 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -133,11 +133,12 @@ INTERNAL {\n \troc_nix_inl_dev_init;\n \troc_nix_inl_dev_is_probed;\n \troc_nix_inl_dev_lock;\n-\troc_nix_inl_dev_unlock;\n \troc_nix_inl_dev_rq;\n \troc_nix_inl_dev_rq_get;\n \troc_nix_inl_dev_rq_put;\n \troc_nix_inl_dev_rq_limit_get;\n+\troc_nix_inl_dev_unlock;\n+\troc_nix_inl_dev_xaq_realloc;\n \troc_nix_inl_inb_is_enabled;\n \troc_nix_inl_inb_init;\n \troc_nix_inl_inb_sa_base_get;\n", "prefixes": [ "v2", "02/21" ] }