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GET /api/patches/107434/?format=api
{ "id": 107434, "url": "https://patches.dpdk.org/api/patches/107434/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220214093511.1592698-14-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220214093511.1592698-14-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220214093511.1592698-14-michaelba@nvidia.com", "date": "2022-02-14T09:35:04", "name": "[v2,13/20] net/mlx5: add E-switch mode flag", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b346c4455ad47ea86b43ea87ffde3eb25f0efc79", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220214093511.1592698-14-michaelba@nvidia.com/mbox/", "series": [ { "id": 21654, "url": "https://patches.dpdk.org/api/series/21654/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=21654", "date": "2022-02-14T09:34:52", "name": "mlx5: refactor devargs management", "version": 2, "mbox": "https://patches.dpdk.org/series/21654/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/107434/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/107434/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A983AA00C4;\n\tMon, 14 Feb 2022 10:36:51 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 59C124120A;\n\tMon, 14 Feb 2022 10:35:53 +0100 (CET)", "from NAM02-BN1-obe.outbound.protection.outlook.com\n (mail-bn1nam07on2086.outbound.protection.outlook.com [40.107.212.86])\n by mails.dpdk.org (Postfix) with ESMTP id 444A44118F\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Subject": "[PATCH v2 13/20] net/mlx5: add E-switch mode flag", "Date": "Mon, 14 Feb 2022 11:35:04 +0200", "Message-ID": "<20220214093511.1592698-14-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220214093511.1592698-1-michaelba@nvidia.com>", "References": "<20220127153950.812953-1-michaelba@nvidia.com>\n <20220214093511.1592698-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "2109bf3f-ce89-4706-c179-08d9ef9d633b", "X-MS-TrafficTypeDiagnostic": "DM4PR12MB5913:EE_", "X-Microsoft-Antispam-PRVS": "\n <DM4PR12MB5913A648E1053296A83D8280CC339@DM4PR12MB5913.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:6108;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n MRuf5eFk4FvLFsAMRfhOIURw57hRbL/q7iK+c12gtmt9pF79ydYPfVGXEFTV4gju47WX+azOhrNPvWbVauXNNEe3kG02u5BFJBuByJSn13IjJkoXLPyvWXBP/ORP9Nl0Cm2zbg5WpLVtD2/ZhgCiWSIS97PHOICbHPqYGjZbeS89AerpzCPhotthPU/OVLz/LjMxbxNEc3y6aEFeCTFvGSPCsjxM+IY5FBu0nawfRkElkfl/wagRv1zxFYbP8Oz5p68HUnx6/GtEt0lFb95SBg9gzMyXyKBjS0nV7Blwf8lyyFzp0sqWw6mTsdhy5WzU4K9zbLvWAQrImEVJ3PPKa6RdM5FIWl726UIvQaeVzEy0Tg2pQxF8dfwQaJ5V3YNfTwcrIM5jwJ4c8uzDtrr8befN5/nz9SossXa2VpM4fcVZqDqeq2HlwiDGWWQxhxTpJjcfKzDPmrt0YfYqcZG0cVxu2KBPGKv/hVTqu1efPY6boqh+ZkvK6e/wY/AwKsJmDBmr37SgjhDXrhZC8hgS/+BGGg8FJzmV9C96KjA5iYkWUhEzO4HfZmc2Sj3scS2qGT9Lupxr9XLxvMLqd911yo3/63h9p1QCzjjOU0WhYhFl6E1lwi5b7FRyG7LD8FXO2ZTog6ruU2DHhWuJwIc9q3NDfJz4eTtpiaW806l9a/PLijLyFYjglqB5983nhqEpTR0oK57+2SGAZJ+o6TqGEA==", "X-Forefront-Antispam-Report": "CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(508600001)(2906002)(7696005)(6666004)(5660300002)(47076005)(70586007)(81166007)(316002)(6286002)(40460700003)(54906003)(426003)(86362001)(55016003)(36860700001)(107886003)(36756003)(8676002)(8936002)(83380400001)(4326008)(6916009)(1076003)(186003)(356005)(336012)(70206006)(2616005)(26005)(82310400004)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "14 Feb 2022 09:35:50.2462 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2109bf3f-ce89-4706-c179-08d9ef9d633b", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT032.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB5913", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds in SH structure a flag which indicates whether is\nE-Switch mode.\nWhen configure \"dv_esw_en\" from devargs, it is enabled only when is\nE-switch mode. So, since dv_esw_en has been configure, it is enough to\ncheck if \"dv_esw_en\" is valid.\nThis patch also removes E-Switch mode check when \"dv_esw_en\" is checked\ntoo.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 14 +++++---------\n drivers/net/mlx5/mlx5.c | 1 +\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_ethdev.c | 4 ++--\n drivers/net/mlx5/mlx5_flow_dv.c | 12 +++---------\n drivers/net/mlx5/mlx5_trigger.c | 5 ++---\n 6 files changed, 14 insertions(+), 23 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 1ff2b8dc22..69ba2aaf88 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -951,10 +951,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tif (!sh)\n \t\treturn NULL;\n \t/* Update final values for devargs before check sibling config. */\n-\tif (config->dv_miss_info) {\n-\t\tif (switch_info->master || switch_info->representor)\n-\t\t\tconfig->dv_xmeta_en = MLX5_XMETA_MODE_META16;\n-\t}\n #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)\n \tif (config->dv_flow_en) {\n \t\tDRV_LOG(WARNING, \"DV flow is not supported.\");\n@@ -962,12 +958,13 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t}\n #endif\n #ifdef HAVE_MLX5DV_DR_ESWITCH\n-\tif (!(hca_attr->eswitch_manager && config->dv_flow_en &&\n-\t (switch_info->representor || switch_info->master)))\n+\tif (!(hca_attr->eswitch_manager && config->dv_flow_en && sh->esw_mode))\n \t\tconfig->dv_esw_en = 0;\n #else\n \tconfig->dv_esw_en = 0;\n #endif\n+\tif (config->dv_miss_info && config->dv_esw_en)\n+\t\tconfig->dv_xmeta_en = MLX5_XMETA_MODE_META16;\n \tif (!config->dv_esw_en &&\n \t config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {\n \t\tDRV_LOG(WARNING,\n@@ -1133,7 +1130,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t * register to match on vport index. The engaged part of metadata\n \t * register is defined by mask.\n \t */\n-\tif (switch_info->representor || switch_info->master) {\n+\tif (sh->esw_mode) {\n \t\terr = mlx5_glue->devx_port_query(sh->cdev->ctx,\n \t\t\t\t\t\t spawn->phys_port,\n \t\t\t\t\t\t &vport_info);\n@@ -1164,8 +1161,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t}\n \tif (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) {\n \t\tpriv->vport_id = vport_info.vport_id;\n-\t} else if (spawn->pf_bond >= 0 &&\n-\t\t (switch_info->representor || switch_info->master)) {\n+\t} else if (spawn->pf_bond >= 0 && sh->esw_mode) {\n \t\tDRV_LOG(ERR,\n \t\t\t\"Cannot deduce vport index for port %d on bonding device %s\",\n \t\t\tspawn->phys_port, spawn->phys_dev_name);\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 531916f3a5..b26632d249 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1259,6 +1259,7 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \tpthread_mutex_init(&sh->txpp.mutex, NULL);\n \tsh->numa_node = spawn->cdev->dev->numa_node;\n \tsh->cdev = spawn->cdev;\n+\tsh->esw_mode = !!(spawn->info.master || spawn->info.representor);\n \tif (spawn->bond_info)\n \t\tsh->bond = *spawn->bond_info;\n \terr = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex d69b6a357b..a713e61572 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1146,6 +1146,7 @@ struct mlx5_flex_item {\n struct mlx5_dev_ctx_shared {\n \tLIST_ENTRY(mlx5_dev_ctx_shared) next;\n \tuint32_t refcnt;\n+\tuint32_t esw_mode:1; /* Whether is E-Switch mode. */\n \tuint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */\n \tuint32_t steering_format_version:4;\n \t/* Indicates the device steering logic format. */\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex 801c467bba..06d5acb75f 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -672,7 +672,7 @@ mlx5_port_to_eswitch_info(uint16_t port, bool valid)\n \t}\n \tdev = &rte_eth_devices[port];\n \tpriv = dev->data->dev_private;\n-\tif (!(priv->representor || priv->master)) {\n+\tif (!priv->sh->esw_mode) {\n \t\trte_errno = EINVAL;\n \t\treturn NULL;\n \t}\n@@ -699,7 +699,7 @@ mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev)\n \tstruct mlx5_priv *priv;\n \n \tpriv = dev->data->dev_private;\n-\tif (!(priv->representor || priv->master)) {\n+\tif (!priv->sh->esw_mode) {\n \t\trte_errno = EINVAL;\n \t\treturn NULL;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 4e60a54df3..6a5ac01c2a 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -6600,11 +6600,6 @@ flow_dv_validate_attributes(struct rte_eth_dev *dev,\n \t\t\t\t(error, ENOTSUP,\n \t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n \t\t\t\t \"E-Switch dr is not supported\");\n-\t\tif (!(priv->representor || priv->master))\n-\t\t\treturn rte_flow_error_set\n-\t\t\t\t(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t\t NULL, \"E-Switch configuration can only be\"\n-\t\t\t\t \" done by a master or a representor device\");\n \t\tif (attributes->egress)\n \t\t\treturn rte_flow_error_set\n \t\t\t\t(error, ENOTSUP,\n@@ -13612,8 +13607,7 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t * E-Switch rule where no port_id item was found. In both cases\n \t * the source port is set according the current port in use.\n \t */\n-\tif (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&\n-\t (priv->representor || priv->master)) {\n+\tif (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) && priv->sh->esw_mode) {\n \t\tif (flow_dv_translate_item_port_id(dev, match_mask,\n \t\t\t\t\t\t match_value, NULL, attr))\n \t\t\treturn -rte_errno;\n@@ -16173,7 +16167,7 @@ __flow_dv_create_policy_flow(struct rte_eth_dev *dev,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tuint8_t misc_mask;\n \n-\tif (match_src_port && (priv->representor || priv->master)) {\n+\tif (match_src_port && priv->sh->esw_mode) {\n \t\tif (flow_dv_translate_item_port_id(dev, matcher.buf,\n \t\t\t\t\t\t value.buf, item, attr)) {\n \t\t\tDRV_LOG(ERR, \"Failed to create meter policy%d flow's\"\n@@ -16225,7 +16219,7 @@ __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tconst uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;\n \n-\tif (match_src_port && (priv->representor || priv->master)) {\n+\tif (match_src_port && priv->sh->esw_mode) {\n \t\tif (flow_dv_translate_item_port_id(dev, matcher.mask.buf,\n \t\t\t\t\t\t value.buf, item, attr)) {\n \t\t\tDRV_LOG(ERR, \"Failed to register meter policy%d matcher\"\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 7aefc93350..a00b56eecf 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -1330,8 +1330,7 @@ mlx5_traffic_enable(struct rte_eth_dev *dev)\n \t\t\t\tgoto error;\n \t\t\t}\n \t\t}\n-\t\tif ((priv->representor || priv->master) &&\n-\t\t priv->config.dv_esw_en) {\n+\t\tif (priv->config.dv_esw_en) {\n \t\t\tif (mlx5_flow_create_devx_sq_miss_flow(dev, i) == 0) {\n \t\t\t\tDRV_LOG(ERR,\n \t\t\t\t\t\"Port %u Tx queue %u SQ create representor devx default miss rule failed.\",\n@@ -1341,7 +1340,7 @@ mlx5_traffic_enable(struct rte_eth_dev *dev)\n \t\t}\n \t\tmlx5_txq_release(dev, i);\n \t}\n-\tif ((priv->master || priv->representor) && priv->config.dv_esw_en) {\n+\tif (priv->config.dv_esw_en) {\n \t\tif (mlx5_flow_create_esw_table_zero_flow(dev))\n \t\t\tpriv->fdb_def_rule = 1;\n \t\telse\n", "prefixes": [ "v2", "13/20" ] }