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GET /api/patches/107297/?format=api
{ "id": 107297, "url": "https://patches.dpdk.org/api/patches/107297/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220210162926.20436-14-suanmingm@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220210162926.20436-14-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220210162926.20436-14-suanmingm@nvidia.com", "date": "2022-02-10T16:29:26", "name": "[13/13] net/mlx5: add header reformat action", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3a6a21b64fa74163daabf9790787b54aebdf82a9", "submitter": { "id": 1887, "url": "https://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220210162926.20436-14-suanmingm@nvidia.com/mbox/", "series": [ { "id": 21609, "url": "https://patches.dpdk.org/api/series/21609/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=21609", "date": "2022-02-10T16:29:13", "name": "net/mlx5: add hardware steering", "version": 1, "mbox": "https://patches.dpdk.org/series/21609/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/107297/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/107297/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 879A0A00BE;\n\tThu, 10 Feb 2022 17:31:43 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 12A1741159;\n\tThu, 10 Feb 2022 17:31:13 +0100 (CET)", "from NAM04-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam08on2055.outbound.protection.outlook.com [40.107.100.55])\n by mails.dpdk.org (Postfix) with ESMTP id 2718A41141\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Subject": "[PATCH 13/13] net/mlx5: add header reformat action", "Date": "Thu, 10 Feb 2022 18:29:26 +0200", "Message-ID": "<20220210162926.20436-14-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220210162926.20436-1-suanmingm@nvidia.com>", "References": "<20220210162926.20436-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "f998bc1f-4991-4e66-068c-08d9ecb2bedb", "X-MS-TrafficTypeDiagnostic": "DM5PR12MB1737:EE_", "X-Microsoft-Antispam-PRVS": "\n <DM5PR12MB17371A79A554E4ED6137FC88C12F9@DM5PR12MB1737.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:9508;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n hEoovUpLknpmrzwyqhN2t/WENl5RXZWS9dGo664lBWGXdb9lQIzANozNvOv4itx1X6tAVi1qkUtExwumm/zuEvbDmKvROPGt/TPAE5OQIQvMqbuU9mL6cArH3dB+WXJhuDLxI17wWR8HeVauxrsLi1T6elONIL9wtFRjvxXnQ6w824zM5h6kD1mYsYw5MLUkVFp99r+BrdyMerkSVkj/AVIKsgMMnO3+uDY8gKQ1iFbv8k/Vn13SCOkgd/SxoG35fqcivXwX4bbinhRVBa1ScqoxhV0HVWD3dxTET2DzbQm4BHBReXVz9NWYyUWx2pZtvsOVcugj8JIV+IbmSRNFiAANBSqqwhRct+BsfFvO1RA63uy7owiZWxQBEU3CQ+6Jsuv6cDNh363vXaSEPuPmvp4qMyESHjAAfoQNyB4uHDi0rS5M2MTTnhRB2SikpBIpvueQHfdLF9UDGUXSEwvsv56F/ilHVyHTGMx9ECIlWWGOgGPGjPUMOPnRElF7v9eb2frWhBFWEJLQkN68QiIDybWazDDk2Y5mlAYUmxQ+4tH5i/VY4c7Hfjq13JAe0MGVm2TrwCg3nMCqgtmUJxGBQ3LNWTl1pUem4ANcDGyyKTd4Gnze3FDiOtaJCAysCwgWE6+kbCxyt7XFL8whIRkeLX53O3MBQDLaTT3sHnY5OGCQ7M8iLNwH8YQcVpY2LJT4lVxag3QyVG9TrVBX1Jhr28IE579B/qkvaARtls7YORlYOs5S3AFA8HUOGIsmAsVTGBNOaefc4kpMbYM92y6JWQ==", "X-Forefront-Antispam-Report": "CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(40460700003)(2906002)(36860700001)(47076005)(4326008)(81166007)(6666004)(356005)(55016003)(36756003)(70206006)(70586007)(8676002)(86362001)(6636002)(316002)(30864003)(110136005)(54906003)(83380400001)(5660300002)(508600001)(26005)(186003)(6286002)(426003)(16526019)(336012)(2616005)(7696005)(8936002)(1076003)(82310400004)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "10 Feb 2022 16:31:09.8588 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f998bc1f-4991-4e66-068c-08d9ecb2bedb", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT008.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR12MB1737", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "HW steering header reformat action can work under bulk mode. In\nthis case, when create the table, bulk size of header reformat\nactions will be allocated in low level. Afterwards, when create\nflow, just simply specify the action index in the bulk and the\nencapsulation data to the action will be enough.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_flow.h | 21 +++\n drivers/net/mlx5/mlx5_flow_dv.c | 4 +-\n drivers/net/mlx5/mlx5_flow_hw.c | 228 +++++++++++++++++++++++++++++++-\n 4 files changed, 251 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex c78dc3c431..e10f55bf8c 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -344,6 +344,7 @@ struct mlx5_hw_q_job {\n \tuint32_t type; /* Job type. */\n \tstruct rte_flow_hw *flow; /* Flow attached to the job. */\n \tvoid *user_data; /* Job user data. */\n+\tuint8_t *encap_data; /* Encap data. */\n };\n \n /* HW steering job descriptor LIFO header . */\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 097e5bf587..16fb6e643b 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1038,6 +1038,14 @@ struct mlx5_action_construct_data {\n \tuint16_t action_src; /* rte_flow_action src offset. */\n \tuint16_t action_dst; /* mlx5dr_rule_action dst offset. */\n \tunion {\n+\t\tstruct {\n+\t\t\t/* encap src(item) offset. */\n+\t\t\tuint16_t src;\n+\t\t\t/* encap dst data offset. */\n+\t\t\tuint16_t dst;\n+\t\t\t/* encap data len. */\n+\t\t\tuint16_t len;\n+\t\t} encap;\n \t\tstruct {\n \t\t\tuint64_t types; /* RSS hash types. */\n \t\t\tuint32_t level; /* RSS level. */\n@@ -1079,6 +1087,13 @@ struct mlx5_hw_jump_action {\n \tstruct mlx5dr_action *hws_action;\n };\n \n+/* Encap decap action struct. */\n+struct mlx5_hw_encap_decap_action {\n+\tstruct mlx5dr_action *action; /* Action object. */\n+\tsize_t data_size; /* Action metadata size. */\n+\tuint8_t data[]; /* Action data. */\n+};\n+\n /* The maximum actions support in the flow. */\n #define MLX5_HW_MAX_ACTS 16\n \n@@ -1088,6 +1103,9 @@ struct mlx5_hw_actions {\n \tLIST_HEAD(act_list, mlx5_action_construct_data) act_list;\n \tstruct mlx5_hw_jump_action *jump; /* Jump action. */\n \tstruct mlx5_hrxq *tir; /* TIR action. */\n+\t/* Encap/Decap action. */\n+\tstruct mlx5_hw_encap_decap_action *encap_decap;\n+\tuint16_t encap_decap_pos; /* Encap/Decap action position. */\n \tuint32_t acts_num:4; /* Total action number. */\n \tuint32_t mark:1; /* Indicate the mark action. */\n \t/* Translated DR action array from action template. */\n@@ -2021,4 +2039,7 @@ int flow_dv_action_query(struct rte_eth_dev *dev,\n \t\t\t const struct rte_flow_action_handle *handle,\n \t\t\t void *data,\n \t\t\t struct rte_flow_error *error);\n+size_t flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type);\n+int flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,\n+\t\t\t size_t *size, struct rte_flow_error *error);\n #endif /* RTE_PMD_MLX5_FLOW_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex ca8ae4214b..377ed6c1db 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -4024,7 +4024,7 @@ flow_dv_push_vlan_action_resource_register\n * @return\n * sizeof struct item_type, 0 if void or irrelevant.\n */\n-static size_t\n+size_t\n flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)\n {\n \tsize_t retval;\n@@ -4090,7 +4090,7 @@ flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)\n * @return\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-static int\n+int\n flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,\n \t\t\t size_t *size, struct rte_flow_error *error)\n {\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 9fc6f24542..5a652ac8e6 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -345,6 +345,50 @@ __flow_hw_act_data_general_append(struct mlx5_priv *priv,\n \treturn 0;\n }\n \n+/**\n+ * Append dynamic encap action to the dynamic action list.\n+ *\n+ * @param[in] priv\n+ * Pointer to the port private data structure.\n+ * @param[in] acts\n+ * Pointer to the template HW steering DR actions.\n+ * @param[in] type\n+ * Action type.\n+ * @param[in] action_src\n+ * Offset of source rte flow action.\n+ * @param[in] action_dst\n+ * Offset of destination DR action.\n+ * @param[in] encap_src\n+ * Offset of source encap raw data.\n+ * @param[in] encap_dst\n+ * Offset of destination encap raw data.\n+ * @param[in] len\n+ * Length of the data to be updated.\n+ *\n+ * @return\n+ * 0 on success, negative value otherwise and rte_errno is set.\n+ */\n+static __rte_always_inline int\n+__flow_hw_act_data_encap_append(struct mlx5_priv *priv,\n+\t\t\t\tstruct mlx5_hw_actions *acts,\n+\t\t\t\tenum rte_flow_action_type type,\n+\t\t\t\tuint16_t action_src,\n+\t\t\t\tuint16_t action_dst,\n+\t\t\t\tuint16_t encap_src,\n+\t\t\t\tuint16_t encap_dst,\n+\t\t\t\tuint16_t len)\n+{\tstruct mlx5_action_construct_data *act_data;\n+\n+\tact_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);\n+\tif (!act_data)\n+\t\treturn -1;\n+\tact_data->encap.src = encap_src;\n+\tact_data->encap.dst = encap_dst;\n+\tact_data->encap.len = len;\n+\tLIST_INSERT_HEAD(&acts->act_list, act_data, next);\n+\treturn 0;\n+}\n+\n /**\n * Append shared RSS action to the dynamic action list.\n *\n@@ -435,6 +479,53 @@ flow_hw_shared_action_translate(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+/**\n+ * Translate encap items to encapsulation list.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev data structure.\n+ * @param[in] acts\n+ * Pointer to the template HW steering DR actions.\n+ * @param[in] type\n+ * Action type.\n+ * @param[in] action_src\n+ * Offset of source rte flow action.\n+ * @param[in] action_dst\n+ * Offset of destination DR action.\n+ * @param[in] items\n+ * Encap item pattern.\n+ * @param[in] items_m\n+ * Encap item mask indicates which part are constant and dynamic.\n+ *\n+ * @return\n+ * 0 on success, negative value otherwise and rte_errno is set.\n+ */\n+static __rte_always_inline int\n+flow_hw_encap_item_translate(struct rte_eth_dev *dev,\n+\t\t\t struct mlx5_hw_actions *acts,\n+\t\t\t enum rte_flow_action_type type,\n+\t\t\t uint16_t action_src,\n+\t\t\t uint16_t action_dst,\n+\t\t\t const struct rte_flow_item *items,\n+\t\t\t const struct rte_flow_item *items_m)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tsize_t len, total_len = 0;\n+\tuint32_t i = 0;\n+\n+\tfor (; items->type != RTE_FLOW_ITEM_TYPE_END; items++, items_m++, i++) {\n+\t\tlen = flow_dv_get_item_hdr_len(items->type);\n+\t\tif ((!items_m->spec ||\n+\t\t memcmp(items_m->spec, items->spec, len)) &&\n+\t\t __flow_hw_act_data_encap_append(priv, acts, type,\n+\t\t\t\t\t\t action_src, action_dst, i,\n+\t\t\t\t\t\t total_len, len))\n+\t\t\treturn -1;\n+\t\ttotal_len += len;\n+\t}\n+\treturn 0;\n+}\n+\n /**\n * Translate rte_flow actions to DR action.\n *\n@@ -472,6 +563,12 @@ flow_hw_actions_translate(struct rte_eth_dev *dev,\n \tstruct rte_flow_action *actions = at->actions;\n \tstruct rte_flow_action *action_start = actions;\n \tstruct rte_flow_action *masks = at->masks;\n+\tenum mlx5dr_action_reformat_type refmt_type = 0;\n+\tconst struct rte_flow_action_raw_encap *raw_encap_data;\n+\tconst struct rte_flow_item *enc_item = NULL, *enc_item_m = NULL;\n+\tuint16_t reformat_pos = MLX5_HW_MAX_ACTS, reformat_src = 0;\n+\tuint8_t *encap_data = NULL;\n+\tsize_t data_size = 0;\n \tbool actions_end = false;\n \tuint32_t type, i;\n \tint err;\n@@ -573,6 +670,56 @@ flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\t}\n \t\t\ti++;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:\n+\t\t\tMLX5_ASSERT(reformat_pos == MLX5_HW_MAX_ACTS);\n+\t\t\tenc_item = ((const struct rte_flow_action_vxlan_encap *)\n+\t\t\t\t actions->conf)->definition;\n+\t\t\tenc_item_m =\n+\t\t\t\t((const struct rte_flow_action_vxlan_encap *)\n+\t\t\t\t masks->conf)->definition;\n+\t\t\treformat_pos = i++;\n+\t\t\treformat_src = actions - action_start;\n+\t\t\trefmt_type = MLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L2;\n+\t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:\n+\t\t\tMLX5_ASSERT(reformat_pos == MLX5_HW_MAX_ACTS);\n+\t\t\tenc_item = ((const struct rte_flow_action_nvgre_encap *)\n+\t\t\t\t actions->conf)->definition;\n+\t\t\tenc_item_m =\n+\t\t\t\t((const struct rte_flow_action_nvgre_encap *)\n+\t\t\t\tactions->conf)->definition;\n+\t\t\treformat_pos = i++;\n+\t\t\treformat_src = actions - action_start;\n+\t\t\trefmt_type = MLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L2;\n+\t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:\n+\t\tcase RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:\n+\t\t\tMLX5_ASSERT(reformat_pos == MLX5_HW_MAX_ACTS);\n+\t\t\treformat_pos = i++;\n+\t\t\trefmt_type = MLX5DR_ACTION_REFORMAT_TYPE_TNL_L2_TO_L2;\n+\t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_RAW_ENCAP:\n+\t\t\traw_encap_data =\n+\t\t\t\t(const struct rte_flow_action_raw_encap *)\n+\t\t\t\t actions->conf;\n+\t\t\tencap_data = raw_encap_data->data;\n+\t\t\tdata_size = raw_encap_data->size;\n+\t\t\tif (reformat_pos != MLX5_HW_MAX_ACTS) {\n+\t\t\t\trefmt_type = data_size <\n+\t\t\t\tMLX5_ENCAPSULATION_DECISION_SIZE ?\n+\t\t\t\tMLX5DR_ACTION_REFORMAT_TYPE_TNL_L3_TO_L2 :\n+\t\t\t\tMLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L3;\n+\t\t\t} else {\n+\t\t\t\treformat_pos = i++;\n+\t\t\t\trefmt_type =\n+\t\t\t\tMLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L2;\n+\t\t\t}\n+\t\t\treformat_src = actions - action_start;\n+\t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_RAW_DECAP:\n+\t\t\treformat_pos = i++;\n+\t\t\trefmt_type = MLX5DR_ACTION_REFORMAT_TYPE_TNL_L2_TO_L2;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_END:\n \t\t\tactions_end = true;\n \t\t\tbreak;\n@@ -580,6 +727,45 @@ flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\tbreak;\n \t\t}\n \t}\n+\tif (reformat_pos != MLX5_HW_MAX_ACTS) {\n+\t\tuint8_t buf[MLX5_ENCAP_MAX_LEN];\n+\n+\t\tif (enc_item) {\n+\t\t\tMLX5_ASSERT(!encap_data);\n+\t\t\tif (flow_dv_convert_encap_data\n+\t\t\t\t(enc_item, buf, &data_size, error) ||\n+\t\t\t flow_hw_encap_item_translate\n+\t\t\t\t(dev, acts, (action_start + reformat_src)->type,\n+\t\t\t\t reformat_src, reformat_pos,\n+\t\t\t\t enc_item, enc_item_m))\n+\t\t\t\tgoto err;\n+\t\t\tencap_data = buf;\n+\t\t} else if (encap_data && __flow_hw_act_data_encap_append\n+\t\t\t\t(priv, acts,\n+\t\t\t\t (action_start + reformat_src)->type,\n+\t\t\t\t reformat_src, reformat_pos, 0, 0, data_size)) {\n+\t\t\tgoto err;\n+\t\t}\n+\t\tacts->encap_decap = mlx5_malloc(MLX5_MEM_ZERO,\n+\t\t\t\t sizeof(*acts->encap_decap) + data_size,\n+\t\t\t\t 0, SOCKET_ID_ANY);\n+\t\tif (!acts->encap_decap)\n+\t\t\tgoto err;\n+\t\tif (data_size) {\n+\t\t\tacts->encap_decap->data_size = data_size;\n+\t\t\tmemcpy(acts->encap_decap->data, encap_data, data_size);\n+\t\t}\n+\t\tacts->encap_decap->action = mlx5dr_action_create_reformat\n+\t\t\t\t(priv->dr_ctx, refmt_type,\n+\t\t\t\t data_size, encap_data,\n+\t\t\t\t rte_log2_u32(table_attr->nb_flows),\n+\t\t\t\t mlx5_hw_act_flag[!!attr->group][type]);\n+\t\tif (!acts->encap_decap->action)\n+\t\t\tgoto err;\n+\t\tacts->rule_acts[reformat_pos].action =\n+\t\t\t\t\t\tacts->encap_decap->action;\n+\t\tacts->encap_decap_pos = reformat_pos;\n+\t}\n \tacts->acts_num = i;\n \treturn 0;\n err:\n@@ -735,6 +921,9 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \tstruct rte_flow_template_table *table = job->flow->table;\n \tstruct mlx5_action_construct_data *act_data;\n \tconst struct rte_flow_action *action;\n+\tconst struct rte_flow_action_raw_encap *raw_encap_data;\n+\tconst struct rte_flow_item *enc_item = NULL;\n+\tuint8_t *buf = job->encap_data;\n \tstruct rte_flow_attr attr = {\n \t\t\t.ingress = 1,\n \t};\n@@ -756,6 +945,9 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t} else {\n \t\tattr.ingress = 1;\n \t}\n+\tif (hw_acts->encap_decap && hw_acts->encap_decap->data_size)\n+\t\tmemcpy(buf, hw_acts->encap_decap->data,\n+\t\t hw_acts->encap_decap->data_size);\n \tLIST_FOREACH(act_data, &hw_acts->act_list, next) {\n \t\tuint32_t jump_group;\n \t\tuint32_t tag;\n@@ -811,10 +1003,38 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t\t &rule_acts[act_data->action_dst]))\n \t\t\t\treturn -1;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:\n+\t\t\tenc_item = ((const struct rte_flow_action_vxlan_encap *)\n+\t\t\t\t action->conf)->definition;\n+\t\t\trte_memcpy((void *)&buf[act_data->encap.dst],\n+\t\t\t\t enc_item[act_data->encap.src].spec,\n+\t\t\t\t act_data->encap.len);\n+\t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:\n+\t\t\tenc_item = ((const struct rte_flow_action_nvgre_encap *)\n+\t\t\t\t action->conf)->definition;\n+\t\t\trte_memcpy((void *)&buf[act_data->encap.dst],\n+\t\t\t\t enc_item[act_data->encap.src].spec,\n+\t\t\t\t act_data->encap.len);\n+\t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_RAW_ENCAP:\n+\t\t\traw_encap_data =\n+\t\t\t\t(const struct rte_flow_action_raw_encap *)\n+\t\t\t\t action->conf;\n+\t\t\trte_memcpy((void *)&buf[act_data->encap.dst],\n+\t\t\t\t raw_encap_data->data, act_data->encap.len);\n+\t\t\tMLX5_ASSERT(raw_encap_data->size ==\n+\t\t\t\t act_data->encap.len);\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tbreak;\n \t\t}\n \t}\n+\tif (hw_acts->encap_decap) {\n+\t\trule_acts[hw_acts->encap_decap_pos].reformat.offset =\n+\t\t\t\tjob->flow->idx - 1;\n+\t\trule_acts[hw_acts->encap_decap_pos].reformat.data = buf;\n+\t}\n \treturn 0;\n }\n \n@@ -1821,6 +2041,7 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\t\tgoto err;\n \t\t}\n \t\tmem_size += (sizeof(struct mlx5_hw_q_job *) +\n+\t\t\t sizeof(uint8_t) * MLX5_ENCAP_MAX_LEN +\n \t\t\t sizeof(struct mlx5_hw_q_job)) *\n \t\t\t queue_attr[0]->size;\n \t}\n@@ -1831,6 +2052,8 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\tgoto err;\n \t}\n \tfor (i = 0; i < nb_queue; i++) {\n+\t\tuint8_t *encap = NULL;\n+\n \t\tpriv->hw_q[i].job_idx = queue_attr[i]->size;\n \t\tpriv->hw_q[i].size = queue_attr[i]->size;\n \t\tif (i == 0)\n@@ -1841,8 +2064,11 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\t\t\t\t &job[queue_attr[i - 1]->size];\n \t\tjob = (struct mlx5_hw_q_job *)\n \t\t &priv->hw_q[i].job[queue_attr[i]->size];\n-\t\tfor (j = 0; j < queue_attr[i]->size; j++)\n+\t\tencap = (uint8_t *)&job[queue_attr[i]->size];\n+\t\tfor (j = 0; j < queue_attr[i]->size; j++) {\n+\t\t\tjob[j].encap_data = &encap[j * MLX5_ENCAP_MAX_LEN];\n \t\t\tpriv->hw_q[i].job[j] = &job[j];\n+\t\t}\n \t}\n \tdr_ctx_attr.pd = priv->sh->cdev->pd;\n \tdr_ctx_attr.queues = nb_queue;\n", "prefixes": [ "13/13" ] }