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GET /api/patches/106974/?format=api
{ "id": 106974, "url": "https://patches.dpdk.org/api/patches/106974/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220207135511.3012285-1-jerinj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220207135511.3012285-1-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220207135511.3012285-1-jerinj@marvell.com", "date": "2022-02-07T13:55:09", "name": "[v4,1/2] ethdev: support queue-based priority flow control", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ef16bab03c639ebe8640cc53636af1bb6a906b21", "submitter": { "id": 1188, "url": "https://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220207135511.3012285-1-jerinj@marvell.com/mbox/", "series": [ { "id": 21495, "url": "https://patches.dpdk.org/api/series/21495/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=21495", "date": "2022-02-07T13:55:09", "name": "[v4,1/2] ethdev: support queue-based priority flow control", "version": 4, "mbox": "https://patches.dpdk.org/series/21495/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/106974/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/106974/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 43071A034F;\n\tMon, 7 Feb 2022 14:54:48 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 31A24410FB;\n\tMon, 7 Feb 2022 14:54:48 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 24B3C410EA\n for <dev@dpdk.org>; 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d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=ZaSDtaAf1JexcIeuvPmqz3+3aKO/KxLgcRc06hGwasU=;\n b=S2XLuViH1wEm4I+3GEFtNGA94NENLIB+jcHdv9eHmPTMNxqNb1MQ4zpubmIvjxsgya2Y\n 2K3XL52oU/4WCs0SBRquGWhSeb5gV6L1j6bymzsgYp836NuHB/BoMDoR9XifIm3Uboh/\n vcAT7mvgR5pw2G77SpVONDQ9q6sO8YWLhODbxK+xMcA+Z9MqL0xJ98qOKrAPUlhDQ63r\n 4ruU4qbM7HngidHlsXG9ptjAsubiR5Y7hydfw7Hh4seO9IvVh5m4FPLxS9lAxXeVRT9D\n AIrtphRR3BwnNzTAdOlVp/Z4/+jj79iwGFN9EbztUR/n19yxOP/yV7HSrCB6eojEw8cv Og==", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Thomas Monjalon <thomas@monjalon.net>, Ferruh Yigit\n <ferruh.yigit@intel.com>, Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,\n Ray Kinsella <mdr@ashroe.eu>", "CC": "<ajit.khaparde@broadcom.com>, <aboyer@pensando.io>,\n <beilei.xing@intel.com>, <bruce.richardson@intel.com>, <chas3@att.com>,\n <chenbo.xia@intel.com>, <ciara.loftus@intel.com>,\n <dsinghrawat@marvell.com>, <ed.czeck@atomicrules.com>,\n <evgenys@amazon.com>, <grive@u256.net>, <g.singh@nxp.com>,\n <zhouguoyang@huawei.com>, <haiyue.wang@intel.com>,\n <hkalra@marvell.com>, <heinrich.kuhn@corigine.com>,\n <hemant.agrawal@nxp.com>, <hyonkim@cisco.com>, <igorch@amazon.com>,\n <irusskikh@marvell.com>, <jgrajcia@cisco.com>,\n <jasvinder.singh@intel.com>, <jianwang@trustnetic.com>,\n <jiawenwu@trustnetic.com>, <jingjing.wu@intel.com>,\n <johndale@cisco.com>, <john.miller@atomicrules.com>,\n <linville@tuxdriver.com>, <keith.wiles@intel.com>,\n <kirankumark@marvell.com>, <oulijun@huawei.com>, <lironh@marvell.com>,\n <longli@microsoft.com>, <mw@semihalf.com>, <spinler@cesnet.cz>,\n <matan@nvidia.com>, <matt.peters@windriver.com>,\n <maxime.coquelin@redhat.com>, <mk@semihalf.com>, <humin29@huawei.com>,\n <pnalla@marvell.com>, <ndabilpuram@marvell.com>,\n <qiming.yang@intel.com>, <qi.z.zhang@intel.com>, <radhac@marvell.com>,\n <rahul.lakkireddy@chelsio.com>, <rmody@marvell.com>,\n <rosen.xu@intel.com>, <sachin.saxena@oss.nxp.com>,\n <skoteshwar@marvell.com>, <shshaikh@marvell.com>,\n <shaibran@amazon.com>, <shepard.siegel@atomicrules.com>,\n <asomalap@amd.com>, <somnath.kotur@broadcom.com>,\n <sthemmin@microsoft.com>, <steven.webster@windriver.com>,\n <skori@marvell.com>, <mtetsuyah@gmail.com>, <vburru@marvell.com>,\n <viacheslavo@nvidia.com>, <xiao.w.wang@intel.com>,\n <cloud.wangxiaoyun@huawei.com>, <yisen.zhuang@huawei.com>,\n <yongwang@vmware.com>, <xuanziyang2@huawei.com>, Jerin Jacob\n <jerinj@marvell.com>", "Subject": "[dpdk-dev] [PATCH v4 1/2] ethdev: support queue-based priority flow\n control", "Date": "Mon, 7 Feb 2022 19:25:09 +0530", "Message-ID": "<20220207135511.3012285-1-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.35.1", "In-Reply-To": "<20220131180859.2662034-1-jerinj@marvell.com>", "References": "<20220131180859.2662034-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "K91MwGT6NB92LXdAdw1JgXwzMniw5n3R", "X-Proofpoint-GUID": "K91MwGT6NB92LXdAdw1JgXwzMniw5n3R", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2022-02-07_05,2022-02-07_02,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nBased on device support and use-case need, there are two different ways\nto enable PFC. The first case is the port level PFC configuration, in\nthis case, rte_eth_dev_priority_flow_ctrl_set() API shall be used to\nconfigure the PFC, and PFC frames will be generated using based on VLAN\nTC value.\n\nThe second case is the queue level PFC configuration, in this\ncase, Any packet field content can be used to steer the packet to the\nspecific queue using rte_flow or RSS and then use\nrte_eth_dev_priority_flow_ctrl_queue_configure() to configure the\nTC mapping on each queue.\nBased on congestion selected on the specific queue, configured TC\nshall be used to generate PFC frames.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n\nv4..v3:\n\n- Remove RTE_ETH_PFC_QUEUE_CAPA_* and replace with enum rte_eth_fc_mode mode_capa\n- More documentaion\n- Address the comment from Ferruh in\nhttp://patches.dpdk.org/project/dpdk/patch/20220131180859.2662034-1-jerinj@marvell.com/\n\nv3..v1:\n\n- Introduce rte_eth_dev_priority_flow_ctrl_queue_info_get() to\navoid updates to rte_eth_dev_info\n\n- Removed devtools/libabigail.abignore changes\n- Address the comment from Ferruh in\nhttp://patches.dpdk.org/project/dpdk/patch/20220113102718.3167282-1-jerinj@marvell.com/\n\n\n doc/guides/nics/features.rst | 7 +-\n doc/guides/rel_notes/release_22_03.rst | 5 +\n lib/ethdev/ethdev_driver.h | 11 ++\n lib/ethdev/rte_ethdev.c | 139 +++++++++++++++++++++++++\n lib/ethdev/rte_ethdev.h | 100 ++++++++++++++++++\n lib/ethdev/version.map | 4 +\n 6 files changed, 264 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst\nindex 27be2d2576..1cacdc883a 100644\n--- a/doc/guides/nics/features.rst\n+++ b/doc/guides/nics/features.rst\n@@ -379,9 +379,12 @@ Flow control\n Supports configuring link flow control.\n \n * **[implements] eth_dev_ops**: ``flow_ctrl_get``, ``flow_ctrl_set``,\n- ``priority_flow_ctrl_set``.\n+ ``priority_flow_ctrl_set``, ``priority_flow_ctrl_queue_info_get``,\n+ ``priority_flow_ctrl_queue_configure``\n * **[related] API**: ``rte_eth_dev_flow_ctrl_get()``, ``rte_eth_dev_flow_ctrl_set()``,\n- ``rte_eth_dev_priority_flow_ctrl_set()``.\n+ ``rte_eth_dev_priority_flow_ctrl_set()``,\n+ ``rte_eth_dev_priority_flow_ctrl_queue_info_get()``,\n+ ``rte_eth_dev_priority_flow_ctrl_queue_configure()``.\n \n \n .. _nic_features_rate_limitation:\ndiff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst\nindex 746f50e84f..2ec6f53efe 100644\n--- a/doc/guides/rel_notes/release_22_03.rst\n+++ b/doc/guides/rel_notes/release_22_03.rst\n@@ -55,6 +55,11 @@ New Features\n Also, make sure to start the actual text at the margin.\n =======================================================\n \n+* **Added an API to enable queue based priority flow ctrl(PFC).**\n+\n+ New APIs, ``rte_eth_dev_priority_flow_ctrl_queue_info_get()`` and\n+ ``rte_eth_dev_priority_flow_ctrl_queue_configure()``, was added.\n+\n * **Updated Cisco enic driver.**\n \n * Added rte_flow support for matching GENEVE packets.\ndiff --git a/lib/ethdev/ethdev_driver.h b/lib/ethdev/ethdev_driver.h\nindex d95605a355..d4d396468c 100644\n--- a/lib/ethdev/ethdev_driver.h\n+++ b/lib/ethdev/ethdev_driver.h\n@@ -533,6 +533,13 @@ typedef int (*flow_ctrl_set_t)(struct rte_eth_dev *dev,\n typedef int (*priority_flow_ctrl_set_t)(struct rte_eth_dev *dev,\n \t\t\t\tstruct rte_eth_pfc_conf *pfc_conf);\n \n+/** @internal Get info for queue based PFC on an Ethernet device. */\n+typedef int (*priority_flow_ctrl_queue_info_get_t)(struct rte_eth_dev *dev,\n+\t\t\tstruct rte_eth_pfc_queue_info *pfc_queue_info);\n+/** @internal Configure queue based PFC parameter on an Ethernet device. */\n+typedef int (*priority_flow_ctrl_queue_config_t)(struct rte_eth_dev *dev,\n+\t\t\tstruct rte_eth_pfc_queue_conf *pfc_queue_conf);\n+\n /** @internal Update RSS redirection table on an Ethernet device. */\n typedef int (*reta_update_t)(struct rte_eth_dev *dev,\n \t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n@@ -1080,6 +1087,10 @@ struct eth_dev_ops {\n \tflow_ctrl_set_t flow_ctrl_set; /**< Setup flow control */\n \t/** Setup priority flow control */\n \tpriority_flow_ctrl_set_t priority_flow_ctrl_set;\n+\t/** Priority flow control queue info get */\n+\tpriority_flow_ctrl_queue_info_get_t priority_flow_ctrl_queue_info_get;\n+\t/** Priority flow control queue configure */\n+\tpriority_flow_ctrl_queue_config_t priority_flow_ctrl_queue_config;\n \n \t/** Set Unicast Table Array */\n \teth_uc_hash_table_set_t uc_hash_table_set;\ndiff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c\nindex 29e21ad580..882f231e42 100644\n--- a/lib/ethdev/rte_ethdev.c\n+++ b/lib/ethdev/rte_ethdev.c\n@@ -4022,6 +4022,145 @@ rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id,\n \treturn -ENOTSUP;\n }\n \n+static int\n+validate_rx_pause_config(struct rte_eth_dev_info *dev_info, uint8_t tc_max,\n+\t\t\t struct rte_eth_pfc_queue_conf *pfc_queue_conf)\n+{\n+\tif ((pfc_queue_conf->mode == RTE_ETH_FC_RX_PAUSE) ||\n+\t\t\t(pfc_queue_conf->mode == RTE_ETH_FC_FULL)) {\n+\t\tif (pfc_queue_conf->rx_pause.tx_qid >= dev_info->nb_tx_queues) {\n+\t\t\tRTE_ETHDEV_LOG(ERR, \"PFC Tx queue not in range for Rx pause requested:%d configured:%d\\n\",\n+\t\t\t\t pfc_queue_conf->rx_pause.tx_qid,\n+\t\t\t\t dev_info->nb_tx_queues);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tif (pfc_queue_conf->rx_pause.tc >= tc_max) {\n+\t\t\tRTE_ETHDEV_LOG(ERR, \"PFC TC not in range for Rx pause requested:%d max:%d\\n\",\n+\t\t\t\t pfc_queue_conf->rx_pause.tc, tc_max);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+validate_tx_pause_config(struct rte_eth_dev_info *dev_info, uint8_t tc_max,\n+\t\t\t struct rte_eth_pfc_queue_conf *pfc_queue_conf)\n+{\n+\tif ((pfc_queue_conf->mode == RTE_ETH_FC_TX_PAUSE) ||\n+\t\t\t(pfc_queue_conf->mode == RTE_ETH_FC_FULL)) {\n+\t\tif (pfc_queue_conf->tx_pause.rx_qid >= dev_info->nb_rx_queues) {\n+\t\t\tRTE_ETHDEV_LOG(ERR, \"PFC Rx queue not in range for Tx pause requested:%d configured:%d\\n\",\n+\t\t\t\t pfc_queue_conf->tx_pause.rx_qid,\n+\t\t\t\t dev_info->nb_rx_queues);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tif (pfc_queue_conf->tx_pause.tc >= tc_max) {\n+\t\t\tRTE_ETHDEV_LOG(ERR, \"PFC TC not in range for Tx pause requested:%d max:%d\\n\",\n+\t\t\t\t pfc_queue_conf->tx_pause.tc, tc_max);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+rte_eth_dev_priority_flow_ctrl_queue_info_get(\n+\tuint16_t port_id, struct rte_eth_pfc_queue_info *pfc_queue_info)\n+{\n+\tstruct rte_eth_dev *dev;\n+\n+\tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n+\tdev = &rte_eth_devices[port_id];\n+\n+\tif (pfc_queue_info == NULL) {\n+\t\tRTE_ETHDEV_LOG(ERR, \"PFC info param is NULL for port (%u)\\n\",\n+\t\t\t port_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (*dev->dev_ops->priority_flow_ctrl_queue_info_get)\n+\t\treturn eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_queue_info_get)\n+\t\t\t\t\t (dev, pfc_queue_info));\n+\treturn -ENOTSUP;\n+}\n+\n+int\n+rte_eth_dev_priority_flow_ctrl_queue_configure(\n+\tuint16_t port_id, struct rte_eth_pfc_queue_conf *pfc_queue_conf)\n+{\n+\tstruct rte_eth_pfc_queue_info pfc_info;\n+\tstruct rte_eth_dev_info dev_info;\n+\tstruct rte_eth_dev *dev;\n+\tint ret;\n+\n+\tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n+\tdev = &rte_eth_devices[port_id];\n+\n+\tif (pfc_queue_conf == NULL) {\n+\t\tRTE_ETHDEV_LOG(ERR, \"PFC parameters are NULL for port (%u)\\n\",\n+\t\t\t port_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = rte_eth_dev_info_get(port_id, &dev_info);\n+\tif (ret != 0)\n+\t\treturn ret;\n+\n+\tret = rte_eth_dev_priority_flow_ctrl_queue_info_get(port_id, &pfc_info);\n+\tif (ret != 0)\n+\t\treturn ret;\n+\n+\tif (pfc_info.tc_max == 0) {\n+\t\tRTE_ETHDEV_LOG(ERR, \"Ethdev port %u does not support PFC TC values\\n\",\n+\t\t\t port_id);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\t/* Check requested mode supported or not */\n+\tif (pfc_info.mode_capa == RTE_ETH_FC_RX_PAUSE &&\n+\t\t\tpfc_queue_conf->mode == RTE_ETH_FC_TX_PAUSE) {\n+\t\tRTE_ETHDEV_LOG(ERR, \"PFC Tx pause unsupported for port (%d)\\n\",\n+\t\t\t port_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (pfc_info.mode_capa == RTE_ETH_FC_TX_PAUSE &&\n+\t\t\tpfc_queue_conf->mode == RTE_ETH_FC_RX_PAUSE) {\n+\t\tRTE_ETHDEV_LOG(ERR, \"PFC Rx pause unsupported for port (%d)\\n\",\n+\t\t\t port_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Validate Rx pause parameters */\n+\tif (pfc_info.mode_capa == RTE_ETH_FC_FULL ||\n+\t\t\tpfc_info.mode_capa == RTE_ETH_FC_RX_PAUSE) {\n+\t\tret = validate_rx_pause_config(&dev_info, pfc_info.tc_max,\n+\t\t\t\t\t pfc_queue_conf);\n+\t\tif (ret != 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* Validate Tx pause parameters */\n+\tif (pfc_info.mode_capa == RTE_ETH_FC_FULL ||\n+\t\t\tpfc_info.mode_capa == RTE_ETH_FC_TX_PAUSE) {\n+\t\tret = validate_tx_pause_config(&dev_info, pfc_info.tc_max,\n+\t\t\t\t\t pfc_queue_conf);\n+\t\tif (ret != 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\tif (*dev->dev_ops->priority_flow_ctrl_queue_config)\n+\t\treturn eth_err(port_id,\n+\t\t\t (*dev->dev_ops->priority_flow_ctrl_queue_config)(\n+\t\t\t\t dev, pfc_queue_conf));\n+\treturn -ENOTSUP;\n+}\n+\n static int\n eth_check_reta_mask(struct rte_eth_rss_reta_entry64 *reta_conf,\n \t\t\tuint16_t reta_size)\ndiff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h\nindex 147cc1ced3..c526c8fc0a 100644\n--- a/lib/ethdev/rte_ethdev.h\n+++ b/lib/ethdev/rte_ethdev.h\n@@ -1408,6 +1408,59 @@ struct rte_eth_pfc_conf {\n \tuint8_t priority; /**< VLAN User Priority. */\n };\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * A structure used to retrieve information of queue based PFC.\n+ */\n+struct rte_eth_pfc_queue_info {\n+\t/**\n+\t * Maximum supported traffic class as per PFC (802.1Qbb) specification.\n+\t */\n+\tuint8_t tc_max;\n+\t/** PFC queue mode capabilities. */\n+\tenum rte_eth_fc_mode mode_capa;\n+};\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * A structure used to configure Ethernet priority flow control parameter for\n+ * ethdev queues.\n+ *\n+ * rte_eth_pfc_queue_conf::rx_pause structure shall used to configure given\n+ * tx_qid with corresponding tc. When ethdev device receives PFC frame with\n+ * rte_eth_pfc_queue_conf::rx_pause::tc, traffic will be paused on\n+ * rte_eth_pfc_queue_conf::rx_pause::tx_qid for that tc.\n+ *\n+ * rte_eth_pfc_queue_conf::tx_pause structure shall used to configure given\n+ * rx_qid. When rx_qid is congested, PFC frames are generated with\n+ * rte_eth_pfc_queue_conf::rx_pause::tc and\n+ * rte_eth_pfc_queue_conf::rx_pause::pause_time to the peer.\n+ */\n+struct rte_eth_pfc_queue_conf {\n+\tenum rte_eth_fc_mode mode; /**< Link flow control mode */\n+\n+\tstruct {\n+\t\tuint16_t tx_qid; /**< Tx queue ID */\n+\t\tuint8_t tc;\n+\t\t/**< Traffic class as per PFC (802.1Qbb) spec. The value must be\n+\t\t * in the range [0, rte_eth_pfc_queue_info::tx_max - 1]\n+\t\t */\n+\t} rx_pause; /* Valid when (mode == FC_RX_PAUSE || mode == FC_FULL) */\n+\n+\tstruct {\n+\t\tuint16_t pause_time; /**< Pause quota in the Pause frame */\n+\t\tuint16_t rx_qid; /**< Rx queue ID */\n+\t\tuint8_t tc;\n+\t\t/**< Traffic class as per PFC (802.1Qbb) spec. The value must be\n+\t\t * in the range [0, rte_eth_pfc_queue_info::tx_max - 1]\n+\t\t */\n+\t} tx_pause; /* Valid when (mode == FC_TX_PAUSE || mode == FC_FULL) */\n+};\n+\n /**\n * Tunnel type for device-specific classifier configuration.\n * @see rte_eth_udp_tunnel\n@@ -4158,6 +4211,53 @@ int rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id,\n int rte_eth_dev_mac_addr_add(uint16_t port_id, struct rte_ether_addr *mac_addr,\n \t\t\t\tuint32_t pool);\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Retrieve the information for queue based PFC.\n+ *\n+ * @param port_id\n+ * The port identifier of the Ethernet device.\n+ * @param pfc_queue_info\n+ * A pointer to a structure of type *rte_eth_pfc_queue_info* to be filled with\n+ * the information about queue based PFC.\n+ * @return\n+ * - (0) if successful.\n+ * - (-ENOTSUP) if support for priority_flow_ctrl_queue_info_get does not exist.\n+ * - (-ENODEV) if *port_id* invalid.\n+ * - (-EINVAL) if bad parameter.\n+ */\n+__rte_experimental\n+int rte_eth_dev_priority_flow_ctrl_queue_info_get(uint16_t port_id,\n+\t\t\t\t struct rte_eth_pfc_queue_info *pfc_queue_info);\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Configure the queue based priority flow control for a given queue\n+ * for Ethernet device.\n+ *\n+ * @note When an ethdev port switches to queue based PFC mode, the\n+ * unconfigured queues shall be configured by the driver with\n+ * default values such as lower priority value for TC etc.\n+ *\n+ * @param port_id\n+ * The port identifier of the Ethernet device.\n+ * @param pfc_queue_conf\n+ * The pointer to the structure of the priority flow control parameters\n+ * for the queue.\n+ * @return\n+ * - (0) if successful.\n+ * - (-ENOTSUP) if hardware doesn't support queue based PFC mode.\n+ * - (-ENODEV) if *port_id* invalid.\n+ * - (-EINVAL) if bad parameter\n+ * - (-EIO) if flow control setup queue failure\n+ */\n+__rte_experimental\n+int rte_eth_dev_priority_flow_ctrl_queue_configure(uint16_t port_id,\n+\t\t\t struct rte_eth_pfc_queue_conf *pfc_queue_conf);\n+\n /**\n * Remove a MAC address from the internal array of addresses.\n *\ndiff --git a/lib/ethdev/version.map b/lib/ethdev/version.map\nindex c2fb0669a4..49523ebc45 100644\n--- a/lib/ethdev/version.map\n+++ b/lib/ethdev/version.map\n@@ -256,6 +256,10 @@ EXPERIMENTAL {\n \trte_flow_flex_item_create;\n \trte_flow_flex_item_release;\n \trte_flow_pick_transfer_proxy;\n+\n+\t# added in 22.03\n+\trte_eth_dev_priority_flow_ctrl_queue_configure;\n+\trte_eth_dev_priority_flow_ctrl_queue_info_get;\n };\n \n INTERNAL {\n", "prefixes": [ "v4", "1/2" ] }