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{
    "id": 106,
    "url": "https://patches.dpdk.org/api/patches/106/?format=api",
    "web_url": "https://patches.dpdk.org/patch/106/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1406535955-31070-4-git-send-email-helin.zhang@intel.com>",
    "date": "2014-07-28T08:25:52",
    "name": "[dpdk-dev,v2,3/6] i40e: support of 'rx_classification_filter_ctl'",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "ac37ba2b8eafc7714ce1c31a379954adc92b64da",
    "submitter": {
        "id": 14,
        "url": "https://patches.dpdk.org/api/people/14/?format=api",
        "name": "Helin Zhang",
        "email": "helin.zhang@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/patch/106/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/106/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/106/checks/",
    "tags": {},
    "headers": {
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "Return-Path": "<hzhan75@shecgisg004.sh.intel.com>",
        "Message-Id": "<1406535955-31070-4-git-send-email-helin.zhang@intel.com>",
        "X-Mailer": "git-send-email 1.7.0.7",
        "To": "dev@dpdk.org",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-BeenThere": "dev@dpdk.org",
        "Received": [
            "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 3C5AF959\n\tfor <dev@dpdk.org>; Mon, 28 Jul 2014 10:24:38 +0200 (CEST)",
            "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga102.fm.intel.com with ESMTP; 28 Jul 2014 01:26:22 -0700",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 28 Jul 2014 01:26:12 -0700",
            "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s6S8Q9LV022891;\n\tMon, 28 Jul 2014 16:26:09 +0800",
            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s6S8Q5r9031201; Mon, 28 Jul 2014 16:26:07 +0800",
            "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s6S8Q5jB031197; \n\tMon, 28 Jul 2014 16:26:05 +0800"
        ],
        "Subject": "[dpdk-dev] [PATCH v2 3/6] i40e: support of\n\t'rx_classification_filter_ctl'",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "In-Reply-To": "<1406535955-31070-1-git-send-email-helin.zhang@intel.com>",
        "X-ExtLoop1": "1",
        "Precedence": "list",
        "From": "Helin Zhang <helin.zhang@intel.com>",
        "X-IronPort-AV": "E=Sophos;i=\"5.01,747,1400050800\"; d=\"scan'208\";a=\"568219948\"",
        "References": "<1406535955-31070-1-git-send-email-helin.zhang@intel.com>",
        "X-List-Received-Date": "Mon, 28 Jul 2014 08:24:39 -0000",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Date": "Mon, 28 Jul 2014 16:25:52 +0800",
        "X-Mailman-Version": "2.1.15"
    },
    "content": "'rx_classification_filter_ctl' was defined as a common API\nfor receive classification filter features. Eight commands\nhas been implemented for selecting hash functions of\n'Toeplitz' and 'Simple XOR', and configuring symmetric hash\nfunctions. In detail,\nRTE_CMD_GET_SYM_HASH_ENABLE_PER_PCTYPE:\n - Get symmetric hash enable configuration per 'PCTYPE'.\nRTE_CMD_SET_SYM_HASH_ENABLE_PER_PCTYPE:\n - Set symmetric hash enable configuration per 'PCTYPE'.\nRTE_CMD_GET_SYM_HASH_ENABLE_PER_PORT:\n - Get symmetric hash enable configuration per port.\nRTE_CMD_SET_SYM_HASH_ENABLE_PER_PORT:\n - Set symmetric hash enable configuration per port.\nRTE_CMD_GET_FILTER_SWAP:\n - Get filter swap configurations.\nRTE_CMD_SET_FILTER_SWAP:\n - Set filter swap configurations.\nRTE_CMD_GET_HASH_FUNCTION:\n - Get current hash function.\nRTE_CMD_SET_HASH_FUNCTION:\n - Set hash function of 'Toeplitz' or 'Simple XOR'.\nNote that 'PCTYPE' means 'Packet Classification Type'.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\n---\n lib/librte_pmd_i40e/Makefile      |   6 +\n lib/librte_pmd_i40e/i40e_ethdev.c | 385 ++++++++++++++++++++++++++++++++++++++\n lib/librte_pmd_i40e/i40e_ethdev.h |   2 +\n lib/librte_pmd_i40e/rte_i40e.h    | 108 +++++++++++\n 4 files changed, 501 insertions(+)\n create mode 100644 lib/librte_pmd_i40e/rte_i40e.h",
    "diff": "diff --git a/lib/librte_pmd_i40e/Makefile b/lib/librte_pmd_i40e/Makefile\nindex 4b31675..a777a76 100644\n--- a/lib/librte_pmd_i40e/Makefile\n+++ b/lib/librte_pmd_i40e/Makefile\n@@ -87,6 +87,12 @@ SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_ethdev.c\n SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_rxtx.c\n SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_ethdev_vf.c\n SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_pf.c\n+\n+#\n+# Export include file\n+#\n+SYMLINK-$(CONFIG_RTE_LIBRTE_I40E_PMD)-include += rte_i40e.h\n+\n # this lib depends upon:\n DEPDIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += lib/librte_eal lib/librte_ether\n DEPDIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += lib/librte_mempool lib/librte_mbuf\ndiff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c\nindex 9ed31b5..4403af4 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.c\n@@ -48,6 +48,7 @@\n #include <rte_malloc.h>\n #include <rte_memcpy.h>\n #include <rte_dev.h>\n+#include <rte_eth_features.h>\n \n #include \"i40e_logs.h\"\n #include \"i40e/i40e_register_x710_int.h\"\n@@ -203,6 +204,9 @@ static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,\n \t\t\t\t    struct rte_eth_rss_conf *rss_conf);\n static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n \t\t\t\t      struct rte_eth_rss_conf *rss_conf);\n+static int i40e_rx_classification_filter_ctl(struct rte_eth_dev *dev,\n+\t\t\t\t\t     enum rte_eth_command cmd,\n+\t\t\t\t\t     void *args);\n \n /* Default hash key buffer for RSS */\n static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];\n@@ -248,6 +252,7 @@ static struct eth_dev_ops i40e_eth_dev_ops = {\n \t.reta_query                   = i40e_dev_rss_reta_query,\n \t.rss_hash_update              = i40e_dev_rss_hash_update,\n \t.rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,\n+\t.rx_classification_filter_ctl = i40e_rx_classification_filter_ctl,\n };\n \n static struct eth_driver rte_i40e_pmd = {\n@@ -3956,3 +3961,383 @@ i40e_pf_config_mq_rx(struct i40e_pf *pf)\n \n \treturn 0;\n }\n+\n+static int\n+i40e_get_filter_swap(struct i40e_hw *hw, struct rte_i40e_filter_swap_info *info)\n+{\n+\tuint32_t reg;\n+\n+\tif (!hw || !info) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tswitch (info->pctype) {\n+\tcase ETH_PCTYPE_NONF_IPV4_UDP:\n+\tcase ETH_PCTYPE_NONF_IPV4_TCP:\n+\tcase ETH_PCTYPE_NONF_IPV4_SCTP:\n+\tcase ETH_PCTYPE_NONF_IPV4_OTHER:\n+\tcase ETH_PCTYPE_FRAG_IPV4:\n+\tcase ETH_PCTYPE_NONF_IPV6_UDP:\n+\tcase ETH_PCTYPE_NONF_IPV6_TCP:\n+\tcase ETH_PCTYPE_NONF_IPV6_SCTP:\n+\tcase ETH_PCTYPE_NONF_IPV6_OTHER:\n+\tcase ETH_PCTYPE_FRAG_IPV6:\n+\tcase ETH_PCTYPE_L2_PAYLOAD:\n+\t\treg = I40E_READ_REG(hw, I40E_GLQF_SWAP(0, info->pctype));\n+\t\tPMD_DRV_LOG(DEBUG, \"Value read from I40E_GLQF_SWAP[0,%d]: \"\n+\t\t\t\t\t\"0x%x\\n\", info->pctype, reg);\n+\n+\t\t/**\n+\t\t * The offset and length read from register in word unit,\n+\t\t * which need to be converted in byte unit before being saved.\n+\t\t */\n+\t\tinfo->off0_src0 =\n+\t\t\t(uint8_t)((reg & I40E_GLQF_SWAP_OFF0_SRC0_MASK) >>\n+\t\t\t\tI40E_GLQF_SWAP_OFF0_SRC0_SHIFT) << 1;\n+\t\tinfo->off0_src1 =\n+\t\t\t(uint8_t)((reg & I40E_GLQF_SWAP_OFF0_SRC1_MASK) >>\n+\t\t\t\tI40E_GLQF_SWAP_OFF0_SRC1_SHIFT) << 1;\n+\t\tinfo->len0 = (uint8_t)((reg & I40E_GLQF_SWAP_FLEN0_MASK) >>\n+\t\t\t\t\tI40E_GLQF_SWAP_FLEN0_SHIFT) << 1;\n+\t\tinfo->off1_src0 =\n+\t\t\t(uint8_t)((reg & I40E_GLQF_SWAP_OFF1_SRC0_MASK) >>\n+\t\t\t\tI40E_GLQF_SWAP_OFF1_SRC0_SHIFT) << 1;\n+\t\tinfo->off1_src1 =\n+\t\t\t(uint8_t)((reg & I40E_GLQF_SWAP_OFF1_SRC1_MASK) >>\n+\t\t\t\tI40E_GLQF_SWAP_OFF1_SRC1_SHIFT) << 1;\n+\t\tinfo->len1 = (uint8_t)((reg & I40E_GLQF_SWAP_FLEN1_MASK) >>\n+\t\t\t\t\tI40E_GLQF_SWAP_FLEN1_SHIFT) << 1;\n+\t\tbreak;\n+\tcase ETH_PCTYPE_FCOE_OX:\n+\tcase ETH_PCTYPE_FCOE_RX:\n+\tcase ETH_PCTYPE_FCOE_OTHER:\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"PCTYPE[%u] is out of supported range\\n\",\n+\t\t\t\t\t\t\tinfo->pctype);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_set_filter_swap(struct i40e_hw *hw, struct rte_i40e_filter_swap_info *info)\n+{\n+#define I40E_FIELD_LEN_MAX 0x1f\n+#define I40E_FIELD_OFFSET_MAX 0x7f\n+\tuint32_t reg;\n+\n+\tif (!hw || !info) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tswitch (info->pctype) {\n+\tcase ETH_PCTYPE_NONF_IPV4_UDP:\n+\tcase ETH_PCTYPE_NONF_IPV4_TCP:\n+\tcase ETH_PCTYPE_NONF_IPV4_SCTP:\n+\tcase ETH_PCTYPE_NONF_IPV4_OTHER:\n+\tcase ETH_PCTYPE_FRAG_IPV4:\n+\tcase ETH_PCTYPE_NONF_IPV6_UDP:\n+\tcase ETH_PCTYPE_NONF_IPV6_TCP:\n+\tcase ETH_PCTYPE_NONF_IPV6_SCTP:\n+\tcase ETH_PCTYPE_NONF_IPV6_OTHER:\n+\tcase ETH_PCTYPE_FRAG_IPV6:\n+\tcase ETH_PCTYPE_L2_PAYLOAD:\n+\t\tif (info->off0_src0 > I40E_FIELD_OFFSET_MAX) {\n+\t\t\tPMD_DRV_LOG(ERR, \"off0_src0 (0x%x) exceeds the \"\n+\t\t\t\t\"maximum of 0x%x\\n\", info->off0_src0,\n+\t\t\t\t\t\tI40E_FIELD_OFFSET_MAX);\n+\t\t\treturn -1;\n+\t\t} else if (info->off0_src1 > I40E_FIELD_OFFSET_MAX) {\n+\t\t\tPMD_DRV_LOG(ERR, \"off0_src1 (0x%x) exceeds the \"\n+\t\t\t\t\"maximum of 0x%x\\n\", info->off0_src1,\n+\t\t\t\t\t\tI40E_FIELD_OFFSET_MAX);\n+\t\t\treturn -1;\n+\t\t} else if (info->len0 > I40E_FIELD_LEN_MAX) {\n+\t\t\tPMD_DRV_LOG(ERR, \"len0 (0x%x) exceeds the maximum \"\n+\t\t\t\t\"of 0x%x\\n\", info->len0, I40E_FIELD_LEN_MAX);\n+\t\t\treturn -1;\n+\t\t} else if (info->off1_src0 > I40E_FIELD_OFFSET_MAX) {\n+\t\t\tPMD_DRV_LOG(ERR, \"off1_src0 (0x%x) exceeds the \"\n+\t\t\t\t\"maximum of 0x%x\\n\", info->off1_src0,\n+\t\t\t\t\t\tI40E_FIELD_OFFSET_MAX);\n+\t\t\treturn -1;\n+\t\t} else if (info->off1_src1 > I40E_FIELD_OFFSET_MAX) {\n+\t\t\tPMD_DRV_LOG(ERR, \"off1_src1 (0x%x) exceeds the \"\n+\t\t\t\t\"maximum of 0x%x\\n\", info->off1_src1,\n+\t\t\t\t\t\tI40E_FIELD_OFFSET_MAX);\n+\t\t\treturn -1;\n+\t\t} else if (info->len1 > I40E_FIELD_LEN_MAX) {\n+\t\t\tPMD_DRV_LOG(ERR, \"len1 (0x%x) exceeds the maximum \"\n+\t\t\t\t\"of 0x%x\\n\", info->len1, I40E_FIELD_LEN_MAX);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\t/**\n+\t\t * The offset and length given in byte unit, which need to be\n+\t\t * converted in word unit before being written to the register,\n+\t\t * as hardware requires it in word unit.\n+\t\t */\n+\t\treg = (info->off0_src0 >> 1) << I40E_GLQF_SWAP_OFF0_SRC0_SHIFT;\n+\t\treg |= (info->off0_src1 >> 1) <<\n+\t\t\tI40E_GLQF_SWAP_OFF0_SRC1_SHIFT;\n+\t\treg |= (info->len0 >> 1) << I40E_GLQF_SWAP_FLEN0_SHIFT;\n+\t\treg |= (info->off1_src0 >> 1) <<\n+\t\t\tI40E_GLQF_SWAP_OFF1_SRC0_SHIFT;\n+\t\treg |= (info->off1_src1 >> 1) <<\n+\t\t\tI40E_GLQF_SWAP_OFF1_SRC1_SHIFT;\n+\t\treg |= (info->len1 >> 1) << I40E_GLQF_SWAP_FLEN1_SHIFT;\n+\t\tPMD_DRV_LOG(DEBUG, \"Value to be written to \"\n+\t\t\t\"I40E_GLQF_SWAP[0,%d]: 0x%x\\n\", info->pctype, reg);\n+\t\tI40E_WRITE_REG(hw, I40E_GLQF_SWAP(0, info->pctype), reg);\n+\t\tI40E_WRITE_FLUSH(hw);\n+\t\tbreak;\n+\tcase ETH_PCTYPE_FCOE_OX:\n+\tcase ETH_PCTYPE_FCOE_RX:\n+\tcase ETH_PCTYPE_FCOE_OTHER:\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"PCTYPE[%u] is out of supported range\\n\",\n+\t\t\t\t\t\t\tinfo->pctype);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)\n+{\n+\tuint32_t reg;\n+\n+\tif (!hw || !enable) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\treg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);\n+\t*enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)\n+{\n+\tuint32_t reg;\n+\n+\tif (!hw || !enable) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\treg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);\n+\tif (*enable > 0) {\n+\t\tif (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {\n+\t\t\tPMD_DRV_LOG(INFO, \"Symmetric hash has already \"\n+\t\t\t\t\t\t\"been enabled\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\t\treg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;\n+\t} else {\n+\t\tif (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {\n+\t\t\tPMD_DRV_LOG(INFO, \"Symmetric hash has already \"\n+\t\t\t\t\t\t\"been disabled\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\t\treg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;\n+\t}\n+\tI40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);\n+\tI40E_WRITE_FLUSH(hw);\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_get_symmetric_hash_enable_per_pctype(struct i40e_hw *hw,\n+\t\t\tstruct rte_i40e_sym_hash_enable_info *info)\n+{\n+\tuint32_t reg;\n+\n+\tif (!hw || !info) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tswitch (info->pctype) {\n+\tcase ETH_PCTYPE_NONF_IPV4_UDP:\n+\tcase ETH_PCTYPE_NONF_IPV4_TCP:\n+\tcase ETH_PCTYPE_NONF_IPV4_SCTP:\n+\tcase ETH_PCTYPE_NONF_IPV4_OTHER:\n+\tcase ETH_PCTYPE_FRAG_IPV4:\n+\tcase ETH_PCTYPE_NONF_IPV6_UDP:\n+\tcase ETH_PCTYPE_NONF_IPV6_TCP:\n+\tcase ETH_PCTYPE_NONF_IPV6_SCTP:\n+\tcase ETH_PCTYPE_NONF_IPV6_OTHER:\n+\tcase ETH_PCTYPE_FRAG_IPV6:\n+\tcase ETH_PCTYPE_L2_PAYLOAD:\n+\t\treg = I40E_READ_REG(hw, I40E_GLQF_HSYM(info->pctype));\n+\t\tbreak;\n+\tcase ETH_PCTYPE_FCOE_OX:\n+\tcase ETH_PCTYPE_FCOE_RX:\n+\tcase ETH_PCTYPE_FCOE_OTHER:\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"PCTYPE[%u] is out of supported range\\n\",\n+\t\t\t\t\t\t\tinfo->pctype);\n+\t\treturn -1;\n+\t}\n+\n+\tinfo->enable = reg & I40E_GLQF_HSYM_SYMH_ENA_MASK ? 1 : 0;\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_set_symmetric_hash_enable_per_pctype(struct i40e_hw *hw,\n+\t\t\tstruct rte_i40e_sym_hash_enable_info *info)\n+{\n+\tuint32_t reg;\n+\n+\tif (!hw || !info) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tswitch (info->pctype) {\n+\tcase ETH_PCTYPE_NONF_IPV4_UDP:\n+\tcase ETH_PCTYPE_NONF_IPV4_TCP:\n+\tcase ETH_PCTYPE_NONF_IPV4_SCTP:\n+\tcase ETH_PCTYPE_NONF_IPV4_OTHER:\n+\tcase ETH_PCTYPE_FRAG_IPV4:\n+\tcase ETH_PCTYPE_NONF_IPV6_UDP:\n+\tcase ETH_PCTYPE_NONF_IPV6_TCP:\n+\tcase ETH_PCTYPE_NONF_IPV6_SCTP:\n+\tcase ETH_PCTYPE_NONF_IPV6_OTHER:\n+\tcase ETH_PCTYPE_FRAG_IPV6:\n+\tcase ETH_PCTYPE_L2_PAYLOAD:\n+\t\treg = info->enable ? I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;\n+\t\tI40E_WRITE_REG(hw, I40E_GLQF_HSYM(info->pctype), reg);\n+\t\tI40E_WRITE_FLUSH(hw);\n+\t\tbreak;\n+\tcase ETH_PCTYPE_FCOE_OX:\n+\tcase ETH_PCTYPE_FCOE_RX:\n+\tcase ETH_PCTYPE_FCOE_OTHER:\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"PCTYPE[%u] is out of supported range\\n\",\n+\t\t\t\t\t\t\tinfo->pctype);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_set_hash_function(struct i40e_hw *hw, enum rte_i40e_hash_function *hf)\n+{\n+\tuint32_t reg;\n+\n+\tif (!hw || !hf) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\treg = I40E_READ_REG(hw, I40E_GLQF_CTL);\n+\tif (*hf == rte_i40e_hash_function_toeplitz) {\n+\t\tif (reg & I40E_GLQF_CTL_HTOEP_MASK) {\n+\t\t\tPMD_DRV_LOG(DEBUG, \"Hash function already set to \"\n+\t\t\t\t\t\t\t\"Toeplitz\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\t\treg |= I40E_GLQF_CTL_HTOEP_MASK;\n+\t} else if (*hf == rte_i40e_hash_function_simple_xor) {\n+\t\tif (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {\n+\t\t\tPMD_DRV_LOG(DEBUG, \"Hash function already set to \"\n+\t\t\t\t\t\t\t\"Simple XOR\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\t\treg &= ~I40E_GLQF_CTL_HTOEP_MASK;\n+\t} else {\n+\t\tPMD_DRV_LOG(ERR, \"Unknown hash function type\\n\");\n+\t\treturn -1;\n+\t}\n+\tPMD_DRV_LOG(INFO, \"Hash function set to %s\\n\",\n+\t\t(reg & I40E_GLQF_CTL_HTOEP_MASK) ? \"Toeplitz\" : \"Simple XOR\");\n+\tI40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);\n+\tI40E_WRITE_FLUSH(hw);\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_get_hash_function(struct i40e_hw *hw, enum rte_i40e_hash_function *hf)\n+{\n+\tuint32_t reg;\n+\n+\tif (!hw || !hf) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\treg = I40E_READ_REG(hw, I40E_GLQF_CTL);\n+\tif (reg & I40E_GLQF_CTL_HTOEP_MASK)\n+\t\t*hf = rte_i40e_hash_function_toeplitz;\n+\telse\n+\t\t*hf = rte_i40e_hash_function_simple_xor;\n+\n+\tPMD_DRV_LOG(INFO, \"Hash function is %s\\n\",\n+\t\t(reg & I40E_GLQF_CTL_HTOEP_MASK) ? \"Toeplitz\" : \"Simple XOR\");\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_rx_classification_filter_ctl(struct rte_eth_dev *dev,\n+\t\t\t\t  enum rte_eth_command cmd,\n+\t\t\t\t  void *args)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tint ret = 0;\n+\n+\tswitch (cmd) {\n+\tcase RTE_CMD_GET_SYM_HASH_ENABLE_PER_PCTYPE:\n+\t\tret = i40e_get_symmetric_hash_enable_per_pctype(hw,\n+\t\t\t(struct rte_i40e_sym_hash_enable_info *)args);\n+\t\tbreak;\n+\tcase RTE_CMD_SET_SYM_HASH_ENABLE_PER_PCTYPE:\n+\t\tret = i40e_set_symmetric_hash_enable_per_pctype(hw,\n+\t\t\t(struct rte_i40e_sym_hash_enable_info *)args);\n+\t\tbreak;\n+\tcase RTE_CMD_GET_SYM_HASH_ENABLE_PER_PORT:\n+\t\tret = i40e_get_symmetric_hash_enable_per_port(hw,\n+\t\t\t\t\t\t(uint8_t *)args);\n+\t\tbreak;\n+\tcase RTE_CMD_SET_SYM_HASH_ENABLE_PER_PORT:\n+\t\tret = i40e_set_symmetric_hash_enable_per_port(hw,\n+\t\t\t\t\t\t(uint8_t *)args);\n+\t\tbreak;\n+\tcase RTE_CMD_GET_FILTER_SWAP:\n+\t\tret = i40e_get_filter_swap(hw,\n+\t\t\t(struct rte_i40e_filter_swap_info *)args);\n+\t\tbreak;\n+\tcase RTE_CMD_SET_FILTER_SWAP:\n+\t\tret = i40e_set_filter_swap(hw,\n+\t\t\t(struct rte_i40e_filter_swap_info *)args);\n+\t\tbreak;\n+\tcase RTE_CMD_GET_HASH_FUNCTION:\n+\t\tret = i40e_get_hash_function(hw,\n+\t\t\t(enum rte_i40e_hash_function *)args);\n+\t\tbreak;\n+\tcase RTE_CMD_SET_HASH_FUNCTION:\n+\t\tret = i40e_set_hash_function(hw,\n+\t\t\t(enum rte_i40e_hash_function *)args);\n+\t\tbreak;\n+\tdefault:\n+\t\tret = -1;\n+\t\tPMD_DRV_LOG(ERR, \"Unknown command which is not \"\n+\t\t\t\t\t\"supported by i40e\\n\");\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\ndiff --git a/lib/librte_pmd_i40e/i40e_ethdev.h b/lib/librte_pmd_i40e/i40e_ethdev.h\nindex 64deef2..001201b 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.h\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.h\n@@ -34,6 +34,8 @@\n #ifndef _I40E_ETHDEV_H_\n #define _I40E_ETHDEV_H_\n \n+#include \"rte_i40e.h\"\n+\n #define I40E_AQ_LEN               32\n #define I40E_AQ_BUF_SZ            4096\n /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */\ndiff --git a/lib/librte_pmd_i40e/rte_i40e.h b/lib/librte_pmd_i40e/rte_i40e.h\nnew file mode 100644\nindex 0000000..041cbab\n--- /dev/null\n+++ b/lib/librte_pmd_i40e/rte_i40e.h\n@@ -0,0 +1,108 @@\n+/*-\n+ *   BSD LICENSE\n+ *\n+ *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+ *   All rights reserved.\n+ *\n+ *   Redistribution and use in source and binary forms, with or without\n+ *   modification, are permitted provided that the following conditions\n+ *   are met:\n+ *\n+ *     * Redistributions of source code must retain the above copyright\n+ *       notice, this list of conditions and the following disclaimer.\n+ *     * Redistributions in binary form must reproduce the above copyright\n+ *       notice, this list of conditions and the following disclaimer in\n+ *       the documentation and/or other materials provided with the\n+ *       distribution.\n+ *     * Neither the name of Intel Corporation nor the names of its\n+ *       contributors may be used to endorse or promote products derived\n+ *       from this software without specific prior written permission.\n+ *\n+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_I40E_H_\n+#define _RTE_I40E_H_\n+\n+/**\n+ * @file\n+ *\n+ * RTE I40E\n+ *\n+ * The I40E defines the commands and structures specifically for i40e hardware\n+ * features. As different types of NIC hardware may have different features,\n+ * they might not be common for all types of NIC hardwares. The commands and\n+ * structures can be used in applications directly together with generalized\n+ * APIs declared in rte_ethdev.h. The commands couldn't be supported by\n+ * non-i40e PMD.\n+ */\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/**\n+ * For commands:\n+ * 'RTE_CMD_GET_HASH_FUNCTION'\n+ * 'RTE_CMD_SET_HASH_FUNCTION'\n+ *\n+ * This enum indicates the possible hash functions of i40e.\n+ */\n+enum rte_i40e_hash_function {\n+\trte_i40e_hash_function_unknown = 0,\n+\trte_i40e_hash_function_toeplitz,\n+\trte_i40e_hash_function_simple_xor,\n+};\n+\n+/**\n+ * For commands:\n+ * 'RTE_CMD_GET_FILTER_SWAP'\n+ * 'RTE_CMD_SET_FILTER_SWAP'\n+ *\n+ * A structure used to get/set filter swap. All of the offsets and\n+ * length are defined in bytes.\n+ */\n+struct rte_i40e_filter_swap_info {\n+\t/**< Packet classification type, defined in rte_ethdev.h */\n+\tuint8_t pctype;\n+\t/**< Offset of the 1st field of the 1st couple to be swapped. */\n+\tuint8_t off0_src0;\n+\t/**< Offset of the 2nd field of the 1st couple to be swapped. */\n+\tuint8_t off0_src1;\n+\t/**< Field length of the first couple. */\n+\tuint8_t len0;\n+\t/**< Offset of the 1st field of the 2nd couple to be swapped. */\n+\tuint8_t off1_src0;\n+\t/**< Offset of the 2nd field of the 2nd couple to be swapped. */\n+\tuint8_t off1_src1;\n+\t/**< Field length of the second couple. */\n+\tuint8_t len1;\n+};\n+\n+/**\n+ * For commands:\n+ * 'RTE_CMD_GET_SYM_HASH_ENABLE_PER_PCTYPE'\n+ * 'RTE_CMD_SET_SYM_HASH_ENABLE_PER_PCTYPE'\n+ *\n+ * A structure used to set/get symmetric hash enable per pctype.\n+ */\n+struct rte_i40e_sym_hash_enable_info {\n+\tuint8_t pctype; /**< packet classification type */\n+\tuint8_t enable; /**< enable or disable flag */\n+};\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#endif /* _RTE_I40E_H_ */\n",
    "prefixes": [
        "dpdk-dev",
        "v2",
        "3/6"
    ]
}