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GET /api/patches/105780/?format=api
{ "id": 105780, "url": "https://patches.dpdk.org/api/patches/105780/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220113102718.3167282-1-jerinj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220113102718.3167282-1-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220113102718.3167282-1-jerinj@marvell.com", "date": "2022-01-13T10:27:17", "name": "[v2,1/2] ethdev: support queue-based priority flow control", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3aa9902e94537b99f96628003360f84284313cbc", "submitter": { "id": 1188, "url": "https://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220113102718.3167282-1-jerinj@marvell.com/mbox/", "series": [ { "id": 21154, "url": "https://patches.dpdk.org/api/series/21154/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=21154", "date": "2022-01-13T10:27:17", "name": "[v2,1/2] ethdev: support queue-based priority flow control", "version": 2, "mbox": "https://patches.dpdk.org/series/21154/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/105780/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/105780/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C31E3A0093;\n\tThu, 13 Jan 2022 11:28:10 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 487934271A;\n\tThu, 13 Jan 2022 11:28:10 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id A85FB40150\n for <dev@dpdk.org>; Thu, 13 Jan 2022 11:28:08 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 20DALJiD029839;\n Thu, 13 Jan 2022 02:27:35 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3djarn9kjy-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 13 Jan 2022 02:27:34 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 13 Jan 2022 02:27:32 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 13 Jan 2022 02:27:32 -0800", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n by maili.marvell.com (Postfix) with ESMTP id A0B643F7070;\n Thu, 13 Jan 2022 02:27:14 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=PFPcpxWJMrSpFgxu/LENm8F+Mn1DN9Lqp7aY10RBp74=;\n b=NdooVVwanNicieP4kBozIbkTgNdauQlYV30JHSk7SsDuzPdEbsImcc8iOkSeVqxCrBKX\n zcvIuwjotVxNS/ufFQUESwL2Slvmg6raiaLczKfnHRuBbckmVKcSIkYld5tGSd5QT9s5\n jcVki6AoBKrIdlZq7HhVWzJrTEFjsWyB3pxYgWx8LBrThgUlug5GmQjZrUVnX44ScAyx\n d47XuOiR2pMWbMfe/Uh0pGlcZPvwlXBZ81kDk1rpdHjwTnJpU4/1AkxgfdGihUqOCbkK\n 9NxBIyDpTK0SZqIfKB6RsTCnjn4qDxVzS8nqWBRWd75b8oiDeJz/jEHhec1H9d8MWiei kw==", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Ray Kinsella <mdr@ashroe.eu>, Thomas Monjalon\n <thomas@monjalon.net>, Ferruh Yigit <ferruh.yigit@intel.com>, \"Andrew\n Rybchenko\" <andrew.rybchenko@oktetlabs.ru>", "CC": "<ajit.khaparde@broadcom.com>, <aboyer@pensando.io>,\n <beilei.xing@intel.com>, <bruce.richardson@intel.com>, <chas3@att.com>,\n <chenbo.xia@intel.com>, <ciara.loftus@intel.com>,\n <dsinghrawat@marvell.com>, <ed.czeck@atomicrules.com>,\n <evgenys@amazon.com>, <grive@u256.net>, <g.singh@nxp.com>,\n <zhouguoyang@huawei.com>, <haiyue.wang@intel.com>,\n <hkalra@marvell.com>, <heinrich.kuhn@corigine.com>,\n <hemant.agrawal@nxp.com>, <hyonkim@cisco.com>, <igorch@amazon.com>,\n <irusskikh@marvell.com>, <jgrajcia@cisco.com>,\n <jasvinder.singh@intel.com>, <jianwang@trustnetic.com>,\n <jiawenwu@trustnetic.com>, <jingjing.wu@intel.com>,\n <johndale@cisco.com>, <john.miller@atomicrules.com>,\n <linville@tuxdriver.com>, <keith.wiles@intel.com>,\n <kirankumark@marvell.com>, <oulijun@huawei.com>, <lironh@marvell.com>,\n <longli@microsoft.com>, <mw@semihalf.com>, <spinler@cesnet.cz>,\n <matan@nvidia.com>, <matt.peters@windriver.com>,\n <maxime.coquelin@redhat.com>, <mk@semihalf.com>, <humin29@huawei.com>,\n <pnalla@marvell.com>, <ndabilpuram@marvell.com>,\n <qiming.yang@intel.com>, <qi.z.zhang@intel.com>, <radhac@marvell.com>,\n <rahul.lakkireddy@chelsio.com>, <rmody@marvell.com>,\n <rosen.xu@intel.com>, <sachin.saxena@oss.nxp.com>,\n <skoteshwar@marvell.com>, <shshaikh@marvell.com>,\n <shaibran@amazon.com>, <shepard.siegel@atomicrules.com>,\n <asomalap@amd.com>, <somnath.kotur@broadcom.com>,\n <sthemmin@microsoft.com>, <steven.webster@windriver.com>,\n <skori@marvell.com>, <mtetsuyah@gmail.com>, <vburru@marvell.com>,\n <viacheslavo@nvidia.com>, <xiao.w.wang@intel.com>,\n <cloud.wangxiaoyun@huawei.com>, <yisen.zhuang@huawei.com>,\n <yongwang@vmware.com>, <xuanziyang2@huawei.com>, Jerin Jacob\n <jerinj@marvell.com>", "Subject": "[dpdk-dev] [PATCH v2 1/2] ethdev: support queue-based priority flow\n control", "Date": "Thu, 13 Jan 2022 15:57:17 +0530", "Message-ID": "<20220113102718.3167282-1-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20220109105851.734687-1-skori@marvell.com>", "References": "<20220109105851.734687-1-skori@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "vu6WZvhuvW8dnUveif_nMFkAt5VAkL1h", "X-Proofpoint-ORIG-GUID": "vu6WZvhuvW8dnUveif_nMFkAt5VAkL1h", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2022-01-13_02,2022-01-13_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nBased on device support and use-case need, there are two different ways\nto enable PFC. The first case is the port level PFC configuration, in\nthis case, rte_eth_dev_priority_flow_ctrl_set() API shall be used to\nconfigure the PFC, and PFC frames will be generated using based on VLAN\nTC value.\n\nThe second case is the queue level PFC configuration, in this\ncase, Any packet field content can be used to steer the packet to the\nspecific queue using rte_flow or RSS and then use\nrte_eth_dev_priority_flow_ctrl_queue_set() to set the TC mapping on each\nqueue. Based on congestion selected on the specific queue, configured TC\nshall be used to generate PFC frames.\n\nOperation of these modes are mutually exclusive, when driver sets\nnon zero value for rte_eth_dev_info::pfc_queue_tc_max,\napplication must use queue level PFC configuration via\nrte_eth_dev_priority_flow_ctrl_queue_set() API instead of port level\nPFC configuration via rte_eth_dev_priority_flow_ctrl_set() API to\nrealize PFC configuration.\n\nThis patch enables the configuration for second case a.k.a queue\nbased PFC also updates rte_eth_dev_priority_flow_ctrl_set()\nimplmentaion to adheher to rte_eth_dev_info::pfc_queue_tc_max\nhandling.\n\nAlso updated libabigail.abignore to ignore the update\nto reserved fields in rte_eth_dev_info.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n\nA driver implemtion based on this API is at\nhttps://patches.dpdk.org/project/dpdk/patch/20220111081831.881374-1-skori@marvell.com/\n\nRFC..v1\n - Added queue based PFC config API instead port based\n\nv1..v2\n- Updated libabigail.ignore as\n has_data_member_inserted_between = {offset_of(reserved_64s), end}\n- Updated doxygen comments of rte_eth_pfc_queue_conf\n\n\n devtools/libabigail.abignore | 5 ++\n doc/guides/nics/features.rst | 5 +-\n doc/guides/rel_notes/release_22_03.rst | 3 +\n lib/ethdev/ethdev_driver.h | 6 +-\n lib/ethdev/rte_ethdev.c | 109 +++++++++++++++++++++++++\n lib/ethdev/rte_ethdev.h | 83 ++++++++++++++++++-\n lib/ethdev/version.map | 3 +\n 7 files changed, 208 insertions(+), 6 deletions(-)", "diff": "diff --git a/devtools/libabigail.abignore b/devtools/libabigail.abignore\nindex 4b676f317d..3bdecaaef0 100644\n--- a/devtools/libabigail.abignore\n+++ b/devtools/libabigail.abignore\n@@ -11,3 +11,8 @@\n ; Ignore generated PMD information strings\n [suppress_variable]\n name_regexp = _pmd_info$\n+\n+;Ignore fields inserted in place of reserved fields of rte_eth_dev_info\n+[suppress_type]\n+ name = rte_eth_dev_info\n+ has_data_member_inserted_between = {offset_of(reserved_64s), end}\ndiff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst\nindex 27be2d2576..277a784f4e 100644\n--- a/doc/guides/nics/features.rst\n+++ b/doc/guides/nics/features.rst\n@@ -379,9 +379,10 @@ Flow control\n Supports configuring link flow control.\n \n * **[implements] eth_dev_ops**: ``flow_ctrl_get``, ``flow_ctrl_set``,\n- ``priority_flow_ctrl_set``.\n+ ``priority_flow_ctrl_set``, ``priority_flow_ctrl_queue_set``.\n * **[related] API**: ``rte_eth_dev_flow_ctrl_get()``, ``rte_eth_dev_flow_ctrl_set()``,\n- ``rte_eth_dev_priority_flow_ctrl_set()``.\n+ ``rte_eth_dev_priority_flow_ctrl_set()``, ``rte_eth_dev_priority_flow_ctrl_queue_set()``.\n+* **[provides] rte_eth_dev_info**: ``pfc_queue_tc_max``.\n \n \n .. _nic_features_rate_limitation:\ndiff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst\nindex 6d99d1eaa9..b75c0356e6 100644\n--- a/doc/guides/rel_notes/release_22_03.rst\n+++ b/doc/guides/rel_notes/release_22_03.rst\n@@ -55,6 +55,9 @@ New Features\n Also, make sure to start the actual text at the margin.\n =======================================================\n \n+* **Added an API to enable queue based priority flow ctrl(PFC).**\n+\n+ A new API, ``rte_eth_dev_priority_flow_ctrl_queue_set()``, was added.\n \n Removed Items\n -------------\ndiff --git a/lib/ethdev/ethdev_driver.h b/lib/ethdev/ethdev_driver.h\nindex d95605a355..e0bbfe89d7 100644\n--- a/lib/ethdev/ethdev_driver.h\n+++ b/lib/ethdev/ethdev_driver.h\n@@ -532,6 +532,9 @@ typedef int (*flow_ctrl_set_t)(struct rte_eth_dev *dev,\n /** @internal Setup priority flow control parameter on an Ethernet device. */\n typedef int (*priority_flow_ctrl_set_t)(struct rte_eth_dev *dev,\n \t\t\t\tstruct rte_eth_pfc_conf *pfc_conf);\n+/** @internal Queue setup for priority flow control parameter on an Ethernet device. */\n+typedef int (*priority_flow_ctrl_queue_set_t)(struct rte_eth_dev *dev,\n+\t\t\t\tstruct rte_eth_pfc_queue_conf *pfc_queue_conf);\n \n /** @internal Update RSS redirection table on an Ethernet device. */\n typedef int (*reta_update_t)(struct rte_eth_dev *dev,\n@@ -1080,7 +1083,8 @@ struct eth_dev_ops {\n \tflow_ctrl_set_t flow_ctrl_set; /**< Setup flow control */\n \t/** Setup priority flow control */\n \tpriority_flow_ctrl_set_t priority_flow_ctrl_set;\n-\n+\t/** Priority flow control queue setup */\n+\tpriority_flow_ctrl_queue_set_t priority_flow_ctrl_queue_set;\n \t/** Set Unicast Table Array */\n \teth_uc_hash_table_set_t uc_hash_table_set;\n \t/** Set Unicast hash bitmap */\ndiff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c\nindex a1d475a292..6def057720 100644\n--- a/lib/ethdev/rte_ethdev.c\n+++ b/lib/ethdev/rte_ethdev.c\n@@ -3998,7 +3998,9 @@ int\n rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id,\n \t\t\t\t struct rte_eth_pfc_conf *pfc_conf)\n {\n+\tstruct rte_eth_dev_info dev_info;\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n \tdev = &rte_eth_devices[port_id];\n@@ -4010,6 +4012,17 @@ rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id,\n \t\treturn -EINVAL;\n \t}\n \n+\tret = rte_eth_dev_info_get(port_id, &dev_info);\n+\tif (ret != 0)\n+\t\treturn ret;\n+\n+\tif (dev_info.pfc_queue_tc_max != 0) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Ethdev port %u driver does not support port level PFC config\\n\",\n+\t\t\tport_id);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \tif (pfc_conf->priority > (RTE_ETH_DCB_NUM_USER_PRIORITIES - 1)) {\n \t\tRTE_ETHDEV_LOG(ERR, \"Invalid priority, only 0-7 allowed\\n\");\n \t\treturn -EINVAL;\n@@ -4022,6 +4035,102 @@ rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id,\n \treturn -ENOTSUP;\n }\n \n+static inline int\n+validate_rx_pause_config(struct rte_eth_dev_info *dev_info,\n+\t\t\t struct rte_eth_pfc_queue_conf *pfc_queue_conf)\n+{\n+\tif ((pfc_queue_conf->mode == RTE_ETH_FC_RX_PAUSE) ||\n+\t (pfc_queue_conf->mode == RTE_ETH_FC_FULL)) {\n+\t\tif (pfc_queue_conf->rx_pause.tx_qid >= dev_info->nb_tx_queues) {\n+\t\t\tRTE_ETHDEV_LOG(ERR, \"Tx queue not in range for Rx pause\"\n+\t\t\t\t \" (requested: %d configured: %d)\\n\",\n+\t\t\t\t pfc_queue_conf->rx_pause.tx_qid,\n+\t\t\t\t dev_info->nb_tx_queues);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tif (pfc_queue_conf->rx_pause.tc >= dev_info->pfc_queue_tc_max) {\n+\t\t\tRTE_ETHDEV_LOG(ERR, \"TC not in range for Rx pause\"\n+\t\t\t\t \" (requested: %d max: %d)\\n\",\n+\t\t\t\t pfc_queue_conf->rx_pause.tc,\n+\t\t\t\t dev_info->pfc_queue_tc_max);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static inline int\n+validate_tx_pause_config(struct rte_eth_dev_info *dev_info,\n+\t\t\t struct rte_eth_pfc_queue_conf *pfc_queue_conf)\n+{\n+\tif ((pfc_queue_conf->mode == RTE_ETH_FC_TX_PAUSE) ||\n+\t (pfc_queue_conf->mode == RTE_ETH_FC_FULL)) {\n+\t\tif (pfc_queue_conf->tx_pause.rx_qid >= dev_info->nb_rx_queues) {\n+\t\t\tRTE_ETHDEV_LOG(ERR, \"Rx queue not in range for Tx pause\"\n+\t\t\t\t \"(requested: %d configured: %d)\\n\",\n+\t\t\t\t pfc_queue_conf->tx_pause.rx_qid,\n+\t\t\t\t dev_info->nb_rx_queues);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tif (pfc_queue_conf->tx_pause.tc >= dev_info->pfc_queue_tc_max) {\n+\t\t\tRTE_ETHDEV_LOG(ERR, \"TC not in range for Tx pause\"\n+\t\t\t\t \"(requested: %d max: %d)\\n\",\n+\t\t\t\t pfc_queue_conf->tx_pause.tc,\n+\t\t\t\t dev_info->pfc_queue_tc_max);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+rte_eth_dev_priority_flow_ctrl_queue_set(\n+\tuint16_t port_id, struct rte_eth_pfc_queue_conf *pfc_queue_conf)\n+{\n+\tstruct rte_eth_dev_info dev_info;\n+\tstruct rte_eth_dev *dev;\n+\tint ret;\n+\n+\tRTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n+\tdev = &rte_eth_devices[port_id];\n+\n+\tif (pfc_queue_conf == NULL) {\n+\t\tRTE_ETHDEV_LOG(ERR, \"PFC parameters are NULL for port (%u)\\n\",\n+\t\t\t port_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = rte_eth_dev_info_get(port_id, &dev_info);\n+\tif (ret != 0)\n+\t\treturn ret;\n+\n+\tif (dev_info.pfc_queue_tc_max == 0) {\n+\t\tRTE_ETHDEV_LOG(ERR,\n+\t\t\t\"Ethdev port %u does not support PFC TC values\\n\",\n+\t\t\tport_id);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tret = validate_rx_pause_config(&dev_info, pfc_queue_conf);\n+\tif (ret != 0)\n+\t\treturn ret;\n+\n+\tret = validate_tx_pause_config(&dev_info, pfc_queue_conf);\n+\tif (ret != 0)\n+\t\treturn ret;\n+\n+\n+\tif (*dev->dev_ops->priority_flow_ctrl_queue_set)\n+\t\treturn eth_err(port_id,\n+\t\t\t (*dev->dev_ops->priority_flow_ctrl_queue_set)(\n+\t\t\t\t dev, pfc_queue_conf));\n+\treturn -ENOTSUP;\n+}\n+\n static int\n eth_check_reta_mask(struct rte_eth_rss_reta_entry64 *reta_conf,\n \t\t\tuint16_t reta_size)\ndiff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h\nindex fa299c8ad7..33e43f6e1d 100644\n--- a/lib/ethdev/rte_ethdev.h\n+++ b/lib/ethdev/rte_ethdev.h\n@@ -1395,6 +1395,28 @@ struct rte_eth_pfc_conf {\n \tuint8_t priority; /**< VLAN User Priority. */\n };\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * A structure used to configure Ethernet priority flow control parameter for\n+ * ethdev queues.\n+ */\n+struct rte_eth_pfc_queue_conf {\n+\tenum rte_eth_fc_mode mode; /**< Link flow control mode */\n+\n+\tstruct {\n+\t\tuint16_t tx_qid; /**< Tx queue ID */\n+\t\tuint8_t tc; /**< Traffic class as per PFC (802.1Qbb) spec */\n+\t} rx_pause; /* Valid when (mode == FC_RX_PAUSE || mode == FC_FULL) */\n+\n+\tstruct {\n+\t\tuint16_t pause_time; /**< Pause quota in the Pause frame */\n+\t\tuint16_t rx_qid; /**< Rx queue ID */\n+\t\tuint8_t tc; /**< Traffic class as per PFC (802.1Qbb) spec */\n+\t} tx_pause; /* Valid when (mode == FC_TX_PAUSE || mode == FC_FULL) */\n+};\n+\n /**\n * Tunnel type for device-specific classifier configuration.\n * @see rte_eth_udp_tunnel\n@@ -1841,8 +1863,30 @@ struct rte_eth_dev_info {\n \t * embedded managed interconnect/switch.\n \t */\n \tstruct rte_eth_switch_info switch_info;\n-\n-\tuint64_t reserved_64s[2]; /**< Reserved for future fields */\n+\t/**\n+\t * Maximum supported traffic class as per PFC (802.1Qbb) specification.\n+\t *\n+\t * Based on device support and use-case need, there are two different\n+\t * ways to enable PFC. The first case is the port level PFC\n+\t * configuration, in this case, rte_eth_dev_priority_flow_ctrl_set()\n+\t * API shall be used to configure the PFC, and PFC frames will be\n+\t * generated using based on VLAN TC value.\n+\t * The second case is the queue level PFC configuration, in this case,\n+\t * Any packet field content can be used to steer the packet to the\n+\t * specific queue using rte_flow or RSS and then use\n+\t * rte_eth_dev_priority_flow_ctrl_queue_set() to set the TC mapping\n+\t * on each queue. Based on congestion selected on the specific queue,\n+\t * configured TC shall be used to generate PFC frames.\n+\t *\n+\t * When set to non zero value, application must use queue level\n+\t * PFC configuration via rte_eth_dev_priority_flow_ctrl_queue_set() API\n+\t * instead of port level PFC configuration via\n+\t * rte_eth_dev_priority_flow_ctrl_set() API to realize\n+\t * PFC configuration.\n+\t */\n+\tuint8_t pfc_queue_tc_max;\n+\tuint8_t reserved_8s[7];\n+\tuint64_t reserved_64s[1]; /**< Reserved for future fields */\n \tvoid *reserved_ptrs[2]; /**< Reserved for future fields */\n };\n \n@@ -4109,6 +4153,9 @@ int rte_eth_dev_flow_ctrl_set(uint16_t port_id,\n * Configure the Ethernet priority flow control under DCB environment\n * for Ethernet device.\n *\n+ * @see struct rte_eth_dev_info::pfc_queue_tc_max priority\n+ * flow control usage models.\n+ *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param pfc_conf\n@@ -4119,10 +4166,40 @@ int rte_eth_dev_flow_ctrl_set(uint16_t port_id,\n * - (-ENODEV) if *port_id* invalid.\n * - (-EINVAL) if bad parameter\n * - (-EIO) if flow control setup failure or device is removed.\n+ *\n */\n int rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id,\n-\t\t\t\tstruct rte_eth_pfc_conf *pfc_conf);\n+\t\t\t\t struct rte_eth_pfc_conf *pfc_conf);\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Configure the Ethernet priority flow control for a given queue\n+ * for Ethernet device.\n+ *\n+ * @see struct rte_eth_dev_info::pfc_queue_tc_max priority flow control\n+ * usage models.\n+ *\n+ * @note When an ethdev port switches to PFC mode, the unconfigured\n+ * queues shall be configured by the driver with default values such as\n+ * lower priority value for TC etc.\n+ *\n+ * @param port_id\n+ * The port identifier of the Ethernet device.\n+ * @param pfc_queue_conf\n+ * The pointer to the structure of the priority flow control parameters\n+ * for the queue.\n+ * @return\n+ * - (0) if successful.\n+ * - (-ENOTSUP) if hardware doesn't support priority flow control mode.\n+ * - (-ENODEV) if *port_id* invalid.\n+ * - (-EINVAL) if bad parameter\n+ * - (-EIO) if flow control setup queue failure\n+ */\n+__rte_experimental\n+int rte_eth_dev_priority_flow_ctrl_queue_set(uint16_t port_id,\n+\t\t\t\t\t struct rte_eth_pfc_queue_conf *pfc_queue_conf);\n /**\n * Add a MAC address to the set used for filtering incoming packets.\n *\ndiff --git a/lib/ethdev/version.map b/lib/ethdev/version.map\nindex c2fb0669a4..8f361ec15a 100644\n--- a/lib/ethdev/version.map\n+++ b/lib/ethdev/version.map\n@@ -256,6 +256,9 @@ EXPERIMENTAL {\n \trte_flow_flex_item_create;\n \trte_flow_flex_item_release;\n \trte_flow_pick_transfer_proxy;\n+\n+\t# added in 22.03\n+\trte_eth_dev_priority_flow_ctrl_queue_set;\n };\n \n INTERNAL {\n", "prefixes": [ "v2", "1/2" ] }