Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/105637/?format=api
{ "id": 105637, "url": "https://patches.dpdk.org/api/patches/105637/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20220105140020.1615256-2-tduszynski@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220105140020.1615256-2-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220105140020.1615256-2-tduszynski@marvell.com", "date": "2022-01-05T14:00:10", "name": "[v4,01/11] raw/cnxk_gpio: add GPIO driver skeleton", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "91f978833164621120a89eecbcf4ea98c319acb1", "submitter": { "id": 2215, "url": "https://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20220105140020.1615256-2-tduszynski@marvell.com/mbox/", "series": [ { "id": 21073, "url": "https://patches.dpdk.org/api/series/21073/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=21073", "date": "2022-01-05T14:00:09", "name": "Add cnxk_gpio", "version": 4, "mbox": "https://patches.dpdk.org/series/21073/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/105637/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/105637/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2D917A034D;\n\tWed, 5 Jan 2022 15:00:42 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id ECADA4114A;\n\tWed, 5 Jan 2022 15:00:33 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 546D841144\n for <dev@dpdk.org>; Wed, 5 Jan 2022 15:00:33 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 205BHCZB030856;\n Wed, 5 Jan 2022 06:00:29 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3dd214x100-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Wed, 05 Jan 2022 06:00:29 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 5 Jan 2022 06:00:27 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Wed, 5 Jan 2022 06:00:27 -0800", "from localhost.localdomain (unknown [10.28.34.39])\n by maili.marvell.com (Postfix) with ESMTP id 866483F709A;\n Wed, 5 Jan 2022 06:00:25 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=YwJ8K2in9T15mfg9NlhHu4ViZwIh8uzp75hD6Yk/8X4=;\n b=V8vTRGtfpoZtrg4YEsS2/8SmnwC9MlXyn8PZXLelqgvZ4lL8ppQHjCKgEd54EgIGn7Wf\n brYYVJPxSBJZAqXAd7ArDlpkP8X3zNa8L4sV82UxFepjJN7DbCBmlqzHVygu/5sexBEj\n Vh94TlU1RZnXgaQNvxejffkKNZh2TBX9fwADvCYqQ3EkR1VYx7qNGdszQt1nsJT7V2P7\n nBv8K0agPvK+AVxVakWtjcd3KEL3eLlZW6KfLCp/QGkdYsqA8xYWfPrnKufQQJo08Wwn\n 9/+pKCY4UVW8hcUgqWz6S3JXyB/ogteQFSrVmcJxLOAN9P+tbGQrEzQyxlcctTb7zNNS ew==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "<dev@dpdk.org>, Ray Kinsella <mdr@ashroe.eu>, Anatoly Burakov\n <anatoly.burakov@intel.com>", "CC": "<thomas@monjalon.net>, <jerinj@marvell.com>, Tomasz Duszynski\n <tduszynski@marvell.com>", "Subject": "[PATCH v4 01/11] raw/cnxk_gpio: add GPIO driver skeleton", "Date": "Wed, 5 Jan 2022 15:00:10 +0100", "Message-ID": "<20220105140020.1615256-2-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220105140020.1615256-1-tduszynski@marvell.com>", "References": "<20211213081732.2096334-1-tduszynski@marvell.com>\n <20220105140020.1615256-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "8mbilF_eOfsfG4snLZlN2ItkeBMXcMoV", "X-Proofpoint-ORIG-GUID": "8mbilF_eOfsfG4snLZlN2ItkeBMXcMoV", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2022-01-05_03,2022-01-04_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add initial support for PMD that allows to control particular pins form\nuserspace. Moreover PMD allows to attach custom interrupt handlers to\ncontrollable GPIOs.\n\nMain users of this PMD are dataplain applications requiring fast and low\nlatency access to pin state.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\n---\n doc/guides/rawdevs/cnxk_gpio.rst | 65 ++++++++\n doc/guides/rawdevs/index.rst | 1 +\n drivers/raw/cnxk_gpio/cnxk_gpio.c | 239 ++++++++++++++++++++++++++++++\n drivers/raw/cnxk_gpio/cnxk_gpio.h | 22 +++\n drivers/raw/cnxk_gpio/meson.build | 8 +\n drivers/raw/cnxk_gpio/version.map | 3 +\n drivers/raw/meson.build | 1 +\n 7 files changed, 339 insertions(+)\n create mode 100644 doc/guides/rawdevs/cnxk_gpio.rst\n create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio.c\n create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio.h\n create mode 100644 drivers/raw/cnxk_gpio/meson.build\n create mode 100644 drivers/raw/cnxk_gpio/version.map", "diff": "diff --git a/doc/guides/rawdevs/cnxk_gpio.rst b/doc/guides/rawdevs/cnxk_gpio.rst\nnew file mode 100644\nindex 0000000000..868302d07f\n--- /dev/null\n+++ b/doc/guides/rawdevs/cnxk_gpio.rst\n@@ -0,0 +1,65 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2021 Marvell.\n+\n+Marvell CNXK GPIO Driver\n+========================\n+\n+CNXK GPIO PMD configures and manages GPIOs available on the system using\n+standard enqueue/dequeue mechanism offered by raw device abstraction. PMD relies\n+both on standard sysfs GPIO interface provided by the Linux kernel and GPIO\n+kernel driver custom interface allowing one to install userspace interrupt\n+handlers.\n+\n+Features\n+--------\n+\n+Following features are available:\n+\n+- export/unexport a GPIO\n+- read/write specific value from/to exported GPIO\n+- set GPIO direction\n+- set GPIO edge that triggers interrupt\n+- set GPIO active low\n+- register interrupt handler for specific GPIO\n+\n+Requirements\n+------------\n+\n+PMD relies on modified kernel GPIO driver which exposes ``ioctl()`` interface\n+for installing interrupt handlers for low latency signal processing.\n+\n+Driver is shipped with Marvell SDK.\n+\n+Device Setup\n+------------\n+\n+CNXK GPIO PMD binds to virtual device which gets created by passing\n+`--vdev=cnxk_gpio,gpiochip=<number>` command line to EAL. `gpiochip` parameter\n+tells PMD which GPIO controller should be used. Available controllers are\n+available under `/sys/class/gpio`. For further details on how Linux represents\n+GPIOs in userspace please refer to\n+`sysfs.txt <https://www.kernel.org/doc/Documentation/gpio/sysfs.txt>`_.\n+\n+If `gpiochip=<number>` was omitted then first gpiochip from the alphabetically\n+sort list of available gpiochips is used.\n+\n+.. code-block:: console\n+\n+ $ ls /sys/class/gpio\n+ export gpiochip448 unexport\n+\n+In above scenario only one GPIO controller is present hence\n+`--vdev=cnxk_gpio,gpiochip=448` should be passed to EAL.\n+\n+Before performing actual data transfer one needs to call\n+``rte_rawdev_queue_count()`` followed by ``rte_rawdev_queue_conf_get()``. The\n+former returns number GPIOs available in the system irrespective of GPIOs\n+being controllable or not. Thus it is user responsibility to pick the proper\n+ones. The latter call simply returns queue capacity.\n+\n+Respective queue needs to be configured with ``rte_rawdev_queue_setup()``. This\n+call barely exports GPIO to userspace.\n+\n+To perform actual data transfer use standard ``rte_rawdev_enqueue_buffers()``\n+and ``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible\n+responses hence dequeueing is not always necessary.\ndiff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst\nindex b6cf917443..0c02da6e90 100644\n--- a/doc/guides/rawdevs/index.rst\n+++ b/doc/guides/rawdevs/index.rst\n@@ -12,6 +12,7 @@ application through rawdev API.\n :numbered:\n \n cnxk_bphy\n+ cnxk_gpio\n dpaa2_cmdif\n dpaa2_qdma\n ifpga\ndiff --git a/drivers/raw/cnxk_gpio/cnxk_gpio.c b/drivers/raw/cnxk_gpio/cnxk_gpio.c\nnew file mode 100644\nindex 0000000000..881615d62e\n--- /dev/null\n+++ b/drivers/raw/cnxk_gpio/cnxk_gpio.c\n@@ -0,0 +1,239 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include <dirent.h>\n+#include <string.h>\n+\n+#include <rte_bus_vdev.h>\n+#include <rte_eal.h>\n+#include <rte_kvargs.h>\n+#include <rte_lcore.h>\n+#include <rte_rawdev_pmd.h>\n+\n+#include <roc_api.h>\n+\n+#include \"cnxk_gpio.h\"\n+\n+#define CNXK_GPIO_BUFSZ 128\n+#define CNXK_GPIO_CLASS_PATH \"/sys/class/gpio\"\n+\n+static const char *const cnxk_gpio_args[] = {\n+#define CNXK_GPIO_ARG_GPIOCHIP \"gpiochip\"\n+\tCNXK_GPIO_ARG_GPIOCHIP,\n+\tNULL\n+};\n+\n+static void\n+cnxk_gpio_format_name(char *name, size_t len)\n+{\n+\tsnprintf(name, len, \"cnxk_gpio\");\n+}\n+\n+static int\n+cnxk_gpio_filter_gpiochip(const struct dirent *dirent)\n+{\n+\tconst char *pattern = \"gpiochip\";\n+\n+\treturn !strncmp(dirent->d_name, pattern, strlen(pattern));\n+}\n+\n+static void\n+cnxk_gpio_set_defaults(struct cnxk_gpiochip *gpiochip)\n+{\n+\tstruct dirent **namelist;\n+\tint n;\n+\n+\tn = scandir(CNXK_GPIO_CLASS_PATH, &namelist, cnxk_gpio_filter_gpiochip,\n+\t\t alphasort);\n+\tif (n < 0 || n == 0)\n+\t\treturn;\n+\n+\tsscanf(namelist[0]->d_name, \"gpiochip%d\", &gpiochip->num);\n+\twhile (n--)\n+\t\tfree(namelist[n]);\n+\tfree(namelist);\n+}\n+\n+static int\n+cnxk_gpio_parse_arg_gpiochip(const char *key __rte_unused, const char *value,\n+\t\t\t void *extra_args)\n+{\n+\tlong val;\n+\n+\terrno = 0;\n+\tval = strtol(value, NULL, 10);\n+\tif (errno)\n+\t\treturn -errno;\n+\n+\t*(int *)extra_args = (int)val;\n+\n+\treturn 0;\n+}\n+\n+static int\n+cnxk_gpio_parse_args(struct cnxk_gpiochip *gpiochip,\n+\t\t struct rte_devargs *devargs)\n+{\n+\tstruct rte_kvargs *kvlist;\n+\tint ret;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, cnxk_gpio_args);\n+\tif (!kvlist)\n+\t\treturn 0;\n+\n+\tret = rte_kvargs_count(kvlist, CNXK_GPIO_ARG_GPIOCHIP);\n+\tif (ret == 1) {\n+\t\tret = rte_kvargs_process(kvlist, CNXK_GPIO_ARG_GPIOCHIP,\n+\t\t\t\t\t cnxk_gpio_parse_arg_gpiochip,\n+\t\t\t\t\t &gpiochip->num);\n+\t\tif (ret)\n+\t\t\tgoto out;\n+\t}\n+\n+\tret = 0;\n+out:\n+\trte_kvargs_free(kvlist);\n+\n+\treturn ret;\n+}\n+\n+static int\n+cnxk_gpio_read_attr(char *attr, char *val)\n+{\n+\tFILE *fp;\n+\tint ret;\n+\n+\tfp = fopen(attr, \"r\");\n+\tif (!fp)\n+\t\treturn -errno;\n+\n+\tret = fscanf(fp, \"%s\", val);\n+\tif (ret < 0)\n+\t\treturn -errno;\n+\tif (ret != 1)\n+\t\treturn -EIO;\n+\n+\tret = fclose(fp);\n+\tif (ret)\n+\t\treturn -errno;\n+\n+\treturn 0;\n+}\n+\n+static int\n+cnxk_gpio_read_attr_int(char *attr, int *val)\n+{\n+\tchar buf[CNXK_GPIO_BUFSZ];\n+\tint ret;\n+\n+\tret = cnxk_gpio_read_attr(attr, buf);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = sscanf(buf, \"%d\", val);\n+\tif (ret < 0)\n+\t\treturn -errno;\n+\n+\treturn 0;\n+}\n+\n+static const struct rte_rawdev_ops cnxk_gpio_rawdev_ops = {\n+};\n+\n+static int\n+cnxk_gpio_probe(struct rte_vdev_device *dev)\n+{\n+\tchar name[RTE_RAWDEV_NAME_MAX_LEN];\n+\tstruct cnxk_gpiochip *gpiochip;\n+\tstruct rte_rawdev *rawdev;\n+\tchar buf[CNXK_GPIO_BUFSZ];\n+\tint ret;\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tcnxk_gpio_format_name(name, sizeof(name));\n+\trawdev = rte_rawdev_pmd_allocate(name, sizeof(*gpiochip),\n+\t\t\t\t\t rte_socket_id());\n+\tif (!rawdev) {\n+\t\tRTE_LOG(ERR, PMD, \"failed to allocate %s rawdev\", name);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\trawdev->dev_ops = &cnxk_gpio_rawdev_ops;\n+\trawdev->device = &dev->device;\n+\trawdev->driver_name = dev->device.name;\n+\n+\tgpiochip = rawdev->dev_private;\n+\tcnxk_gpio_set_defaults(gpiochip);\n+\n+\t/* defaults may be overwritten by this call */\n+\tret = cnxk_gpio_parse_args(gpiochip, dev->device.devargs);\n+\tif (ret)\n+\t\tgoto out;\n+\n+\t/* read gpio base */\n+\tsnprintf(buf, sizeof(buf), \"%s/gpiochip%d/base\", CNXK_GPIO_CLASS_PATH,\n+\t\t gpiochip->num);\n+\tret = cnxk_gpio_read_attr_int(buf, &gpiochip->base);\n+\tif (ret) {\n+\t\tRTE_LOG(ERR, PMD, \"failed to read %s\", buf);\n+\t\tgoto out;\n+\t}\n+\n+\t/* read number of available gpios */\n+\tsnprintf(buf, sizeof(buf), \"%s/gpiochip%d/ngpio\", CNXK_GPIO_CLASS_PATH,\n+\t\t gpiochip->num);\n+\tret = cnxk_gpio_read_attr_int(buf, &gpiochip->num_gpios);\n+\tif (ret) {\n+\t\tRTE_LOG(ERR, PMD, \"failed to read %s\", buf);\n+\t\tgoto out;\n+\t}\n+\n+\tgpiochip->gpios = rte_calloc(NULL, gpiochip->num_gpios,\n+\t\t\t\t sizeof(struct cnxk_gpio *), 0);\n+\tif (!gpiochip->gpios) {\n+\t\tRTE_LOG(ERR, PMD, \"failed to allocate gpios memory\");\n+\t\tret = -ENOMEM;\n+\t\tgoto out;\n+\t}\n+\n+\treturn 0;\n+out:\n+\trte_rawdev_pmd_release(rawdev);\n+\n+\treturn ret;\n+}\n+\n+static int\n+cnxk_gpio_remove(struct rte_vdev_device *dev)\n+{\n+\tchar name[RTE_RAWDEV_NAME_MAX_LEN];\n+\tstruct cnxk_gpiochip *gpiochip;\n+\tstruct rte_rawdev *rawdev;\n+\n+\tRTE_SET_USED(dev);\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tcnxk_gpio_format_name(name, sizeof(name));\n+\trawdev = rte_rawdev_pmd_get_named_dev(name);\n+\tif (!rawdev)\n+\t\treturn -ENODEV;\n+\n+\tgpiochip = rawdev->dev_private;\n+\trte_free(gpiochip->gpios);\n+\trte_rawdev_pmd_release(rawdev);\n+\n+\treturn 0;\n+}\n+\n+static struct rte_vdev_driver cnxk_gpio_drv = {\n+\t.probe = cnxk_gpio_probe,\n+\t.remove = cnxk_gpio_remove,\n+};\n+\n+RTE_PMD_REGISTER_VDEV(cnxk_gpio, cnxk_gpio_drv);\n+RTE_PMD_REGISTER_PARAM_STRING(cnxk_gpio, \"gpiochip=<int>\");\ndiff --git a/drivers/raw/cnxk_gpio/cnxk_gpio.h b/drivers/raw/cnxk_gpio/cnxk_gpio.h\nnew file mode 100644\nindex 0000000000..4dae8316ba\n--- /dev/null\n+++ b/drivers/raw/cnxk_gpio/cnxk_gpio.h\n@@ -0,0 +1,22 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _CNXK_GPIO_H_\n+#define _CNXK_GPIO_H_\n+\n+struct cnxk_gpiochip;\n+\n+struct cnxk_gpio {\n+\tstruct cnxk_gpiochip *gpiochip;\n+\tint num;\n+};\n+\n+struct cnxk_gpiochip {\n+\tint num;\n+\tint base;\n+\tint num_gpios;\n+\tstruct cnxk_gpio **gpios;\n+};\n+\n+#endif /* _CNXK_GPIO_H_ */\ndiff --git a/drivers/raw/cnxk_gpio/meson.build b/drivers/raw/cnxk_gpio/meson.build\nnew file mode 100644\nindex 0000000000..9a7e716c1e\n--- /dev/null\n+++ b/drivers/raw/cnxk_gpio/meson.build\n@@ -0,0 +1,8 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(C) 2021 Marvell.\n+#\n+\n+deps += ['bus_vdev', 'common_cnxk', 'rawdev', 'kvargs']\n+sources = files(\n+ 'cnxk_gpio.c',\n+)\ndiff --git a/drivers/raw/cnxk_gpio/version.map b/drivers/raw/cnxk_gpio/version.map\nnew file mode 100644\nindex 0000000000..4a76d1d52d\n--- /dev/null\n+++ b/drivers/raw/cnxk_gpio/version.map\n@@ -0,0 +1,3 @@\n+DPDK_21 {\n+\tlocal: *;\n+};\ndiff --git a/drivers/raw/meson.build b/drivers/raw/meson.build\nindex 87694a758e..05e7de1bfe 100644\n--- a/drivers/raw/meson.build\n+++ b/drivers/raw/meson.build\n@@ -7,6 +7,7 @@ endif\n \n drivers = [\n 'cnxk_bphy',\n+ 'cnxk_gpio',\n 'dpaa2_cmdif',\n 'dpaa2_qdma',\n 'ifpga',\n", "prefixes": [ "v4", "01/11" ] }