Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/103991/?format=api
{ "id": 103991, "url": "https://patches.dpdk.org/api/patches/103991/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211108123354.2194-4-rzidane@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211108123354.2194-4-rzidane@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211108123354.2194-4-rzidane@nvidia.com", "date": "2021-11-08T12:33:53", "name": "[V2,3/4] crypto/mlx5: fix the queue size configuration", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8ed81ad5a21317a4a431fa804f0ac40677283051", "submitter": { "id": 2300, "url": "https://patches.dpdk.org/api/people/2300/?format=api", "name": "Raja Zidane", "email": "rzidane@nvidia.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211108123354.2194-4-rzidane@nvidia.com/mbox/", "series": [ { "id": 20386, "url": "https://patches.dpdk.org/api/series/20386/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=20386", "date": "2021-11-08T12:33:50", "name": "fixes to queue size config", "version": 2, "mbox": "https://patches.dpdk.org/series/20386/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/103991/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/103991/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 80AD7A0C4D;\n\tMon, 8 Nov 2021 13:34:46 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C31A641150;\n\tMon, 8 Nov 2021 13:34:29 +0100 (CET)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2062.outbound.protection.outlook.com [40.107.243.62])\n by mails.dpdk.org (Postfix) with ESMTP id 85BD341149;\n Mon, 8 Nov 2021 13:34:26 +0100 (CET)", "from BN6PR17CA0010.namprd17.prod.outlook.com (2603:10b6:404:65::20)\n by MN2PR12MB4173.namprd12.prod.outlook.com (2603:10b6:208:1d8::10)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.13; Mon, 8 Nov\n 2021 12:34:24 +0000", "from BN8NAM11FT004.eop-nam11.prod.protection.outlook.com\n (2603:10b6:404:65:cafe::1b) by BN6PR17CA0010.outlook.office365.com\n (2603:10b6:404:65::20) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.13 via Frontend\n Transport; Mon, 8 Nov 2021 12:34:24 +0000", "from mail.nvidia.com (216.228.112.34) by\n BN8NAM11FT004.mail.protection.outlook.com (10.13.176.164) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4669.10 via Frontend Transport; Mon, 8 Nov 2021 12:34:23 +0000", "from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 8 Nov\n 2021 12:34:14 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=I5CC8nPZox/jHIL3tlZBeDnW5KqBnMHjrXAalgA/0fE15P09wpFi7OOfCvrqSg37Hupk3AfYZKxo/LhOT51gK6e8PDxh+kzP3Na35yG9X5oHC/9zxQXm5/fZcOpJ+d+KOffEuzYxjFFkK5U+pYKBtgSoKisIdJ1wcDtMsDPpqpCFNn+bWVSGL4cz5nMiUzQT744jakDQikcm9y0YL510XEVszaj00gG8FXe6sQ+kZnix1oW/7l9p7mmt8kCbB7f76ZtxDgqH3aVDS4ZJf+3HZerwRNfJ8Jk6Vsvmj+VeoRD6wqhD3N7qr7HZd2GSHFTU/Hbf2pqRwbWioYyg/8FtQg==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=7HFoZu2z49U2xbwlfxJMWUEnDpFXlBR5vDC1yG98n+A=;\n b=X7roE/A40kdhIgW2+Au/w+l7kCC9fJ30+Drf7izjKUJuJL+M03QvMuizYqPSfi0jdwX0++8PEiQukLo8ku8r+UWFRIMsHbSQefIdzjflqdXYrKgnKRJWU0m7NKx4lLdXpTq1pfqE+W1OqJqeyIQcHEfXM5ImxLjLVf98A1yiYeT1pcyHkXGWuyU6X5e/WjZg0SBUPLGeuBh1I3lQYww/ZK47GmebaSDLLwVSUfwiuQEU09tenPp6GcXaxxjvatzj74yEc1t+Tmo9CkglZFZR9rKfhQIZifqIVZNRHoGjgS9jykIZn10GtH2w7DH8ZASwOvD9T7N8YVOiq/bmWVqOVg==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=quarantine pct=100) action=none\n header.from=nvidia.com; dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=7HFoZu2z49U2xbwlfxJMWUEnDpFXlBR5vDC1yG98n+A=;\n b=LWcZExoxmPj03QaMXzROhgQufCevYTUCzWQtnAdTaFfbmOgCKevwnWj31SNP/P2ywoMTPYk/vghzTVcKuetiKWfar2lnDBXpA9P90VrFp/S8mOysREk/mKbmnOj4O2QKN+hRKJwszHnhLs65QIpmTUy9rg7Eb+sIpKnCx0y0013l/WHZBj7VsUXZJFh7ErTBi4m0Orxbe4KLymgno/A6rLFP/EFmFUZjzMBsB3vPGVWo/Dza9DWHhmo+gK52Vz4EKeteicr768DafKBCs9RgGVXls/HwnLjrqZbxeo+U/tP+vtZTlivFRjQfONkIr+VlTh5ArotDRP5Ec/qOiVRJ4w==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Raja Zidane <rzidane@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, <stable@dpdk.org>", "Date": "Mon, 8 Nov 2021 12:33:53 +0000", "Message-ID": "<20211108123354.2194-4-rzidane@nvidia.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20211108123354.2194-1-rzidane@nvidia.com>", "References": "<20211104124929.24899-1-rzidane@nvidia.com>\n <20211108123354.2194-1-rzidane@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "400586cf-85d8-471a-18ec-08d9a2b4186f", "X-MS-TrafficTypeDiagnostic": "MN2PR12MB4173:", "X-Microsoft-Antispam-PRVS": "\n <MN2PR12MB4173D6C749E4E6157E9A31A8C7919@MN2PR12MB4173.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:4941;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n T/oF2ZFUgPuHzMVQFQ6qWxaVNCX+bWUQGXCtiF8wVerPlGJyGBo55/WVjc4MgIdRxINYkKIiLVdSrds42eR2R90lhqgK1qL0qj4nHzmc+LAfWJo9mbMsmOfX299lpL/t+dgYv+wwwN8DUmiyQHFC9k/YrSMWY5VY0Det0pV6cXglYSAGqDGH7nBRA7yWqJkBpyfo5mwIhiHJWUdHssSHwwC/1WhjX6VR+keK5es4BUr8yYTRsjh/MyH7iSE+L2r1lcxvBI2eClVT+aQsfdMf6fe/7hZu6tgrlV7doc6jjNwn4s8MYiiPJ3ap4Yp5tCL5Fth31Qx8f/Fcckzgdmhz4nSOozoRbqN3IvYCrseK/3cGF6QT2jVAFd0x8QJQqCBu0coo1ux9P7zkXpH88nTcVVLftvgThZNbUMYhqTGIpPgwdSwyuLzMo3DwnWYMj4JPjyhHoOK4n6ntn5I0IJ7vSBjINguSjr3uTnvriXzS4wflA8+791UCxghy/7kY3WQXdWBs6d4a73Qpzpe1csne/F3K/LUfQgB2SQHD8V6UqIxkpoozuQMdUEqL35TQtJrzvk7O54FhLxmzEkarITiwgLA4s7gpK/4fuBVqmFE/9pM+gYUNG5Gpc2xJQSXaQMWGCgli0CzAy9eLEFqazCJqWCWfGfjDvI0GbHT/nmPtDnkadXvfEJAXOsviaCv3iEbYL0oVANHA6SppTilJI2MgHw==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(26005)(6286002)(7696005)(450100002)(55016002)(54906003)(70206006)(336012)(7636003)(6916009)(5660300002)(83380400001)(36860700001)(16526019)(4326008)(186003)(8676002)(6666004)(47076005)(30864003)(82310400003)(86362001)(356005)(2906002)(426003)(1076003)(2616005)(316002)(8936002)(70586007)(508600001)(36756003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Nov 2021 12:34:23.5713 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 400586cf-85d8-471a-18ec-08d9a2b4186f", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT004.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4173", "Subject": "[dpdk-dev] [PATCH V2 3/4] crypto/mlx5: fix the queue size\n configuration", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The DevX interface for QP creation expects the number of WQEBBs.\nWrongly, the number of descriptors was provided to the QP creation.\nIn addition, the QP size must be a power of 2 what was not guaranteed.\nProvide the number of WQEBBs to the QP creation API.\nRound up the SQ size to a power of 2.\nRename (sq/rq)_size to num_of_(send/receive)_wqes.\n\nFixes: 6152534e211e (\"crypto/mlx5: support queue pairs operations\")\nCc: stable@dpdk.org\n\nSigned-off-by: Raja Zidane <rzidane@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 14 +--\n drivers/common/mlx5/mlx5_devx_cmds.h | 5 +-\n drivers/compress/mlx5/mlx5_compress.c | 4 +-\n drivers/crypto/mlx5/mlx5_crypto.c | 120 +++++++++++++++++++-----\n drivers/crypto/mlx5/mlx5_crypto.h | 7 ++\n drivers/regex/mlx5/mlx5_regex_control.c | 4 +-\n drivers/vdpa/mlx5/mlx5_vdpa_event.c | 4 +-\n 7 files changed, 120 insertions(+), 38 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex cecbf541f6..e52b995ee3 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -832,6 +832,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t\tMLX5_HCA_CAP_OPMOD_GET_CUR);\n \tif (!hcattr)\n \t\treturn rc;\n+\tattr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq);\n \tattr->flow_counter_bulk_alloc_bitmap =\n \t\t\tMLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);\n \tattr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,\n@@ -2153,21 +2154,22 @@ mlx5_devx_cmd_create_qp(void *ctx,\n \t\tif (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)\n \t\t\tMLX5_SET(qpc, qpc, log_page_size,\n \t\t\t\t attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);\n-\t\tif (attr->sq_size) {\n-\t\t\tMLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));\n+\t\tif (attr->num_of_send_wqbbs) {\n+\t\t\tMLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs));\n \t\t\tMLX5_SET(qpc, qpc, cqn_snd, attr->cqn);\n \t\t\tMLX5_SET(qpc, qpc, log_sq_size,\n-\t\t\t\t rte_log2_u32(attr->sq_size));\n+\t\t\t\t rte_log2_u32(attr->num_of_send_wqbbs));\n \t\t} else {\n \t\t\tMLX5_SET(qpc, qpc, no_sq, 1);\n \t\t}\n-\t\tif (attr->rq_size) {\n-\t\t\tMLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));\n+\t\tif (attr->num_of_receive_wqes) {\n+\t\t\tMLX5_ASSERT(RTE_IS_POWER_OF_2(\n+\t\t\t\t\tattr->num_of_receive_wqes));\n \t\t\tMLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);\n \t\t\tMLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -\n \t\t\t\t MLX5_LOG_RQ_STRIDE_SHIFT);\n \t\t\tMLX5_SET(qpc, qpc, log_rq_size,\n-\t\t\t\t rte_log2_u32(attr->rq_size));\n+\t\t\t\t rte_log2_u32(attr->num_of_receive_wqes));\n \t\t\tMLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);\n \t\t} else {\n \t\t\tMLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 447f76f1f9..d7f71646a3 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -251,6 +251,7 @@ struct mlx5_hca_attr {\n \tuint32_t log_max_mmo_decompress:5;\n \tuint32_t umr_modify_entity_size_disabled:1;\n \tuint32_t umr_indirect_mkey_disabled:1;\n+\tuint16_t max_wqe_sz_sq;\n };\n \n /* LAG Context. */\n@@ -477,9 +478,9 @@ struct mlx5_devx_qp_attr {\n \tuint32_t uar_index:24;\n \tuint32_t cqn:24;\n \tuint32_t log_page_size:5;\n-\tuint32_t rq_size:17; /* Must be power of 2. */\n+\tuint32_t num_of_receive_wqes:17; /* Must be power of 2. */\n \tuint32_t log_rq_stride:3;\n-\tuint32_t sq_size:17; /* Must be power of 2. */\n+\tuint32_t num_of_send_wqbbs:17; /* Must be power of 2. */\n \tuint32_t ts_format:2;\n \tuint32_t dbr_umem_valid:1;\n \tuint32_t dbr_umem_id;\ndiff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex d5511aebdf..7813af38e6 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -244,8 +244,8 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \tqp_attr.cqn = qp->cq.cq->id;\n \tqp_attr.ts_format =\n \t\tmlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);\n-\tqp_attr.rq_size = 0;\n-\tqp_attr.sq_size = RTE_BIT32(log_ops_n);\n+\tqp_attr.num_of_receive_wqes = 0;\n+\tqp_attr.num_of_send_wqbbs = RTE_BIT32(log_ops_n);\n \tqp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp\n \t\t\t&& priv->mmo_dma_qp;\n \tret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, log_ops_n, &qp_attr,\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 1d0f1f3cfc..55208a87eb 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -545,7 +545,7 @@ mlx5_crypto_qp_init(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp)\n \t\tucseg->if_cf_toe_cq_res = RTE_BE32(1u << MLX5_UMRC_IF_OFFSET);\n \t\tucseg->mkey_mask = RTE_BE64(1u << 0); /* Mkey length bit. */\n \t\tucseg->ko_to_bs = rte_cpu_to_be_32\n-\t\t\t((RTE_ALIGN(priv->max_segs_num, 4u) <<\n+\t\t\t((MLX5_CRYPTO_KLM_SEGS_NUM(priv->umr_wqe_size) <<\n \t\t\t MLX5_UMRC_KO_OFFSET) | (4 << MLX5_UMRC_TO_BS_OFFSET));\n \t\tbsf->keytag = priv->keytag;\n \t\t/* Init RDMA WRITE WQE. */\n@@ -569,7 +569,7 @@ mlx5_crypto_indirect_mkeys_prepare(struct mlx5_crypto_priv *priv,\n \t\t.umr_en = 1,\n \t\t.crypto_en = 1,\n \t\t.set_remote_rw = 1,\n-\t\t.klm_num = RTE_ALIGN(priv->max_segs_num, 4),\n+\t\t.klm_num = MLX5_CRYPTO_KLM_SEGS_NUM(priv->umr_wqe_size),\n \t};\n \n \tfor (umr = (struct mlx5_umr_wqe *)qp->qp_obj.umem_buf, i = 0;\n@@ -597,6 +597,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \tuint16_t log_nb_desc = rte_log2_u32(qp_conf->nb_descriptors);\n \tuint32_t ret;\n \tuint32_t alloc_size = sizeof(*qp);\n+\tuint32_t log_wqbb_n;\n \tstruct mlx5_devx_cq_attr cq_attr = {\n \t\t.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar.obj),\n \t};\n@@ -619,14 +620,16 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n \t\tgoto error;\n \t}\n+\tlog_wqbb_n = rte_log2_u32(RTE_BIT32(log_nb_desc) *\n+\t\t\t\t(priv->wqe_set_size / MLX5_SEND_WQE_BB));\n \tattr.pd = priv->cdev->pdn;\n \tattr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar.obj);\n \tattr.cqn = qp->cq_obj.cq->id;\n-\tattr.rq_size = 0;\n-\tattr.sq_size = RTE_BIT32(log_nb_desc);\n+\tattr.num_of_receive_wqes = 0;\n+\tattr.num_of_send_wqbbs = RTE_BIT32(log_wqbb_n);\n \tattr.ts_format =\n \t\tmlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);\n-\tret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp_obj, log_nb_desc,\n+\tret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp_obj, log_wqbb_n,\n \t\t\t\t &attr, socket_id);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Failed to create QP.\");\n@@ -747,10 +750,8 @@ mlx5_crypto_args_check_handler(const char *key, const char *val, void *opaque)\n \t\treturn -errno;\n \t}\n \tif (strcmp(key, \"max_segs_num\") == 0) {\n-\t\tif (!tmp || tmp > MLX5_CRYPTO_MAX_SEGS) {\n-\t\t\tDRV_LOG(WARNING, \"Invalid max_segs_num: %d, should\"\n-\t\t\t\t\" be less than %d.\",\n-\t\t\t\t(uint32_t)tmp, MLX5_CRYPTO_MAX_SEGS);\n+\t\tif (!tmp) {\n+\t\t\tDRV_LOG(ERR, \"max_segs_num must be greater than 0.\");\n \t\t\trte_errno = EINVAL;\n \t\t\treturn -rte_errno;\n \t\t}\n@@ -809,6 +810,81 @@ mlx5_crypto_parse_devargs(struct rte_devargs *devargs,\n \treturn 0;\n }\n \n+/*\n+ * Calculate UMR WQE size and RDMA Write WQE size with the\n+ * following limitations:\n+ *\t- Each WQE size is multiple of 64.\n+ *\t- The summarize of both UMR WQE and RDMA_W WQE is a power of 2.\n+ *\t- The number of entries in the UMR WQE's KLM list is multiple of 4.\n+ */\n+static void\n+mlx5_crypto_get_wqe_sizes(uint32_t segs_num, uint32_t *umr_size,\n+\t\t\tuint32_t *rdmaw_size)\n+{\n+\tuint32_t diff, wqe_set_size;\n+\n+\t*umr_size = MLX5_CRYPTO_UMR_WQE_STATIC_SIZE +\n+\t\t\tRTE_ALIGN(segs_num, 4) *\n+\t\t\tsizeof(struct mlx5_wqe_dseg);\n+\t/* Make sure UMR WQE size is multiple of WQBB. */\n+\t*umr_size = RTE_ALIGN(*umr_size, MLX5_SEND_WQE_BB);\n+\t*rdmaw_size = sizeof(struct mlx5_rdma_write_wqe) +\n+\t\t\tsizeof(struct mlx5_wqe_dseg) *\n+\t\t\t(segs_num <= 2 ? 2 : 2 +\n+\t\t\tRTE_ALIGN(segs_num - 2, 4));\n+\t/* Make sure RDMA_WRITE WQE size is multiple of WQBB. */\n+\t*rdmaw_size = RTE_ALIGN(*rdmaw_size, MLX5_SEND_WQE_BB);\n+\twqe_set_size = *rdmaw_size + *umr_size;\n+\tdiff = rte_align32pow2(wqe_set_size) - wqe_set_size;\n+\t/* Make sure wqe_set size is power of 2. */\n+\tif (diff)\n+\t\t*umr_size += diff;\n+}\n+\n+static uint8_t\n+mlx5_crypto_max_segs_num(uint16_t max_wqe_size)\n+{\n+\tint klms_sizes = max_wqe_size - MLX5_CRYPTO_UMR_WQE_STATIC_SIZE;\n+\tuint32_t max_segs_cap = RTE_ALIGN_FLOOR(klms_sizes, MLX5_SEND_WQE_BB) /\n+\t\t\tsizeof(struct mlx5_wqe_dseg);\n+\n+\tMLX5_ASSERT(klms_sizes >= MLX5_SEND_WQE_BB);\n+\twhile (max_segs_cap) {\n+\t\tuint32_t umr_wqe_size, rdmw_wqe_size;\n+\n+\t\tmlx5_crypto_get_wqe_sizes(max_segs_cap, &umr_wqe_size,\n+\t\t\t\t\t\t&rdmw_wqe_size);\n+\t\tif (umr_wqe_size <= max_wqe_size &&\n+\t\t\t\trdmw_wqe_size <= max_wqe_size)\n+\t\t\tbreak;\n+\t\tmax_segs_cap -= 4;\n+\t}\n+\treturn max_segs_cap;\n+}\n+\n+static int\n+mlx5_crypto_configure_wqe_size(struct mlx5_crypto_priv *priv,\n+\t\t\t\tuint16_t max_wqe_size, uint32_t max_segs_num)\n+{\n+\tuint32_t rdmw_wqe_size, umr_wqe_size;\n+\n+\tmlx5_crypto_get_wqe_sizes(max_segs_num, &umr_wqe_size,\n+\t\t\t\t\t&rdmw_wqe_size);\n+\tpriv->wqe_set_size = rdmw_wqe_size + umr_wqe_size;\n+\tif (umr_wqe_size > max_wqe_size ||\n+\t\t\t\trdmw_wqe_size > max_wqe_size) {\n+\t\tDRV_LOG(ERR, \"Invalid max_segs_num: %u. should be %u or lower.\",\n+\t\t\tmax_segs_num,\n+\t\t\tmlx5_crypto_max_segs_num(max_wqe_size));\n+\t\trte_errno = EINVAL;\n+\t\treturn -EINVAL;\n+\t}\n+\tpriv->umr_wqe_size = (uint16_t)umr_wqe_size;\n+\tpriv->umr_wqe_stride = priv->umr_wqe_size / MLX5_SEND_WQE_BB;\n+\tpriv->max_rdmar_ds = rdmw_wqe_size / sizeof(struct mlx5_wqe_dseg);\n+\treturn 0;\n+}\n+\n static int\n mlx5_crypto_dev_probe(struct mlx5_common_device *cdev)\n {\n@@ -824,7 +900,6 @@ mlx5_crypto_dev_probe(struct mlx5_common_device *cdev)\n \t\t\t\tRTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS,\n \t};\n \tconst char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx);\n-\tuint16_t rdmw_wqe_size;\n \tint ret;\n \n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n@@ -873,20 +948,17 @@ mlx5_crypto_dev_probe(struct mlx5_common_device *cdev)\n \t}\n \tpriv->login_obj = login;\n \tpriv->keytag = rte_cpu_to_be_64(devarg_prms.keytag);\n-\tpriv->max_segs_num = devarg_prms.max_segs_num;\n-\tpriv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) +\n-\t\t\t sizeof(struct mlx5_wqe_cseg) +\n-\t\t\t sizeof(struct mlx5_wqe_umr_cseg) +\n-\t\t\t sizeof(struct mlx5_wqe_mkey_cseg) +\n-\t\t\t RTE_ALIGN(priv->max_segs_num, 4) *\n-\t\t\t sizeof(struct mlx5_wqe_dseg);\n-\trdmw_wqe_size = sizeof(struct mlx5_rdma_write_wqe) +\n-\t\t\t sizeof(struct mlx5_wqe_dseg) *\n-\t\t\t (priv->max_segs_num <= 2 ? 2 : 2 +\n-\t\t\t RTE_ALIGN(priv->max_segs_num - 2, 4));\n-\tpriv->wqe_set_size = priv->umr_wqe_size + rdmw_wqe_size;\n-\tpriv->umr_wqe_stride = priv->umr_wqe_size / MLX5_SEND_WQE_BB;\n-\tpriv->max_rdmar_ds = rdmw_wqe_size / sizeof(struct mlx5_wqe_dseg);\n+\tret = mlx5_crypto_configure_wqe_size(priv,\n+\t\tcdev->config.hca_attr.max_wqe_sz_sq, devarg_prms.max_segs_num);\n+\tif (ret) {\n+\t\tmlx5_crypto_uar_release(priv);\n+\t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n+\t\treturn -1;\n+\t}\n+\tDRV_LOG(INFO, \"Max number of segments: %u.\",\n+\t\t(unsigned int)RTE_MIN(\n+\t\t\tMLX5_CRYPTO_KLM_SEGS_NUM(priv->umr_wqe_size),\n+\t\t\t(uint16_t)(priv->max_rdmar_ds - 2)));\n \tpthread_mutex_lock(&priv_list_lock);\n \tTAILQ_INSERT_TAIL(&mlx5_crypto_priv_list, priv, next);\n \tpthread_mutex_unlock(&priv_list_lock);\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 135cd78212..f04b3d8c20 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -16,6 +16,13 @@\n \n #define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11)\n #define MLX5_CRYPTO_KEY_LENGTH 80\n+#define MLX5_CRYPTO_UMR_WQE_STATIC_SIZE (sizeof(struct mlx5_wqe_cseg) +\\\n+\t\t\t\t\tsizeof(struct mlx5_wqe_umr_cseg) +\\\n+\t\t\t\t\tsizeof(struct mlx5_wqe_mkey_cseg) +\\\n+\t\t\t\t\tsizeof(struct mlx5_wqe_umr_bsf_seg))\n+#define MLX5_CRYPTO_KLM_SEGS_NUM(umr_wqe_sz) ((umr_wqe_sz -\\\n+\t\t\t\t\tMLX5_CRYPTO_UMR_WQE_STATIC_SIZE) /\\\n+\t\t\t\t\tMLX5_WSEG_SIZE)\n \n struct mlx5_crypto_priv {\n \tTAILQ_ENTRY(mlx5_crypto_priv) next;\ndiff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c\nindex d184b1a921..46e400a93f 100644\n--- a/drivers/regex/mlx5/mlx5_regex_control.c\n+++ b/drivers/regex/mlx5/mlx5_regex_control.c\n@@ -149,8 +149,8 @@ regex_ctrl_create_hw_qp(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,\n \tqp_obj->qpn = q_ind;\n \tqp_obj->ci = 0;\n \tqp_obj->pi = 0;\n-\tattr.rq_size = 0;\n-\tattr.sq_size = RTE_BIT32(MLX5_REGEX_WQE_LOG_NUM(priv->has_umr,\n+\tattr.num_of_receive_wqes = 0;\n+\tattr.num_of_send_wqbbs = RTE_BIT32(MLX5_REGEX_WQE_LOG_NUM(priv->has_umr,\n \t\t\tlog_nb_desc));\n \tattr.mmo = priv->mmo_regex_qp_cap;\n \tret = mlx5_devx_qp_create(priv->cdev->ctx, &qp_obj->qp_obj,\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\nindex 9cc71714a2..657c39dae1 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n@@ -589,9 +589,9 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,\n \t}\n \tattr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar.obj);\n \tattr.cqn = eqp->cq.cq_obj.cq->id;\n-\tattr.rq_size = RTE_BIT32(log_desc_n);\n+\tattr.num_of_receive_wqes = RTE_BIT32(log_desc_n);\n \tattr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);\n-\tattr.sq_size = 0; /* No need SQ. */\n+\tattr.num_of_send_wqbbs = 0; /* No need SQ. */\n \tattr.ts_format =\n \t\tmlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);\n \tret = mlx5_devx_qp_create(priv->cdev->ctx, &(eqp->sw_qp), log_desc_n,\n", "prefixes": [ "V2", "3/4" ] }