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GET /api/patches/103875/?format=api
{ "id": 103875, "url": "https://patches.dpdk.org/api/patches/103875/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211105142814.183067-3-bingz@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211105142814.183067-3-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211105142814.183067-3-bingz@nvidia.com", "date": "2021-11-05T14:28:14", "name": "[v6,2/2] net/mlx5: check delay drop settings in kernel driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cc9bf420d5af69d0b48561dd3030c5cb9d45ca0a", "submitter": { "id": 1976, "url": "https://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211105142814.183067-3-bingz@nvidia.com/mbox/", "series": [ { "id": 20346, "url": "https://patches.dpdk.org/api/series/20346/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=20346", "date": "2021-11-05T14:28:12", "name": "Add delay drop support for Rx queue", "version": 6, "mbox": "https://patches.dpdk.org/series/20346/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/103875/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/103875/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B57C0A0C4B;\n\tFri, 5 Nov 2021 15:28:47 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5A53F426D4;\n\tFri, 5 Nov 2021 15:28:39 +0100 (CET)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2040.outbound.protection.outlook.com [40.107.94.40])\n by mails.dpdk.org (Postfix) with ESMTP id 8987B426D3\n for <dev@dpdk.org>; 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mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=quarantine pct=100) action=none\n header.from=nvidia.com; dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=HrJtYVbrVSLhwZGQMqpHVryOHOLSma80FcMYPLBUlUs=;\n b=Andfqm8d2pPHjVCrV78quETVe4tqbjz4uVofv37IWcNIScEPammKTWVnl4ZKa46TOad6g5GXobZ95oe6lBrB8aYJdFOCAZ3Pz4v8MkS0YMLcwteIC29xBnJzvKKYvuKpnmOOqI/GNIB+j3L6rFksW1qteTWa6ouYu02eN1AqWPqEVPdf/W6v3C7L02wy5NE0F9jqcIeg5HHjk3dLxQDIKvrbe93v+5oadxYbl4xVaMBTs0HWtq2HB363/6LuAS6i7p7bwA84qpIrryrjvjtCf++dZ6qdFoQQxtjm8sg1OG/zEEq9WDgvEshBlHzwdOADYkNAENzQDbUQ5YqinXKPoA==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed)\n header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>, <thomas@monjalon.net>,\n <orika@nvidia.com>", "Date": "Fri, 5 Nov 2021 16:28:14 +0200", "Message-ID": "<20211105142814.183067-3-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20211105142814.183067-1-bingz@nvidia.com>", "References": "<20211104112644.17278-1-bingz@nvidia.com>\n <20211105142814.183067-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "2d53dfde-f179-4456-bba1-08d9a0688cc0", "X-MS-TrafficTypeDiagnostic": "BYAPR12MB2728:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BYAPR12MB2728ED2A8671C3371D9783B9D08E9@BYAPR12MB2728.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:5797;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Lnp5JiiNPMf09wlp442UK8WGo9QeF7IV4M7wtheqxdDGRh/ZczXWXjMl06BIgezy//mE9/3xY9LSXB2UDyxVBHqerERFcGRCj31kKqXDGPoF3bgfNScF4PNpm2fbtrjUUX2T8HD8nMSg+OCZ3pow8GVFGOCbbwszbmt6MEGKEhfubca4MDj6/EPNKWjl7KTuxtesrl6h4Sdz5Qsx+7qSqJ0hZyrUNU0Ij4AFhjpVijF2nk6fHJ9bvB2nozW9kW6WaLDr5mX4Vwi6V8XX8XjpRrwWM6Tk/YVLMxJeUn17iNCIsanK/HyyS1amKs2iEPu7Lcv3DMqjMX32sRSV4VrDRlXm3bUVkvbGDWVKC4ROERnbm3+9CKgumUxtdVARr/bVDxrrL6Aizxu6gqUwpsgjzFu1sNaUQ699PRO1URbwaUdtg4x4C19fTWegMse1aFlFhQ0F6zijtg7euCJ7bbo9nLp6YBuaa1Gmf+Q2CqvFSW8PSOZJYdfFpaFkdWc/g9ILJ+bhjNZU0UY9PC2T9Ohh9WhpEZj5yc29bHu6lpkaqR3c7Ab97ShwiMpZF936gkSBLcbNMThwLmeSk49Qhve1QTtbHBdRpuaYUVA6HP12RwSgUTmlLR0+HCFyOeaz6LH8xKSds7HRhZ8HI2YDeTFMU5hX5mT0eb9XcDPyXIG0MoX9PUrPHN1iJdKVOSZf0DZcE1lksw2fhpKkCKrOWRRQwQ==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(7696005)(82310400003)(186003)(70586007)(55016002)(8676002)(4326008)(6286002)(2616005)(426003)(8936002)(86362001)(36756003)(36860700001)(1076003)(5660300002)(508600001)(2906002)(16526019)(70206006)(336012)(316002)(83380400001)(107886003)(110136005)(47076005)(356005)(6666004)(6636002)(26005)(7636003)(54906003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 Nov 2021 14:28:34.6950 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2d53dfde-f179-4456-bba1-08d9a0688cc0", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT027.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR12MB2728", "Subject": "[dpdk-dev] [PATCH v6 2/2] net/mlx5: check delay drop settings in\n kernel driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The delay drop is the common feature managed on per device basis\nand the kernel driver is responsible one for the initialization and\nrearming.\n\nBy default, the timeout value is set to activate the delay drop when\nthe driver is loaded.\n\nA private flag \"dropless_rq\" is used to control the rearming. Only\nwhen it is on, the rearming will be handled once received a timeout\nevent. Or else, the delay drop will be deactivated after the first\ntimeout occurs and all the Rx queues won't have this feature.\n\nThe PMD is trying to query this flag and warn the application when\nsome queues are created with delay drop but the flag is off.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_ethdev_os.c | 111 ++++++++++++++++++++++\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_trigger.c | 18 ++++\n drivers/net/mlx5/windows/mlx5_ethdev_os.c | 17 ++++\n 4 files changed, 147 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c\nindex 9d0e491d0c..c19825ee52 100644\n--- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c\n@@ -1630,3 +1630,114 @@ mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN])\n \tmemcpy(mac, request.ifr_hwaddr.sa_data, RTE_ETHER_ADDR_LEN);\n \treturn 0;\n }\n+\n+/*\n+ * Query dropless_rq private flag value provided by ETHTOOL.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ *\n+ * @return\n+ * - 0 on success, flag is not set.\n+ * - 1 on success, flag is set.\n+ * - negative errno value otherwise and rte_errno is set.\n+ */\n+int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev)\n+{\n+\tstruct {\n+\t\tstruct ethtool_sset_info hdr;\n+\t\tuint32_t buf[1];\n+\t} sset_info;\n+\tstruct ethtool_drvinfo drvinfo;\n+\tstruct ifreq ifr;\n+\tstruct ethtool_gstrings *strings = NULL;\n+\tstruct ethtool_value flags;\n+\tconst int32_t flag_len = sizeof(flags.data) * CHAR_BIT;\n+\tint32_t str_sz;\n+\tint32_t len;\n+\tint32_t i;\n+\tint ret;\n+\n+\tsset_info.hdr.cmd = ETHTOOL_GSSET_INFO;\n+\tsset_info.hdr.reserved = 0;\n+\tsset_info.hdr.sset_mask = 1ULL << ETH_SS_PRIV_FLAGS;\n+\tifr.ifr_data = (caddr_t)&sset_info;\n+\tret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);\n+\tif (!ret) {\n+\t\tconst uint32_t *sset_lengths = sset_info.hdr.data;\n+\n+\t\tlen = sset_info.hdr.sset_mask ? sset_lengths[0] : 0;\n+\t} else if (ret == -EOPNOTSUPP) {\n+\t\tdrvinfo.cmd = ETHTOOL_GDRVINFO;\n+\t\tifr.ifr_data = (caddr_t)&drvinfo;\n+\t\tret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(WARNING, \"port %u cannot get the driver info\",\n+\t\t\t\tdev->data->port_id);\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tlen = *(uint32_t *)((char *)&drvinfo +\n+\t\t\toffsetof(struct ethtool_drvinfo, n_priv_flags));\n+\t} else {\n+\t\tDRV_LOG(WARNING, \"port %u cannot get the sset info\",\n+\t\t\tdev->data->port_id);\n+\t\tgoto exit;\n+\t}\n+\tif (!len) {\n+\t\tDRV_LOG(WARNING, \"port %u does not have private flag\",\n+\t\t\tdev->data->port_id);\n+\t\trte_errno = EOPNOTSUPP;\n+\t\tret = -rte_errno;\n+\t\tgoto exit;\n+\t} else if (len > flag_len) {\n+\t\tDRV_LOG(WARNING, \"port %u maximal private flags number is %d\",\n+\t\t\tdev->data->port_id, flag_len);\n+\t\tlen = flag_len;\n+\t}\n+\tstr_sz = ETH_GSTRING_LEN * len;\n+\tstrings = (struct ethtool_gstrings *)\n+\t\t mlx5_malloc(0, str_sz + sizeof(struct ethtool_gstrings), 0,\n+\t\t\t SOCKET_ID_ANY);\n+\tif (!strings) {\n+\t\tDRV_LOG(WARNING, \"port %u unable to allocate memory for\"\n+\t\t\t\" private flags\", dev->data->port_id);\n+\t\trte_errno = ENOMEM;\n+\t\tret = -rte_errno;\n+\t\tgoto exit;\n+\t}\n+\tstrings->cmd = ETHTOOL_GSTRINGS;\n+\tstrings->string_set = ETH_SS_PRIV_FLAGS;\n+\tstrings->len = len;\n+\tifr.ifr_data = (caddr_t)strings;\n+\tret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);\n+\tif (ret) {\n+\t\tDRV_LOG(WARNING, \"port %u unable to get private flags strings\",\n+\t\t\tdev->data->port_id);\n+\t\tgoto exit;\n+\t}\n+\tfor (i = 0; i < len; i++) {\n+\t\tstrings->data[(i + 1) * ETH_GSTRING_LEN - 1] = 0;\n+\t\tif (!strcmp((const char *)strings->data + i * ETH_GSTRING_LEN,\n+\t\t\t \"dropless_rq\"))\n+\t\t\tbreak;\n+\t}\n+\tif (i == len) {\n+\t\tDRV_LOG(WARNING, \"port %u does not support dropless_rq\",\n+\t\t\tdev->data->port_id);\n+\t\trte_errno = EOPNOTSUPP;\n+\t\tret = -rte_errno;\n+\t\tgoto exit;\n+\t}\n+\tflags.cmd = ETHTOOL_GPFLAGS;\n+\tifr.ifr_data = (caddr_t)&flags;\n+\tret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);\n+\tif (ret) {\n+\t\tDRV_LOG(WARNING, \"port %u unable to get private flags status\",\n+\t\t\tdev->data->port_id);\n+\t\tgoto exit;\n+\t}\n+\tret = !!(flags.data & (1U << i));\n+exit:\n+\tmlx5_free(strings);\n+\treturn ret;\n+}\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex b2022f3300..9307a4f95b 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1602,6 +1602,7 @@ int mlx5_os_read_dev_stat(struct mlx5_priv *priv,\n int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats);\n int mlx5_os_get_stats_n(struct rte_eth_dev *dev);\n void mlx5_os_stats_init(struct rte_eth_dev *dev);\n+int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev);\n \n /* mlx5_mac.c */\n \ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex a3e62e9533..0ecc530043 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -1129,6 +1129,24 @@ mlx5_dev_start(struct rte_eth_dev *dev)\n \t\t\tdev->data->port_id, strerror(rte_errno));\n \t\tgoto error;\n \t}\n+\tif (priv->config.std_delay_drop || priv->config.hp_delay_drop) {\n+\t\tif (!priv->config.vf && !priv->config.sf &&\n+\t\t !priv->representor) {\n+\t\t\tret = mlx5_get_flag_dropless_rq(dev);\n+\t\t\tif (ret < 0)\n+\t\t\t\tDRV_LOG(WARNING,\n+\t\t\t\t\t\"port %u cannot query dropless flag\",\n+\t\t\t\t\tdev->data->port_id);\n+\t\t\telse if (!ret)\n+\t\t\t\tDRV_LOG(WARNING,\n+\t\t\t\t\t\"port %u dropless_rq OFF, no rearming\",\n+\t\t\t\t\tdev->data->port_id);\n+\t\t} else {\n+\t\t\tDRV_LOG(DEBUG,\n+\t\t\t\t\"port %u doesn't support dropless_rq flag\",\n+\t\t\t\tdev->data->port_id);\n+\t\t}\n+\t}\n \tret = mlx5_rxq_start(dev);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"port %u Rx queue allocation failed: %s\",\ndiff --git a/drivers/net/mlx5/windows/mlx5_ethdev_os.c b/drivers/net/mlx5/windows/mlx5_ethdev_os.c\nindex fddc7a6b12..359f73df7c 100644\n--- a/drivers/net/mlx5/windows/mlx5_ethdev_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_ethdev_os.c\n@@ -389,3 +389,20 @@ mlx5_is_removed(struct rte_eth_dev *dev)\n \t\treturn 1;\n \treturn 0;\n }\n+\n+/*\n+ * Query dropless_rq private flag value provided by ETHTOOL.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ *\n+ * @return\n+ * - 0 on success, flag is not set.\n+ * - 1 on success, flag is set.\n+ * - negative errno value otherwise and rte_errno is set.\n+ */\n+int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+\treturn -ENOTSUP;\n+}\n", "prefixes": [ "v6", "2/2" ] }