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GET /api/patches/103770/?format=api
{ "id": 103770, "url": "https://patches.dpdk.org/api/patches/103770/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20211104140154.51122-2-bingz@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211104140154.51122-2-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211104140154.51122-2-bingz@nvidia.com", "date": "2021-11-04T14:01:53", "name": "[v2,1/2] net/mlx5: add support for Rx queue delay drop", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c2daec6804d98c74d725fc8babfe3aad7cb801b1", "submitter": { "id": 1976, "url": "https://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20211104140154.51122-2-bingz@nvidia.com/mbox/", "series": [ { "id": 20314, "url": "https://patches.dpdk.org/api/series/20314/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=20314", "date": "2021-11-04T14:01:52", "name": "Add delay drop support for Rx queue", "version": 2, "mbox": "https://patches.dpdk.org/series/20314/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/103770/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/103770/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5820AA0C41;\n\tThu, 4 Nov 2021 15:02:28 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6370242745;\n\tThu, 4 Nov 2021 15:02:25 +0100 (CET)", "from NAM02-BN1-obe.outbound.protection.outlook.com\n (mail-bn1nam07on2071.outbound.protection.outlook.com [40.107.212.71])\n by mails.dpdk.org (Postfix) with ESMTP id EADFA42742\n for <dev@dpdk.org>; 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mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=quarantine pct=100) action=none\n header.from=nvidia.com; dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=RNtRNDW8SBgDcDmY9+E2pmM0a+EZV6v/tmUT6LtHQ4g=;\n b=EjYkuu84TFLz94odIo4ZDMWABbHcGLklnC2Uc1HF5rPy1PdQYyn+tKwO7F7vxeicrbk32QKS8uGl1cCTNfsA7b+L4KfLqCkmPShkqg6lENTFxCSWUoDnw1nyhZjmZtuJ7lf5KTy7NgFHC/upHxefg5r1gu0TDBNq0H2IusU3quO7ktU6RXYAQx4EVAu2sr4/WgVVr6xJu19nF/3jeBAlTY1cJPvVFd3NAFoAqfzmf7ZoM7JsVMZdoG1jzI3DkOB+5k+rMU5NrEyn0sP2UFKXPfxwYVBOcE+r9t/Vth5+Kxxrx+Jn21bmmxzUlngHZyx+hCzFgz4FfNaLyJNPB3sZ4g==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed)\n header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>, <thomas@monjalon.net>,\n <orika@nvidia.com>", "Date": "Thu, 4 Nov 2021 16:01:53 +0200", "Message-ID": "<20211104140154.51122-2-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20211104140154.51122-1-bingz@nvidia.com>", "References": "<20211104112644.17278-1-bingz@nvidia.com>\n <20211104140154.51122-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "1551b4f2-1007-483e-e819-08d99f9bb82d", "X-MS-TrafficTypeDiagnostic": "BY5PR12MB3794:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BY5PR12MB37947C14F75F3D58FBBCAC21D08D9@BY5PR12MB3794.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:6790;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n GjODm8ydXoZx7w0TnGOAlWwCRLfmrfoYpCSWdm5COVIuMtJD05T2jdJLQRObL9BEHLPm0XuAJfiDF4pAyixPkVPBqhpjCmz2KYfnquNy3dgeaFDu2o7Wa5WnvzVwzMPxoQRzSjsoCF3Q3J7d97PREtC6RjIHi8jIiyYomdhQmxaEWj24jkw9ia+CKai3BFLkXfZMYBo4dR79lvdg4DFueguX8tl7hEnzKC7PUkmehMnurLdu8thMZEySR56tfDWmmJsj0KNQGM1HmHF55OyDzAJG3oVjAB7dJtPm8mDNtX+6+AkFbPs1LAjO7JzZwnEwvWvo1lRJzjsp9POfyGFyHcC1s96J5xrakcBjZvUTIP2vhhwMPoxQOwTDzs8oOf9JSo0CZ2TFHu/UQiHUp2m70xTpSYfxF+LS72iFLBgQ/Y6ZSbBYREaR1xymQLmnlrOHawQ3Am5wgACHH/t2/9Cxivi+YswiWQDzzrAs8aOD3fUsNkv7d8GSK4IA9sNDUg2fyOHIeDMJGHqOPS430nbIjpR/yhyCvijuCxOfgh6JS7+nlXkdfJR/nnGAYaK2zsxtMYIEGJ6DApHDg92NaRSFtujVgPV9ZRPhVwUr3FtqN8z8EYm1NNRiSsZ2VnrJMm/maFzyp4v/qJzPEuTpHHedpe4bRR1KqmWCUmdizOuyAIEMYLti8qdvQ6oLkxYU0LA7SKV8LNKV8CMJkM7foINuwJjQMU8a2lVMBUc6NjLzJa8=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(1076003)(7636003)(83380400001)(7696005)(82310400003)(4326008)(47076005)(5660300002)(2906002)(8676002)(356005)(70586007)(6666004)(70206006)(508600001)(86362001)(107886003)(36860700001)(6636002)(26005)(316002)(54906003)(110136005)(426003)(55016002)(6286002)(36756003)(16526019)(2616005)(8936002)(186003)(336012)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Nov 2021 14:02:20.5610 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 1551b4f2-1007-483e-e819-08d99f9bb82d", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT003.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB3794", "Subject": "[dpdk-dev] [PATCH v2 1/2] net/mlx5: add support for Rx queue delay\n drop", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "For an Ethernet RQ, packets received when receive WQEs are exhausted\nare dropped. This behavior prevents slow or malicious software\nentities at the host from affecting the network. While for hairpin\ncases, even if there is no software involved during the packet\nforwarding from Rx to Tx side, some hiccup in the hardware or back\npressure from Tx side may still cause the WQEs to be exhausted. In\ncertain scenarios it may be preferred to configure the device to\navoid such packet drops, assuming the posting of WQEs will resume\nshortly.\n\nTo support this, a new devarg \"delay_drop_en\" is introduced, by\ndefault, the delay drop is enabled for hairpin Rx queues and\ndisabled for standard Rx queues. This value is used as a bit mask:\n - bit 0: enablement of standard Rx queue\n - bit 1: enablement of hairpin Rx queue\nAnd this attribute will be applied to all Rx queues of a device.\n\nThe \"rq_delay_drop\" capability in the HCA_CAP is checked before\ncreating any queue. If the hardware capabilities do not support\nthis delay drop, all the Rx queues will still be created without\nthis attribute, and the devarg setting will be ignored even if it\nis specified explicitly.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 1 +\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n drivers/net/mlx5/linux/mlx5_os.c | 11 +++++++++++\n drivers/net/mlx5/mlx5.c | 7 +++++++\n drivers/net/mlx5/mlx5.h | 9 +++++++++\n drivers/net/mlx5/mlx5_devx.c | 5 +++++\n drivers/net/mlx5/mlx5_rx.h | 1 +\n 7 files changed, 35 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 12c114a91b..eaf1dd5046 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -962,6 +962,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n \t\t\t\t\t general_obj_types) &\n \t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);\n+\tattr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop);\n \tif (attr->qos.sup) {\n \t\thcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,\n \t\t\t\tMLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 2326f1e968..25e2814ac0 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -176,6 +176,7 @@ struct mlx5_hca_attr {\n \tuint32_t swp_csum:1;\n \tuint32_t swp_lso:1;\n \tuint32_t lro_max_msg_sz_mode:2;\n+\tuint32_t rq_delay_drop:1;\n \tuint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];\n \tuint16_t lro_min_mss_size;\n \tuint32_t flex_parser_protocols;\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex f51da8c3a3..e8894239ed 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1506,6 +1506,15 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tgoto error;\n #endif\n \t}\n+\tif (config->std_delay_drop || config->hp_delay_drop) {\n+\t\tif (!config->hca_attr.rq_delay_drop) {\n+\t\t\tconfig->std_delay_drop = 0;\n+\t\t\tconfig->hp_delay_drop = 0;\n+\t\t\tDRV_LOG(WARNING,\n+\t\t\t\t\"dev_port-%u: Rxq delay drop is not supported\",\n+\t\t\t\tpriv->dev_port);\n+\t\t}\n+\t}\n \tif (sh->devx) {\n \t\tuint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];\n \n@@ -2075,6 +2084,8 @@ mlx5_os_config_default(struct mlx5_dev_config *config)\n \tconfig->decap_en = 1;\n \tconfig->log_hp_size = MLX5_ARG_UNSET;\n \tconfig->allow_duplicate_pattern = 1;\n+\tconfig->std_delay_drop = 0;\n+\tconfig->hp_delay_drop = 0;\n }\n \n /**\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex dc15688f21..80a6692b94 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -183,6 +183,9 @@\n /* Device parameter to configure implicit registration of mempool memory. */\n #define MLX5_MR_MEMPOOL_REG_EN \"mr_mempool_reg_en\"\n \n+/* Device parameter to configure the delay drop when creating Rxqs. */\n+#define MLX5_DELAY_DROP_EN \"delay_drop_en\"\n+\n /* Shared memory between primary and secondary processes. */\n struct mlx5_shared_data *mlx5_shared_data;\n \n@@ -2095,6 +2098,9 @@ mlx5_args_check(const char *key, const char *val, void *opaque)\n \t\tconfig->decap_en = !!tmp;\n \t} else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {\n \t\tconfig->allow_duplicate_pattern = !!tmp;\n+\t} else if (strcmp(MLX5_DELAY_DROP_EN, key) == 0) {\n+\t\tconfig->std_delay_drop = tmp & MLX5_DELAY_DROP_STANDARD;\n+\t\tconfig->hp_delay_drop = tmp & MLX5_DELAY_DROP_HAIRPIN;\n \t} else {\n \t\tDRV_LOG(WARNING, \"%s: unknown parameter\", key);\n \t\trte_errno = EINVAL;\n@@ -2157,6 +2163,7 @@ mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)\n \t\tMLX5_DECAP_EN,\n \t\tMLX5_ALLOW_DUPLICATE_PATTERN,\n \t\tMLX5_MR_MEMPOOL_REG_EN,\n+\t\tMLX5_DELAY_DROP_EN,\n \t\tNULL,\n \t};\n \tstruct rte_kvargs *kvlist;\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 74af88ec19..8d32d55c9a 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -99,6 +99,13 @@ enum mlx5_flow_type {\n \tMLX5_FLOW_TYPE_MAXI,\n };\n \n+/* The mode of delay drop for Rx queues. */\n+enum mlx5_delay_drop_mode {\n+\tMLX5_DELAY_DROP_NONE = 0, /* All disabled. */\n+\tMLX5_DELAY_DROP_STANDARD = RTE_BIT32(0), /* Standard queues enable. */\n+\tMLX5_DELAY_DROP_HAIRPIN = RTE_BIT32(1), /* Hairpin queues enable. */\n+};\n+\n /* Hlist and list callback context. */\n struct mlx5_flow_cb_ctx {\n \tstruct rte_eth_dev *dev;\n@@ -264,6 +271,8 @@ struct mlx5_dev_config {\n \tunsigned int dv_miss_info:1; /* restore packet after partial hw miss */\n \tunsigned int allow_duplicate_pattern:1;\n \t/* Allow/Prevent the duplicate rules pattern. */\n+\tunsigned int std_delay_drop:1; /* Enable standard Rxq delay drop. */\n+\tunsigned int hp_delay_drop:1; /* Enable hairpin Rxq delay drop. */\n \tstruct {\n \t\tunsigned int enabled:1; /* Whether MPRQ is enabled. */\n \t\tunsigned int stride_num_n; /* Number of strides. */\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 424f77be79..2e1d849eab 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -280,6 +280,7 @@ mlx5_rxq_create_devx_rq_resources(struct rte_eth_dev *dev,\n \t\t\t\t\t\tMLX5_WQ_END_PAD_MODE_NONE;\n \trq_attr.wq_attr.pd = cdev->pdn;\n \trq_attr.counter_set_id = priv->counter_set_id;\n+\trq_attr.delay_drop_en = rxq_data->delay_drop;\n \t/* Create RQ using DevX API. */\n \treturn mlx5_devx_rq_create(cdev->ctx, &rxq_ctrl->obj->rq_obj, wqe_size,\n \t\t\t\t log_desc_n, &rq_attr, rxq_ctrl->socket);\n@@ -443,6 +444,8 @@ mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)\n \t\t\tattr.wq_attr.log_hairpin_data_sz -\n \t\t\tMLX5_HAIRPIN_QUEUE_STRIDE;\n \tattr.counter_set_id = priv->counter_set_id;\n+\trxq_data->delay_drop = priv->config.hp_delay_drop;\n+\tattr.delay_drop_en = priv->config.hp_delay_drop;\n \ttmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &attr,\n \t\t\t\t\t rxq_ctrl->socket);\n \tif (!tmpl->rq) {\n@@ -503,6 +506,7 @@ mlx5_rxq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n \t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n \t\tgoto error;\n \t}\n+\trxq_data->delay_drop = priv->config.std_delay_drop;\n \t/* Create RQ using DevX API. */\n \tret = mlx5_rxq_create_devx_rq_resources(dev, rxq_data);\n \tif (ret) {\n@@ -921,6 +925,7 @@ mlx5_rxq_devx_obj_drop_create(struct rte_eth_dev *dev)\n \trxq_ctrl->priv = priv;\n \trxq_ctrl->obj = rxq;\n \trxq_data = &rxq_ctrl->rxq;\n+\trxq_data->delay_drop = 0;\n \t/* Create CQ using DevX API. */\n \tret = mlx5_rxq_create_devx_cq_resources(dev, rxq_data);\n \tif (ret != 0) {\ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex 69b1263339..05807764b8 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -92,6 +92,7 @@ struct mlx5_rxq_data {\n \tunsigned int lro:1; /* Enable LRO. */\n \tunsigned int dynf_meta:1; /* Dynamic metadata is configured. */\n \tunsigned int mcqe_format:3; /* CQE compression format. */\n+\tunsigned int delay_drop:1; /* Enable delay drop. */\n \tvolatile uint32_t *rq_db;\n \tvolatile uint32_t *cq_db;\n \tuint16_t port_id;\n", "prefixes": [ "v2", "1/2" ] }